// SPDX-License-Identifier: GPL-2.0 /* * Intel Broxton SoC pinctrl/GPIO driver * * Copyright (C) 2015, 2016 Intel Corporation * Author: Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define BXT_PAD_OWN 0x020#define BXT_PADCFGLOCK 0x060#define BXT_HOSTSW_OWN 0x080#define BXT_GPI_IS 0x100#define BXT_GPI_IE 0x110#define BXT_COMMUNITY(b, s, e) \/* BXT */ static const struct pinctrl_pin_desc bxt_north_pins[] = {"GPIO_0" ),"GPIO_1" ),"GPIO_2" ),"GPIO_3" ),"GPIO_4" ),"GPIO_5" ),"GPIO_6" ),"GPIO_7" ),"GPIO_8" ),"GPIO_9" ),"GPIO_10" ),"GPIO_11" ),"GPIO_12" ),"GPIO_13" ),"GPIO_14" ),"GPIO_15" ),"GPIO_16" ),"GPIO_17" ),"GPIO_18" ),"GPIO_19" ),"GPIO_20" ),"GPIO_21" ),"GPIO_22" ),"GPIO_23" ),"GPIO_24" ),"GPIO_25" ),"GPIO_26" ),"GPIO_27" ),"GPIO_28" ),"GPIO_29" ),"GPIO_30" ),"GPIO_31" ),"GPIO_32" ),"GPIO_33" ),"PWM0" ),"PWM1" ),"PWM2" ),"PWM3" ),"LPSS_UART0_RXD" ),"LPSS_UART0_TXD" ),"LPSS_UART0_RTS_B" ),"LPSS_UART0_CTS_B" ),"LPSS_UART1_RXD" ),"LPSS_UART1_TXD" ),"LPSS_UART1_RTS_B" ),"LPSS_UART1_CTS_B" ),"LPSS_UART2_RXD" ),"LPSS_UART2_TXD" ),"LPSS_UART2_RTS_B" ),"LPSS_UART2_CTS_B" ),"ISH_UART0_RXD" ),"ISH_UART0_TXT" ),"ISH_UART0_RTS_B" ),"ISH_UART0_CTS_B" ),"ISH_UART1_RXD" ),"ISH_UART1_TXT" ),"ISH_UART1_RTS_B" ),"ISH_UART1_CTS_B" ),"ISH_UART2_RXD" ),"ISH_UART2_TXD" ),"ISH_UART2_RTS_B" ),"ISH_UART2_CTS_B" ),"GP_CAMERASB00" ),"GP_CAMERASB01" ),"GP_CAMERASB02" ),"GP_CAMERASB03" ),"GP_CAMERASB04" ),"GP_CAMERASB05" ),"GP_CAMERASB06" ),"GP_CAMERASB07" ),"GP_CAMERASB08" ),"GP_CAMERASB09" ),"GP_CAMERASB10" ),"GP_CAMERASB11" ),"TCK" ),"TRST_B" ),"TMS" ),"TDI" ),"CX_PMODE" ),"CX_PREQ_B" ),"JTAGX" ),"CX_PRDY_B" ),"TDO" ),static const unsigned int bxt_north_pwm0_pins[] = { 34 };static const unsigned int bxt_north_pwm1_pins[] = { 35 };static const unsigned int bxt_north_pwm2_pins[] = { 36 };static const unsigned int bxt_north_pwm3_pins[] = { 37 };static const unsigned int bxt_north_uart0_pins[] = { 38, 39, 40, 41 };static const unsigned int bxt_north_uart1_pins[] = { 42, 43, 44, 45 };static const unsigned int bxt_north_uart2_pins[] = { 46, 47, 48, 49 };static const unsigned int bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };static const unsigned int bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };static const unsigned int bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };static const unsigned int bxt_north_uart3_pins[] = { 58, 59, 60, 61 };static const struct intel_pingroup bxt_north_groups[] = {"pwm0_grp" , bxt_north_pwm0_pins, 1),"pwm1_grp" , bxt_north_pwm1_pins, 1),"pwm2_grp" , bxt_north_pwm2_pins, 1),"pwm3_grp" , bxt_north_pwm3_pins, 1),"uart0_grp" , bxt_north_uart0_pins, 1),"uart1_grp" , bxt_north_uart1_pins, 1),"uart2_grp" , bxt_north_uart2_pins, 1),"uart0b_grp" , bxt_north_uart0b_pins, 2),"uart1b_grp" , bxt_north_uart1b_pins, 2),"uart2b_grp" , bxt_north_uart2b_pins, 2),"uart3_grp" , bxt_north_uart3_pins, 3),static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };static const char * const bxt_north_uart0_groups[] = {"uart0_grp" , "uart0b_grp" ,static const char * const bxt_north_uart1_groups[] = {"uart1_grp" , "uart1b_grp" ,static const char * const bxt_north_uart2_groups[] = {"uart2_grp" , "uart2b_grp" ,static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };static const struct intel_function bxt_north_functions[] = {"pwm0" , bxt_north_pwm0_groups),"pwm1" , bxt_north_pwm1_groups),"pwm2" , bxt_north_pwm2_groups),"pwm3" , bxt_north_pwm3_groups),"uart0" , bxt_north_uart0_groups),"uart1" , bxt_north_uart1_groups),"uart2" , bxt_north_uart2_groups),"uart3" , bxt_north_uart3_groups),static const struct intel_community bxt_north_communities[] = {static const struct intel_pinctrl_soc_data bxt_north_soc_data = {"1" ,static const struct pinctrl_pin_desc bxt_northwest_pins[] = {"PMC_SPI_FS0" ),"PMC_SPI_FS1" ),"PMC_SPI_FS2" ),"PMC_SPI_RXD" ),"PMC_SPI_TXD" ),"PMC_SPI_CLK" ),"PMC_UART_RXD" ),"PMC_UART_TXD" ),"PMIC_PWRGOOD" ),"PMIC_RESET_B" ),"RTC_CLK" ),"PMIC_SDWN_B" ),"PMIC_BCUDISW2" ),"PMIC_BCUDISCRIT" ),"PMIC_THERMTRIP_B" ),"PMIC_STDBY" ),"SVID0_ALERT_B" ),"SVID0_DATA" ),"SVID0_CLK" ),"PMIC_I2C_SCL" ),"PMIC_I2C_SDA" ),"AVS_I2S1_MCLK" ),"AVS_I2S1_BCLK" ),"AVS_I2S1_WS_SYNC" ),"AVS_I2S1_SDI" ),"AVS_I2S1_SDO" ),"AVS_M_CLK_A1" ),"AVS_M_CLK_B1" ),"AVS_M_DATA_1" ),"AVS_M_CLK_AB2" ),"AVS_M_DATA_2" ),"AVS_I2S2_MCLK" ),"AVS_I2S2_BCLK" ),"AVS_I2S2_WS_SYNC" ),"AVS_I2S2_SDI" ),"AVS_I2S2_SDOK" ),"AVS_I2S3_BCLK" ),"AVS_I2S3_WS_SYNC" ),"AVS_I2S3_SDI" ),"AVS_I2S3_SDO" ),"AVS_I2S4_BCLK" ),"AVS_I2S4_WS_SYNC" ),"AVS_I2S4_SDI" ),"AVS_I2S4_SDO" ),"PROCHOT_B" ),"FST_SPI_CS0_B" ),"FST_SPI_CS1_B" ),"FST_SPI_MOSI_IO0" ),"FST_SPI_MISO_IO1" ),"FST_SPI_IO2" ),"FST_SPI_IO3" ),"FST_SPI_CLK" ),"FST_SPI_CLK_FB" ),"GP_SSP_0_CLK" ),"GP_SSP_0_FS0" ),"GP_SSP_0_FS1" ),"GP_SSP_0_FS2" ),"GP_SSP_0_RXD" ),"GP_SSP_0_TXD" ),"GP_SSP_1_CLK" ),"GP_SSP_1_FS0" ),"GP_SSP_1_FS1" ),"GP_SSP_1_FS2" ),"GP_SSP_1_FS3" ),"GP_SSP_1_RXD" ),"GP_SSP_1_TXD" ),"GP_SSP_2_CLK" ),"GP_SSP_2_FS0" ),"GP_SSP_2_FS1" ),"GP_SSP_2_FS2" ),"GP_SSP_2_RXD" ),"GP_SSP_2_TXD" ),static const unsigned int bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };static const unsigned int bxt_northwest_ssp1_pins[] = {static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };static const struct intel_pingroup bxt_northwest_groups[] = {"ssp0_grp" , bxt_northwest_ssp0_pins, 1),"ssp1_grp" , bxt_northwest_ssp1_pins, 1),"ssp2_grp" , bxt_northwest_ssp2_pins, 1),"uart3_grp" , bxt_northwest_uart3_pins, 2),static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };static const struct intel_function bxt_northwest_functions[] = {"ssp0" , bxt_northwest_ssp0_groups),"ssp1" , bxt_northwest_ssp1_groups),"ssp2" , bxt_northwest_ssp2_groups),"uart3" , bxt_northwest_uart3_groups),static const struct intel_community bxt_northwest_communities[] = {static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {"2" ,static const struct pinctrl_pin_desc bxt_west_pins[] = {"LPSS_I2C0_SDA" ),"LPSS_I2C0_SCL" ),"LPSS_I2C1_SDA" ),"LPSS_I2C1_SCL" ),"LPSS_I2C2_SDA" ),"LPSS_I2C2_SCL" ),"LPSS_I2C3_SDA" ),"LPSS_I2C3_SCL" ),"LPSS_I2C4_SDA" ),"LPSS_I2C4_SCL" ),"LPSS_I2C5_SDA" ),"LPSS_I2C5_SCL" ),"LPSS_I2C6_SDA" ),"LPSS_I2C6_SCL" ),"LPSS_I2C7_SDA" ),"LPSS_I2C7_SCL" ),"ISH_I2C0_SDA" ),"ISH_I2C0_SCL" ),"ISH_I2C1_SDA" ),"ISH_I2C1_SCL" ),"ISH_I2C2_SDA" ),"ISH_I2C2_SCL" ),"ISH_GPIO_0" ),"ISH_GPIO_1" ),"ISH_GPIO_2" ),"ISH_GPIO_3" ),"ISH_GPIO_4" ),"ISH_GPIO_5" ),"ISH_GPIO_6" ),"ISH_GPIO_7" ),"ISH_GPIO_8" ),"ISH_GPIO_9" ),"MODEM_CLKREQ" ),"DGCLKDBG_PMC_0" ),"DGCLKDBG_PMC_1" ),"DGCLKDBG_PMC_2" ),"DGCLKDBG_ICLK_0" ),"DGCLKDBG_ICLK_1" ),"OSC_CLK_OUT_0" ),"OSC_CLK_OUT_1" ),"OSC_CLK_OUT_2" ),"OSC_CLK_OUT_3" ),static const unsigned int bxt_west_i2c0_pins[] = { 0, 1 };static const unsigned int bxt_west_i2c1_pins[] = { 2, 3 };static const unsigned int bxt_west_i2c2_pins[] = { 4, 5 };static const unsigned int bxt_west_i2c3_pins[] = { 6, 7 };static const unsigned int bxt_west_i2c4_pins[] = { 8, 9 };static const unsigned int bxt_west_i2c5_pins[] = { 10, 11 };static const unsigned int bxt_west_i2c6_pins[] = { 12, 13 };static const unsigned int bxt_west_i2c7_pins[] = { 14, 15 };static const unsigned int bxt_west_i2c5b_pins[] = { 16, 17 };static const unsigned int bxt_west_i2c6b_pins[] = { 18, 19 };static const unsigned int bxt_west_i2c7b_pins[] = { 20, 21 };static const struct intel_pingroup bxt_west_groups[] = {"i2c0_grp" , bxt_west_i2c0_pins, 1),"i2c1_grp" , bxt_west_i2c1_pins, 1),"i2c2_grp" , bxt_west_i2c2_pins, 1),"i2c3_grp" , bxt_west_i2c3_pins, 1),"i2c4_grp" , bxt_west_i2c4_pins, 1),"i2c5_grp" , bxt_west_i2c5_pins, 1),"i2c6_grp" , bxt_west_i2c6_pins, 1),"i2c7_grp" , bxt_west_i2c7_pins, 1),"i2c5b_grp" , bxt_west_i2c5b_pins, 2),"i2c6b_grp" , bxt_west_i2c6b_pins, 2),"i2c7b_grp" , bxt_west_i2c7b_pins, 2),static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp" , "i2c5b_grp" };static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp" , "i2c6b_grp" };static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp" , "i2c7b_grp" };static const struct intel_function bxt_west_functions[] = {"i2c0" , bxt_west_i2c0_groups),"i2c1" , bxt_west_i2c1_groups),"i2c2" , bxt_west_i2c2_groups),"i2c3" , bxt_west_i2c3_groups),"i2c4" , bxt_west_i2c4_groups),"i2c5" , bxt_west_i2c5_groups),"i2c6" , bxt_west_i2c6_groups),"i2c7" , bxt_west_i2c7_groups),static const struct intel_community bxt_west_communities[] = {static const struct intel_pinctrl_soc_data bxt_west_soc_data = {"3" ,static const struct pinctrl_pin_desc bxt_southwest_pins[] = {"EMMC0_CLK" ),"EMMC0_D0" ),"EMMC0_D1" ),"EMMC0_D2" ),"EMMC0_D3" ),"EMMC0_D4" ),"EMMC0_D5" ),"EMMC0_D6" ),"EMMC0_D7" ),"EMMC0_CMD" ),"SDIO_CLK" ),"SDIO_D0" ),"SDIO_D1" ),"SDIO_D2" ),"SDIO_D3" ),"SDIO_CMD" ),"SDCARD_CLK" ),"SDCARD_D0" ),"SDCARD_D1" ),"SDCARD_D2" ),"SDCARD_D3" ),"SDCARD_CD_B" ),"SDCARD_CMD" ),"SDCARD_LVL_CLK_FB" ),"SDCARD_LVL_CMD_DIR" ),"SDCARD_LVL_DAT_DIR" ),"EMMC0_STROBE" ),"SDIO_PWR_DOWN_B" ),"SDCARD_PWR_DOWN_B" ),"SDCARD_LVL_SEL" ),"SDCARD_LVL_WP" ),static const unsigned int bxt_southwest_emmc0_pins[] = {static const unsigned int bxt_southwest_sdio_pins[] = {static const unsigned int bxt_southwest_sdcard_pins[] = {static const struct intel_pingroup bxt_southwest_groups[] = {"emmc0_grp" , bxt_southwest_emmc0_pins, 1),"sdio_grp" , bxt_southwest_sdio_pins, 1),"sdcard_grp" , bxt_southwest_sdcard_pins, 1),static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };static const struct intel_function bxt_southwest_functions[] = {"emmc0" , bxt_southwest_emmc0_groups),"sdio" , bxt_southwest_sdio_groups),"sdcard" , bxt_southwest_sdcard_groups),static const struct intel_community bxt_southwest_communities[] = {static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {"4" ,static const struct pinctrl_pin_desc bxt_south_pins[] = {"HV_DDI0_DDC_SDA" ),"HV_DDI0_DDC_SCL" ),"HV_DDI1_DDC_SDA" ),"HV_DDI1_DDC_SCL" ),"DBI_SDA" ),"DBI_SCL" ),"PANEL0_VDDEN" ),"PANEL0_BKLTEN" ),"PANEL0_BKLTCTL" ),"PANEL1_VDDEN" ),"PANEL1_BKLTEN" ),"PANEL1_BKLTCTL" ),"DBI_CSX" ),"DBI_RESX" ),"GP_INTD_DSI_TE1" ),"GP_INTD_DSI_TE2" ),"USB_OC0_B" ),"USB_OC1_B" ),"MEX_WAKE0_B" ),"MEX_WAKE1_B" ),static const struct intel_community bxt_south_communities[] = {static const struct intel_pinctrl_soc_data bxt_south_soc_data = {"5" ,static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {/* APL */ static const struct pinctrl_pin_desc apl_north_pins[] = {"GPIO_0" ),"GPIO_1" ),"GPIO_2" ),"GPIO_3" ),"GPIO_4" ),"GPIO_5" ),"GPIO_6" ),"GPIO_7" ),"GPIO_8" ),"GPIO_9" ),"GPIO_10" ),"GPIO_11" ),"GPIO_12" ),"GPIO_13" ),"GPIO_14" ),"GPIO_15" ),"GPIO_16" ),"GPIO_17" ),"GPIO_18" ),"GPIO_19" ),"GPIO_20" ),"GPIO_21" ),"GPIO_22" ),"GPIO_23" ),"GPIO_24" ),"GPIO_25" ),"GPIO_26" ),"GPIO_27" ),"GPIO_28" ),"GPIO_29" ),"GPIO_30" ),"GPIO_31" ),"GPIO_32" ),"GPIO_33" ),"PWM0" ),"PWM1" ),"PWM2" ),"PWM3" ),"LPSS_UART0_RXD" ),"LPSS_UART0_TXD" ),"LPSS_UART0_RTS_B" ),"LPSS_UART0_CTS_B" ),"LPSS_UART1_RXD" ),"LPSS_UART1_TXD" ),"LPSS_UART1_RTS_B" ),"LPSS_UART1_CTS_B" ),"LPSS_UART2_RXD" ),"LPSS_UART2_TXD" ),"LPSS_UART2_RTS_B" ),"LPSS_UART2_CTS_B" ),"GP_CAMERASB00" ),"GP_CAMERASB01" ),"GP_CAMERASB02" ),"GP_CAMERASB03" ),"GP_CAMERASB04" ),"GP_CAMERASB05" ),"GP_CAMERASB06" ),"GP_CAMERASB07" ),"GP_CAMERASB08" ),"GP_CAMERASB09" ),"GP_CAMERASB10" ),"GP_CAMERASB11" ),"TCK" ),"TRST_B" ),"TMS" ),"TDI" ),"CX_PMODE" ),"CX_PREQ_B" ),"JTAGX" ),"CX_PRDY_B" ),"TDO" ),"CNV_BRI_DT" ),"CNV_BRI_RSP" ),"CNV_RGI_DT" ),"CNV_RGI_RSP" ),"SVID0_ALERT_B" ),"SVID0_DATA" ),"SVID0_CLK" ),static const unsigned int apl_north_pwm0_pins[] = { 34 };static const unsigned int apl_north_pwm1_pins[] = { 35 };static const unsigned int apl_north_pwm2_pins[] = { 36 };static const unsigned int apl_north_pwm3_pins[] = { 37 };static const unsigned int apl_north_uart0_pins[] = { 38, 39, 40, 41 };static const unsigned int apl_north_uart1_pins[] = { 42, 43, 44, 45 };static const unsigned int apl_north_uart2_pins[] = { 46, 47, 48, 49 };static const struct intel_pingroup apl_north_groups[] = {"pwm0_grp" , apl_north_pwm0_pins, 1),"pwm1_grp" , apl_north_pwm1_pins, 1),"pwm2_grp" , apl_north_pwm2_pins, 1),"pwm3_grp" , apl_north_pwm3_pins, 1),"uart0_grp" , apl_north_uart0_pins, 1),"uart1_grp" , apl_north_uart1_pins, 1),"uart2_grp" , apl_north_uart2_pins, 1),static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };static const char * const apl_north_uart0_groups[] = { "uart0_grp" };static const char * const apl_north_uart1_groups[] = { "uart1_grp" };static const char * const apl_north_uart2_groups[] = { "uart2_grp" };static const struct intel_function apl_north_functions[] = {"pwm0" , apl_north_pwm0_groups),"pwm1" , apl_north_pwm1_groups),"pwm2" , apl_north_pwm2_groups),"pwm3" , apl_north_pwm3_groups),"uart0" , apl_north_uart0_groups),"uart1" , apl_north_uart1_groups),"uart2" , apl_north_uart2_groups),static const struct intel_community apl_north_communities[] = {static const struct intel_pinctrl_soc_data apl_north_soc_data = {"1" ,static const struct pinctrl_pin_desc apl_northwest_pins[] = {"HV_DDI0_DDC_SDA" ),"HV_DDI0_DDC_SCL" ),"HV_DDI1_DDC_SDA" ),"HV_DDI1_DDC_SCL" ),"DBI_SDA" ),"DBI_SCL" ),"PANEL0_VDDEN" ),"PANEL0_BKLTEN" ),"PANEL0_BKLTCTL" ),"PANEL1_VDDEN" ),"PANEL1_BKLTEN" ),"PANEL1_BKLTCTL" ),"DBI_CSX" ),"DBI_RESX" ),"GP_INTD_DSI_TE1" ),"GP_INTD_DSI_TE2" ),"USB_OC0_B" ),"USB_OC1_B" ),"PMC_SPI_FS0" ),"PMC_SPI_FS1" ),"PMC_SPI_FS2" ),"PMC_SPI_RXD" ),"PMC_SPI_TXD" ),"PMC_SPI_CLK" ),"PMIC_PWRGOOD" ),"PMIC_RESET_B" ),"PMIC_SDWN_B" ),"PMIC_BCUDISW2" ),"PMIC_BCUDISCRIT" ),"PMIC_THERMTRIP_B" ),"PMIC_STDBY" ),"PROCHOT_B" ),"PMIC_I2C_SCL" ),"PMIC_I2C_SDA" ),"AVS_I2S1_MCLK" ),"AVS_I2S1_BCLK" ),"AVS_I2S1_WS_SYNC" ),"AVS_I2S1_SDI" ),"AVS_I2S1_SDO" ),"AVS_M_CLK_A1" ),"AVS_M_CLK_B1" ),"AVS_M_DATA_1" ),"AVS_M_CLK_AB2" ),"AVS_M_DATA_2" ),"AVS_I2S2_MCLK" ),"AVS_I2S2_BCLK" ),"AVS_I2S2_WS_SYNC" ),"AVS_I2S2_SDI" ),"AVS_I2S2_SDO" ),"AVS_I2S3_BCLK" ),"AVS_I2S3_WS_SYNC" ),"AVS_I2S3_SDI" ),"AVS_I2S3_SDO" ),"FST_SPI_CS0_B" ),"FST_SPI_CS1_B" ),"FST_SPI_MOSI_IO0" ),"FST_SPI_MISO_IO1" ),"FST_SPI_IO2" ),"FST_SPI_IO3" ),"FST_SPI_CLK" ),"FST_SPI_CLK_FB" ),"GP_SSP_0_CLK" ),"GP_SSP_0_FS0" ),"GP_SSP_0_FS1" ),"GP_SSP_0_RXD" ),"GP_SSP_0_TXD" ),"GP_SSP_1_CLK" ),"GP_SSP_1_FS0" ),"GP_SSP_1_FS1" ),"GP_SSP_1_RXD" ),"GP_SSP_1_TXD" ),"GP_SSP_2_CLK" ),"GP_SSP_2_FS0" ),"GP_SSP_2_FS1" ),"GP_SSP_2_FS2" ),"GP_SSP_2_RXD" ),"GP_SSP_2_TXD" ),static const unsigned int apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };static const unsigned int apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };static const struct intel_pingroup apl_northwest_groups[] = {"ssp0_grp" , apl_northwest_ssp0_pins, 1),"ssp1_grp" , apl_northwest_ssp1_pins, 1),"ssp2_grp" , apl_northwest_ssp2_pins, 1),"uart3_grp" , apl_northwest_uart3_pins, 2),static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };static const struct intel_function apl_northwest_functions[] = {"ssp0" , apl_northwest_ssp0_groups),"ssp1" , apl_northwest_ssp1_groups),"ssp2" , apl_northwest_ssp2_groups),"uart3" , apl_northwest_uart3_groups),static const struct intel_community apl_northwest_communities[] = {static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {"2" ,static const struct pinctrl_pin_desc apl_west_pins[] = {"LPSS_I2C0_SDA" ),"LPSS_I2C0_SCL" ),"LPSS_I2C1_SDA" ),"LPSS_I2C1_SCL" ),"LPSS_I2C2_SDA" ),"LPSS_I2C2_SCL" ),"LPSS_I2C3_SDA" ),"LPSS_I2C3_SCL" ),"LPSS_I2C4_SDA" ),"LPSS_I2C4_SCL" ),"LPSS_I2C5_SDA" ),"LPSS_I2C5_SCL" ),"LPSS_I2C6_SDA" ),"LPSS_I2C6_SCL" ),"LPSS_I2C7_SDA" ),"LPSS_I2C7_SCL" ),"ISH_GPIO_0" ),"ISH_GPIO_1" ),"ISH_GPIO_2" ),"ISH_GPIO_3" ),"ISH_GPIO_4" ),"ISH_GPIO_5" ),"ISH_GPIO_6" ),"ISH_GPIO_7" ),"ISH_GPIO_8" ),"ISH_GPIO_9" ),"PCIE_CLKREQ0_B" ),"PCIE_CLKREQ1_B" ),"PCIE_CLKREQ2_B" ),"PCIE_CLKREQ3_B" ),"OSC_CLK_OUT_0" ),"OSC_CLK_OUT_1" ),"OSC_CLK_OUT_2" ),"OSC_CLK_OUT_3" ),"OSC_CLK_OUT_4" ),"PMU_AC_PRESENT" ),"PMU_BATLOW_B" ),"PMU_PLTRST_B" ),"PMU_PWRBTN_B" ),"PMU_RESETBUTTON_B" ),"PMU_SLP_S0_B" ),"PMU_SLP_S3_B" ),"PMU_SLP_S4_B" ),"PMU_SUSCLK" ),"PMU_WAKE_B" ),"SUS_STAT_B" ),"SUSPWRDNACK" ),static const unsigned int apl_west_i2c0_pins[] = { 0, 1 };static const unsigned int apl_west_i2c1_pins[] = { 2, 3 };static const unsigned int apl_west_i2c2_pins[] = { 4, 5 };static const unsigned int apl_west_i2c3_pins[] = { 6, 7 };static const unsigned int apl_west_i2c4_pins[] = { 8, 9 };static const unsigned int apl_west_i2c5_pins[] = { 10, 11 };static const unsigned int apl_west_i2c6_pins[] = { 12, 13 };static const unsigned int apl_west_i2c7_pins[] = { 14, 15 };static const unsigned int apl_west_uart2_pins[] = { 20, 21, 22, 34 };static const struct intel_pingroup apl_west_groups[] = {"i2c0_grp" , apl_west_i2c0_pins, 1),"i2c1_grp" , apl_west_i2c1_pins, 1),"i2c2_grp" , apl_west_i2c2_pins, 1),"i2c3_grp" , apl_west_i2c3_pins, 1),"i2c4_grp" , apl_west_i2c4_pins, 1),"i2c5_grp" , apl_west_i2c5_pins, 1),"i2c6_grp" , apl_west_i2c6_pins, 1),"i2c7_grp" , apl_west_i2c7_pins, 1),"uart2_grp" , apl_west_uart2_pins, 3),static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };static const char * const apl_west_uart2_groups[] = { "uart2_grp" };static const struct intel_function apl_west_functions[] = {"i2c0" , apl_west_i2c0_groups),"i2c1" , apl_west_i2c1_groups),"i2c2" , apl_west_i2c2_groups),"i2c3" , apl_west_i2c3_groups),"i2c4" , apl_west_i2c4_groups),"i2c5" , apl_west_i2c5_groups),"i2c6" , apl_west_i2c6_groups),"i2c7" , apl_west_i2c7_groups),"uart2" , apl_west_uart2_groups),static const struct intel_community apl_west_communities[] = {static const struct intel_pinctrl_soc_data apl_west_soc_data = {"3" ,static const struct pinctrl_pin_desc apl_southwest_pins[] = {"PCIE_WAKE0_B" ),"PCIE_WAKE1_B" ),"PCIE_WAKE2_B" ),"PCIE_WAKE3_B" ),"EMMC0_CLK" ),"EMMC0_D0" ),"EMMC0_D1" ),"EMMC0_D2" ),"EMMC0_D3" ),"EMMC0_D4" ),"EMMC0_D5" ),"EMMC0_D6" ),"EMMC0_D7" ),"EMMC0_CMD" ),"SDIO_CLK" ),"SDIO_D0" ),"SDIO_D1" ),"SDIO_D2" ),"SDIO_D3" ),"SDIO_CMD" ),"SDCARD_CLK" ),"SDCARD_CLK_FB" ),"SDCARD_D0" ),"SDCARD_D1" ),"SDCARD_D2" ),"SDCARD_D3" ),"SDCARD_CD_B" ),"SDCARD_CMD" ),"SDCARD_LVL_WP" ),"EMMC0_STROBE" ),"SDIO_PWR_DOWN_B" ),"SMB_ALERTB" ),"SMB_CLK" ),"SMB_DATA" ),"LPC_ILB_SERIRQ" ),"LPC_CLKOUT0" ),"LPC_CLKOUT1" ),"LPC_AD0" ),"LPC_AD1" ),"LPC_AD2" ),"LPC_AD3" ),"LPC_CLKRUNB" ),"LPC_FRAMEB" ),static const unsigned int apl_southwest_emmc0_pins[] = {static const unsigned int apl_southwest_sdio_pins[] = {static const unsigned int apl_southwest_sdcard_pins[] = {static const unsigned int apl_southwest_i2c7_pins[] = { 32, 33 };static const struct intel_pingroup apl_southwest_groups[] = {"emmc0_grp" , apl_southwest_emmc0_pins, 1),"sdio_grp" , apl_southwest_sdio_pins, 1),"sdcard_grp" , apl_southwest_sdcard_pins, 1),"i2c7_grp" , apl_southwest_i2c7_pins, 2),static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };static const struct intel_function apl_southwest_functions[] = {"emmc0" , apl_southwest_emmc0_groups),"sdio" , apl_southwest_sdio_groups),"sdcard" , apl_southwest_sdcard_groups),"i2c7" , apl_southwest_i2c7_groups),static const struct intel_community apl_southwest_communities[] = {static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {"4" ,static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {"INT3452" , (kernel_ulong_t)apl_pinctrl_soc_data },"INT34D1" , (kernel_ulong_t)bxt_pinctrl_soc_data },static const struct platform_device_id bxt_pinctrl_platform_ids[] = {"apollolake-pinctrl" , (kernel_ulong_t)apl_pinctrl_soc_data },"broxton-pinctrl" , (kernel_ulong_t)bxt_pinctrl_soc_data },static struct platform_driver bxt_pinctrl_driver = {"broxton-pinctrl" ,static int __init bxt_pinctrl_init(void )return platform_driver_register(&bxt_pinctrl_driver);static void __exit bxt_pinctrl_exit(void )"Mika Westerberg " );"Intel Broxton SoC pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 C=96 H=95 G=95
¤ Dauer der Verarbeitung: 0.16 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
