// SPDX-License-Identifier: GPL-2.0 /* * Intel Ice Lake PCH pinctrl/GPIO driver * * Copyright (C) 2018, 2022 Intel Corporation * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> * Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/acpi.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define ICL_LP_PAD_OWN 0x020#define ICL_LP_PADCFGLOCK 0x080#define ICL_LP_HOSTSW_OWN 0x0b0#define ICL_LP_GPI_IS 0x100#define ICL_LP_GPI_IE 0x110#define ICL_N_PAD_OWN 0x020#define ICL_N_PADCFGLOCK 0x080#define ICL_N_HOSTSW_OWN 0x0b0#define ICL_N_GPI_IS 0x100#define ICL_N_GPI_IE 0x120#define ICL_GPP(r, s, e, g) \#define ICL_LP_COMMUNITY(b, s, e, g) \#define ICL_N_COMMUNITY(b, s, e, g) \/* Ice Lake-LP */ static const struct pinctrl_pin_desc icllp_pins[] = {/* GPP_G */ "SD3_CMD" ),"SD3_D0" ),"SD3_D1" ),"SD3_D2" ),"SD3_D3" ),"SD3_CDB" ),"SD3_CLK" ),"SD3_WP" ),/* GPP_B */ "CORE_VID_0" ),"CORE_VID_1" ),"VRALERTB" ),"CPU_GP_2" ),"CPU_GP_3" ),"ISH_I2C0_SDA" ),"ISH_I2C0_SCL" ),"ISH_I2C1_SDA" ),"ISH_I2C1_SCL" ),"I2C5_SDA" ),"I2C5_SCL" ),"PMCALERTB" ),"SLP_S0B" ),"PLTRSTB" ),"SPKR" ),"GSPI0_CS0B" ),"GSPI0_CLK" ),"GSPI0_MISO" ),"GSPI0_MOSI" ),"GSPI1_CS0B" ),"GSPI1_CLK" ),"GSPI1_MISO" ),"GSPI1_MOSI" ),"SML1ALERTB" ),"GSPI0_CLK_LOOPBK" ),"GSPI1_CLK_LOOPBK" ),/* GPP_A */ "ESPI_IO_0" ),"ESPI_IO_1" ),"ESPI_IO_2" ),"ESPI_IO_3" ),"ESPI_CSB" ),"ESPI_CLK" ),"ESPI_RESETB" ),"I2S2_SCLK" ),"I2S2_SFRM" ),"I2S2_TXD" ),"I2S2_RXD" ),"SATA_DEVSLP_2" ),"SATAXPCIE_1" ),"SATAXPCIE_2" ),"USB2_OCB_1" ),"USB2_OCB_2" ),"USB2_OCB_3" ),"DDSP_HPD_C" ),"DDSP_HPD_B" ),"DDSP_HPD_1" ),"DDSP_HPD_2" ),"I2S5_TXD" ),"I2S5_RXD" ),"I2S1_SCLK" ),"ESPI_CLK_LOOPBK" ),/* GPP_H */ "SD_1P8_SEL" ),"SD_PWR_EN_B" ),"GPPC_H_2" ),"SX_EXIT_HOLDOFFB" ),"I2C2_SDA" ),"I2C2_SCL" ),"I2C3_SDA" ),"I2C3_SCL" ),"I2C4_SDA" ),"I2C4_SCL" ),"SRCCLKREQB_4" ),"SRCCLKREQB_5" ),"M2_SKT2_CFG_0" ),"M2_SKT2_CFG_1" ),"M2_SKT2_CFG_2" ),"M2_SKT2_CFG_3" ),"DDPB_CTRLCLK" ),"DDPB_CTRLDATA" ),"CPU_VCCIO_PWR_GATEB" ),"TIME_SYNC_0" ),"IMGCLKOUT_1" ),"IMGCLKOUT_2" ),"IMGCLKOUT_3" ),"IMGCLKOUT_4" ),/* GPP_D */ "ISH_GP_0" ),"ISH_GP_1" ),"ISH_GP_2" ),"ISH_GP_3" ),"IMGCLKOUT_0" ),"SRCCLKREQB_0" ),"SRCCLKREQB_1" ),"SRCCLKREQB_2" ),"SRCCLKREQB_3" ),"ISH_SPI_CSB" ),"ISH_SPI_CLK" ),"ISH_SPI_MISO" ),"ISH_SPI_MOSI" ),"ISH_UART0_RXD" ),"ISH_UART0_TXD" ),"ISH_UART0_RTSB" ),"ISH_UART0_CTSB" ),"ISH_GP_4" ),"ISH_GP_5" ),"I2S_MCLK" ),"GSPI2_CLK_LOOPBK" ),/* GPP_F */ "CNV_BRI_DT" ),"CNV_BRI_RSP" ),"CNV_RGI_DT" ),"CNV_RGI_RSP" ),"CNV_RF_RESET_B" ),"EMMC_HIP_MON" ),"CNV_PA_BLANKING" ),"EMMC_CMD" ),"EMMC_DATA0" ),"EMMC_DATA1" ),"EMMC_DATA2" ),"EMMC_DATA3" ),"EMMC_DATA4" ),"EMMC_DATA5" ),"EMMC_DATA6" ),"EMMC_DATA7" ),"EMMC_RCLK" ),"EMMC_CLK" ),"EMMC_RESETB" ),"A4WP_PRESENT" ),/* vGPIO */ "CNV_BTEN" ),"CNV_WCEN" ),"CNV_BT_HOST_WAKEB" ),"CNV_BT_IF_SELECT" ),"vCNV_BT_UART_TXD" ),"vCNV_BT_UART_RXD" ),"vCNV_BT_UART_CTS_B" ),"vCNV_BT_UART_RTS_B" ),"vCNV_MFUART1_TXD" ),"vCNV_MFUART1_RXD" ),"vCNV_MFUART1_CTS_B" ),"vCNV_MFUART1_RTS_B" ),"vUART0_TXD" ),"vUART0_RXD" ),"vUART0_CTS_B" ),"vUART0_RTS_B" ),"vISH_UART0_TXD" ),"vISH_UART0_RXD" ),"vISH_UART0_CTS_B" ),"vISH_UART0_RTS_B" ),"vCNV_BT_I2S_BCLK" ),"vCNV_BT_I2S_WS_SYNC" ),"vCNV_BT_I2S_SDO" ),"vCNV_BT_I2S_SDI" ),"vI2S2_SCLK" ),"vI2S2_SFRM" ),"vI2S2_TXD" ),"vI2S2_RXD" ),"vSD3_CD_B" ),/* GPP_C */ "SMBCLK" ),"SMBDATA" ),"SMBALERTB" ),"SML0CLK" ),"SML0DATA" ),"SML0ALERTB" ),"SML1CLK" ),"SML1DATA" ),"UART0_RXD" ),"UART0_TXD" ),"UART0_RTSB" ),"UART0_CTSB" ),"UART1_RXD" ),"UART1_TXD" ),"UART1_RTSB" ),"UART1_CTSB" ),"I2C0_SDA" ),"I2C0_SCL" ),"I2C1_SDA" ),"I2C1_SCL" ),"UART2_RXD" ),"UART2_TXD" ),"UART2_RTSB" ),"UART2_CTSB" ),/* HVCMOS */ "L_BKLTEN" ),"L_BKLTCTL" ),"L_VDDEN" ),"SYS_PWROK" ),"SYS_RESETB" ),"MLK_RSTB" ),/* GPP_E */ "SATAXPCIE_0" ),"SPI1_IO_2" ),"SPI1_IO_3" ),"CPU_GP_0" ),"SATA_DEVSLP_0" ),"SATA_DEVSLP_1" ),"GPPC_E_6" ),"CPU_GP_1" ),"SATA_LEDB" ),"USB2_OCB_0" ),"SPI1_CSB" ),"SPI1_CLK" ),"SPI1_MISO_IO_1" ),"SPI1_MOSI_IO_0" ),"DDSP_HPD_A" ),"ISH_GP_6" ),"ISH_GP_7" ),"DISP_MISC_4" ),"DDP1_CTRLCLK" ),"DDP1_CTRLDATA" ),"DDP2_CTRLCLK" ),"DDP2_CTRLDATA" ),"DDPA_CTRLCLK" ),"DDPA_CTRLDATA" ),/* JTAG */ "JTAG_TDO" ),"JTAGX" ),"PRDYB" ),"PREQB" ),"CPU_TRSTB" ),"JTAG_TDI" ),"JTAG_TMS" ),"JTAG_TCK" ),"ITP_PMODE" ),/* GPP_R */ "HDA_BCLK" ),"HDA_SYNC" ),"HDA_SDO" ),"HDA_SDI_0" ),"HDA_RSTB" ),"HDA_SDI_1" ),"I2S1_TXD" ),"I2S1_RXD" ),/* GPP_S */ "SNDW1_CLK" ),"SNDW1_DATA" ),"SNDW2_CLK" ),"SNDW2_DATA" ),"SNDW3_CLK" ),"SNDW3_DATA" ),"SNDW4_CLK" ),"SNDW4_DATA" ),/* SPI */ "SPI0_IO_2" ),"SPI0_IO_3" ),"SPI0_MOSI_IO_0" ),"SPI0_MISO_IO_1" ),"SPI0_TPM_CSB" ),"SPI0_FLASH_0_CSB" ),"SPI0_FLASH_1_CSB" ),"SPI0_CLK" ),"SPI0_CLK_LOOPBK" ),static const struct intel_padgroup icllp_community0_gpps[] = {/* GPP_G */ /* GPP_B */ /* GPP_A */ static const struct intel_padgroup icllp_community1_gpps[] = {/* GPP_H */ /* GPP_D */ /* GPP_F */ /* vGPIO */ static const struct intel_padgroup icllp_community4_gpps[] = {/* GPP_C */ /* HVCMOS */ /* GPP_E */ /* JTAG */ static const struct intel_padgroup icllp_community5_gpps[] = {/* GPP_R */ /* GPP_S */ /* SPI */ static const struct intel_community icllp_communities[] = {static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 };static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 };static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 };static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 };static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 };static const unsigned int icllp_i2c0_pins[] = { 169, 170 };static const unsigned int icllp_i2c1_pins[] = { 171, 172 };static const unsigned int icllp_i2c2_pins[] = { 63, 64 };static const unsigned int icllp_i2c3_pins[] = { 65, 66 };static const unsigned int icllp_i2c4_pins[] = { 67, 68 };static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 };static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 };static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 };static const struct intel_pingroup icllp_groups[] = {"spi0_grp" , icllp_spi0_pins, icllp_spi0_modes),"spi1_grp" , icllp_spi1_pins, icllp_spi1_modes),"spi2_grp" , icllp_spi2_pins, icllp_spi2_modes),"i2c0_grp" , icllp_i2c0_pins, 1),"i2c1_grp" , icllp_i2c1_pins, 1),"i2c2_grp" , icllp_i2c2_pins, 1),"i2c3_grp" , icllp_i2c3_pins, 1),"i2c4_grp" , icllp_i2c4_pins, 1),"uart0_grp" , icllp_uart0_pins, 1),"uart1_grp" , icllp_uart1_pins, 1),"uart2_grp" , icllp_uart2_pins, 1),static const char * const icllp_spi0_groups[] = { "spi0_grp" };static const char * const icllp_spi1_groups[] = { "spi1_grp" };static const char * const icllp_spi2_groups[] = { "spi2_grp" };static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };static const char * const icllp_uart0_groups[] = { "uart0_grp" };static const char * const icllp_uart1_groups[] = { "uart1_grp" };static const char * const icllp_uart2_groups[] = { "uart2_grp" };static const struct intel_function icllp_functions[] = {"spi0" , icllp_spi0_groups),"spi1" , icllp_spi1_groups),"spi2" , icllp_spi2_groups),"i2c0" , icllp_i2c0_groups),"i2c1" , icllp_i2c1_groups),"i2c2" , icllp_i2c2_groups),"i2c3" , icllp_i2c3_groups),"i2c4" , icllp_i2c4_groups),"uart0" , icllp_uart0_groups),"uart1" , icllp_uart1_groups),"uart2" , icllp_uart2_groups),static const struct intel_pinctrl_soc_data icllp_soc_data = {/* Ice Lake-N */ static const struct pinctrl_pin_desc icln_pins[] = {/* SPI */ "SPI0_IO_2" ),"SPI0_IO_3" ),"SPI0_MOSI_IO_0" ),"SPI0_MISO_IO_1" ),"SPI0_TPM_CSB" ),"SPI0_FLASH_0_CSB" ),"SPI0_FLASH_1_CSB" ),"SPI0_CLK" ),"SPI0_CLK_LOOPBK" ),/* GPP_B */ "CORE_VID_0" ),"CORE_VID_1" ),"VRALERTB" ),"CPU_GP_2" ),"CPU_GP_3" ),"SRCCLKREQB_0" ),"SRCCLKREQB_1" ),"SRCCLKREQB_2" ),"SRCCLKREQB_3" ),"SRCCLKREQB_4" ),"SRCCLKREQB_5" ),"EXT_PWR_GATEB" ),"SLP_S0B" ),"PLTRSTB" ),"SPKR_GSPI0_CS1B" ),"GSPI0_CS0B" ),"GSPI0_CLK" ),"GSPI0_MISO_TBT_LSX3_A" ),"GSPI0_MOSI_TBT_LSX3_B" ),"GSPI1_CS0B" ),"GSPI1_CLK_NFC_CLK" ),"GSPI1_MISO_NFC_CLKREQ" ),"GSPI1_MOSI" ),"GSPI1_CS1B" ),"GSPI0_CLK_LOOPBK" ),"GSPI1_CLK_LOOPBK" ),/* GPP_A */ "ESPI_IO_0" ),"ESPI_IO_1" ),"ESPI_IO_2" ),"ESPI_IO_3" ),"ESPI_CSB" ),"ESPI_CLK" ),"ESPI_RESETB" ),"SMBCLK" ),"SMBDATA" ),"SMBALERTB" ),"CPU_GP_0" ),"CPU_GP_1" ),"USB2_OCB_1" ),"USB2_OCB_2" ),"USB2_OCB_3" ),"DDSP_HPD_A_TIME_SYNC_0" ),"DDSP_HPD_B_TIME_SYNC_1" ),"DDSP_HPD_C" ),"USB2_OCB_0" ),"PCHHOTB" ),"ESPI_CLK_LOOPBK" ),/* GPP_S */ "SNDW1_CLK" ),"SNDW1_DATA" ),"SNDW2_CLK" ),"SNDW2_DATA" ),"SNDW3_CLK_DMIC_CLK_1" ),"SNDW3_DATA_DMIC_DATA_1" ),"SNDW4_CLK_DMIC_CLK_0" ),"SNDW4_DATA_DMIC_DATA_0" ),/* GPP_R */ "HDA_BCLK" ),"HDA_SYNC" ),"HDA_SDO" ),"HDA_SDI_0" ),"HDA_RSTB" ),"HDA_SDI_1_I2S1_RXD" ),"I2S1_SFRM" ),"I2S1_TXD" ),/* GPP_H */ "GPPC_H_0" ),"CNV_RF_RESET_B" ),"MODEM_CLKREQ" ),"SX_EXIT_HOLDOFFB" ),"I2C2_SDA" ),"I2C2_SCL" ),"I2C3_SDA" ),"I2C3_SCL" ),"I2C4_SDA" ),"I2C4_SCL" ),"CPU_VCCIO_PWR_GATEB" ),"I2S2_SCLK" ),"CNV_RF_RESET_B" ),"MODEM_CLKREQ" ),"I2S2_RXD" ),"I2S1_SCLK" ),"GPPC_H_16" ),"GPPC_H_17" ),"GPPC_H_18" ),"GPPC_H_19" ),"GPPC_H_20" ),"GPPC_H_21" ),"GPPC_H_22" ),"GPPC_H_23" ),/* GPP_D */ "SPI1_CSB_BK_0_SBK_0" ),"SPI1_CLK_BK_1_SBK_1" ),"SPI1_MISO_IO_1_BK_2_SBK_2" ),"SPI1_MOSI_IO_0_BK_3_SBK_3" ),"ISH_I2C0_SDA" ),"ISH_I2C0_SCL" ),"ISH_I2C1_SDA" ),"ISH_I2C1_SCL" ),"ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A" ),"ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B" ),"ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A" ),"ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B" ),"ISH_UART0_RXD_I2C4B_SDA" ),"ISH_UART0_TXD_I2C4B_SCL" ),"ISH_UART0_RTSB_GSPI2_CS1B" ),"ISH_UART0_CTSB_CNV_WCEN" ),"SPI1_IO_2" ),"SPI1_IO_3" ),"I2S_MCLK" ),"CNV_MFUART2_RXD" ),"CNV_MFUART2_TXD" ),"CNV_PA_BLANKING" ),"I2C5_SDA_ISH_I2C2_SDA" ),"I2C5_SCL_ISH_I2C2_SCL" ),"GSPI2_CLK_LOOPBK" ),"SPI1_CLK_LOOPBK" ),/* vGPIO */ "CNV_BTEN" ),"CNV_WCEN" ),"CNV_BT_HOST_WAKEB" ),"CNV_BT_IF_SELECT" ),"vCNV_BT_UART_TXD" ),"vCNV_BT_UART_RXD" ),"vCNV_BT_UART_CTS_B" ),"vCNV_BT_UART_RTS_B" ),"vCNV_MFUART1_TXD" ),"vCNV_MFUART1_RXD" ),"vCNV_MFUART1_CTS_B" ),"vCNV_MFUART1_RTS_B" ),"vUART0_TXD" ),"vUART0_RXD" ),"vUART0_CTS_B" ),"vUART0_RTS_B" ),"vISH_UART0_TXD" ),"vISH_UART0_RXD" ),"vISH_UART0_CTS_B" ),"vISH_UART0_RTS_B" ),"vCNV_BT_I2S_BCLK" ),"vCNV_BT_I2S_WS_SYNC" ),"vCNV_BT_I2S_SDO" ),"vCNV_BT_I2S_SDI" ),"vI2S2_SCLK" ),"vI2S2_SFRM" ),"vI2S2_TXD" ),"vI2S2_RXD" ),"vSD3_CD_B" ),/* GPP_C */ "GPPC_C_0" ),"GPPC_C_1" ),"GPPC_C_2" ),"GPPC_C_3" ),"GPPC_C_4" ),"GPPC_C_5" ),"SUSWARNB_SUSPWRDNACK" ),"SUSACKB" ),"UART0_RXD" ),"UART0_TXD" ),"UART0_RTSB" ),"UART0_CTSB" ),"UART1_RXD_ISH_UART1_RXD" ),"UART1_TXD_ISH_UART1_TXD" ),"UART1_RTSB_ISH_UART1_RTSB" ),"UART1_CTSB_ISH_UART1_CTSB" ),"I2C0_SDA" ),"I2C0_SCL" ),"I2C1_SDA" ),"I2C1_SCL" ),"UART2_RXD_CNV_MFUART0_RXD" ),"UART2_TXD_CNV_MFUART0_TXD" ),"UART2_RTSB_CNV_MFUART0_RTS_B" ),"UART2_CTSB_CNV_MFUART0_CTS_B" ),/* HVCMOS */ "L_BKLTEN" ),"L_BKLTCTL" ),"L_VDDEN" ),"SYS_PWROK" ),"SYS_RESETB" ),"MLK_RSTB" ),/* GPP_E */ "ISH_GP_0_IMGCLKOUT_0" ),"ISH_GP_1" ),"IMGCLKOUT_1" ),"ISH_GP_2_SATA_DEVSLP_0" ),"IMGCLKOUT_2" ),"SATA_LEDB_SPI1_CS1B" ),"IMGCLKOUT_3" ),"ISH_GP_3_SATA_DEVSLP_1" ),"FIVR_DIGPB_0" ),"SML0CLK" ),"SML0DATA" ),"BSSB_LS3_RX" ),"BSSB_LS3_TX" ),"BSSB_LS0_RX" ),"BSSB_LS0_TX" ),"BSSB_LS1_RX" ),"BSSB_LS1_TX" ),"BSSB_LS2_RX" ),"BSSB_LS2_TX" ),"FIVR_DIGPB_1" ),"CNV_BRI_DT" ),"CNV_BRI_RSP" ),"CNV_RGI_DT" ),"CNV_RGI_RSP" ),/* GPP_G */ "SD3_CMD" ),"SD3_D0" ),"SD3_D1" ),"SD3_D2" ),"SD3_D3" ),"SD3_CDB" ),"SD3_CLK" ),"SD3_WP" ),static const struct intel_padgroup icln_community0_gpps[] = {/* SPI */ /* GPP_B */ /* GPP_A */ /* GPP_S */ /* GPP_R */ static const struct intel_padgroup icln_community1_gpps[] = {/* GPP_H */ /* GPP_D */ /* vGPIO */ /* GPP_C */ static const struct intel_padgroup icln_community4_gpps[] = {/* HVCMOS */ /* GPP_E */ static const struct intel_padgroup icln_community5_gpps[] = {/* GPP_G */ static const struct intel_community icln_communities[] = {static const struct intel_pinctrl_soc_data icln_soc_data = {static const struct acpi_device_id icl_pinctrl_acpi_match[] = {"INT3455" , (kernel_ulong_t)&icllp_soc_data },"INT34C3" , (kernel_ulong_t)&icln_soc_data },static struct platform_driver icl_pinctrl_driver = {"icelake-pinctrl" ,"Andy Shevchenko <andriy.shevchenko@linux.intel.com>" );"Mika Westerberg <mika.westerberg@linux.intel.com>" );"Intel Ice Lake PCH pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 in Prozent C=96 H=95 G=95
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(vorverarbeitet am 2026-04-29)
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