// SPDX-License-Identifier: GPL-2.0 /* * The MT7623 driver based on Linux generic pinctrl binding. * * Copyright (C) 2015 - 2018 MediaTek Inc. * Author: Biao Huang <biao.huang@mediatek.com> * Ryder Lee <ryder.lee@mediatek.com> * Sean Wang <sean.wang@mediatek.com> #include "pinctrl-moore.h" #define PIN_BOND_REG0 0xb10#define PIN_BOND_REG1 0xf20#define PIN_BOND_REG2 0xef0#define BOND_PCIE_CLR (0x77 << 3)#define BOND_I2S_CLR 0x3#define BOND_MSDC0E_CLR 0x1#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \false )#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \#define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = {static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = {static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = {static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = {static const struct mtk_pin_field_calc mt7623_pin_tdsel_range[] = {static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = {/* MSDC0 */ /* MSDC1 */ /* MSDC1 */ /* MSDC0E */ static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = {/* MSDC0 */ /* MSDC1 */ /* MSDC2 */ /* MSDC0E */ static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = {/* MSDC0 */ /* MSDC1 */ /* MSDC2 */ /* MSDC0E */ static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {static const struct mtk_pin_desc mt7623_pins[] = {"PWRAP_SPI0_MI" , 148, DRV_GRP3),"PWRAP_SPI0_MO" , 149, DRV_GRP3),"PWRAP_INT" , 150, DRV_GRP3),"PWRAP_SPI0_CK" , 151, DRV_GRP3),"PWRAP_SPI0_CSN" , 152, DRV_GRP3),"PWRAP_SPI0_CK2" , 153, DRV_GRP3),"PWRAP_SPI0_CSN2" , 154, DRV_GRP3),"SPI1_CSN" , 155, DRV_GRP3),"SPI1_MI" , 156, DRV_GRP3),"SPI1_MO" , 157, DRV_GRP3),"RTC32K_CK" , 158, DRV_GRP3),"WATCHDOG" , 159, DRV_GRP3),"SRCLKENA" , 160, DRV_GRP3),"SRCLKENAI" , 161, DRV_GRP3),"URXD2" , 162, DRV_GRP1),"UTXD2" , 163, DRV_GRP1),"I2S5_DATA_IN" , 164, DRV_GRP1),"I2S5_BCK" , 165, DRV_GRP1),"PCM_CLK" , 166, DRV_GRP1),"PCM_SYNC" , 167, DRV_GRP1),"PCM_RX" , EINT_NA, DRV_GRP1),"PCM_TX" , EINT_NA, DRV_GRP1),"EINT0" , 0, DRV_GRP1),"EINT1" , 1, DRV_GRP1),"EINT2" , 2, DRV_GRP1),"EINT3" , 3, DRV_GRP1),"EINT4" , 4, DRV_GRP1),"EINT5" , 5, DRV_GRP1),"EINT6" , 6, DRV_GRP1),"EINT7" , 7, DRV_GRP1),"I2S5_LRCK" , 12, DRV_GRP1),"I2S5_MCLK" , 13, DRV_GRP1),"I2S5_DATA" , 14, DRV_GRP1),"I2S1_DATA" , 15, DRV_GRP1),"I2S1_DATA_IN" , 16, DRV_GRP1),"I2S1_BCK" , 17, DRV_GRP1),"I2S1_LRCK" , 18, DRV_GRP1),"I2S1_MCLK" , 19, DRV_GRP1),"I2S2_DATA" , 20, DRV_GRP1),"JTMS" , 21, DRV_GRP3),"JTCK" , 22, DRV_GRP3),"JTDI" , 23, DRV_GRP3),"JTDO" , 24, DRV_GRP3),"NCLE" , 25, DRV_GRP1),"NCEB1" , 26, DRV_GRP1),"NCEB0" , 27, DRV_GRP1),"IR" , 28, DRV_FIXED),"NREB" , 29, DRV_GRP1),"NRNB" , 30, DRV_GRP1),"I2S0_DATA" , 31, DRV_GRP1),"I2S2_BCK" , 32, DRV_GRP1),"I2S2_DATA_IN" , 33, DRV_GRP1),"I2S2_LRCK" , 34, DRV_GRP1),"SPI0_CSN" , 35, DRV_GRP1),"SPI0_CK" , 36, DRV_GRP1),"SPI0_MI" , 37, DRV_GRP1),"SPI0_MO" , 38, DRV_GRP1),"SDA1" , 39, DRV_FIXED),"SCL1" , 40, DRV_FIXED),"RAMBUF_I_CLK" , EINT_NA, DRV_FIXED),"WB_RSTB" , 41, DRV_GRP3),"F2W_DATA" , 42, DRV_GRP3),"F2W_CLK" , 43, DRV_GRP3),"WB_SCLK" , 44, DRV_GRP3),"WB_SDATA" , 45, DRV_GRP3),"WB_SEN" , 46, DRV_GRP3),"WB_CRTL0" , 47, DRV_GRP3),"WB_CRTL1" , 48, DRV_GRP3),"WB_CRTL2" , 49, DRV_GRP3),"WB_CRTL3" , 50, DRV_GRP3),"WB_CRTL4" , 51, DRV_GRP3),"WB_CRTL5" , 52, DRV_GRP3),"I2S0_DATA_IN" , 53, DRV_GRP1),"I2S0_LRCK" , 54, DRV_GRP1),"I2S0_BCK" , 55, DRV_GRP1),"SDA0" , 56, DRV_FIXED),"SCL0" , 57, DRV_FIXED),"SDA2" , 58, DRV_FIXED),"SCL2" , 59, DRV_FIXED),"URXD0" , 60, DRV_FIXED),"UTXD0" , 61, DRV_FIXED),"URXD1" , 62, DRV_FIXED),"UTXD1" , 63, DRV_FIXED),"LCM_RST" , 64, DRV_FIXED),"DSI_TE" , 65, DRV_FIXED),"MSDC2_CMD" , 66, DRV_GRP4),"MSDC2_CLK" , 67, DRV_GRP4),"MSDC2_DAT0" , 68, DRV_GRP4),"MSDC2_DAT1" , 69, DRV_GRP4),"MSDC2_DAT2" , 70, DRV_GRP4),"MSDC2_DAT3" , 71, DRV_GRP4),"TDN3" , EINT_NA, DRV_FIXED),"TDP3" , EINT_NA, DRV_FIXED),"TDN2" , EINT_NA, DRV_FIXED),"TDP2" , EINT_NA, DRV_FIXED),"TCN" , EINT_NA, DRV_FIXED),"TCP" , EINT_NA, DRV_FIXED),"TDN1" , EINT_NA, DRV_FIXED),"TDP1" , EINT_NA, DRV_FIXED),"TDN0" , EINT_NA, DRV_FIXED),"TDP0" , EINT_NA, DRV_FIXED),"SPI2_CSN" , 74, DRV_FIXED),"SPI2_MI" , 75, DRV_FIXED),"SPI2_MO" , 76, DRV_FIXED),"SPI2_CLK" , 77, DRV_FIXED),"MSDC1_CMD" , 78, DRV_GRP4),"MSDC1_CLK" , 79, DRV_GRP4),"MSDC1_DAT0" , 80, DRV_GRP4),"MSDC1_DAT1" , 81, DRV_GRP4),"MSDC1_DAT2" , 82, DRV_GRP4),"MSDC1_DAT3" , 83, DRV_GRP4),"MSDC0_DAT7" , 84, DRV_GRP4),"MSDC0_DAT6" , 85, DRV_GRP4),"MSDC0_DAT5" , 86, DRV_GRP4),"MSDC0_DAT4" , 87, DRV_GRP4),"MSDC0_RSTB" , 88, DRV_GRP4),"MSDC0_CMD" , 89, DRV_GRP4),"MSDC0_CLK" , 90, DRV_GRP4),"MSDC0_DAT3" , 91, DRV_GRP4),"MSDC0_DAT2" , 92, DRV_GRP4),"MSDC0_DAT1" , 93, DRV_GRP4),"MSDC0_DAT0" , 94, DRV_GRP4),"CEC" , 95, DRV_FIXED),"HTPLG" , 96, DRV_FIXED),"HDMISCK" , 97, DRV_FIXED),"HDMISD" , 98, DRV_FIXED),"I2S0_MCLK" , 99, DRV_GRP1),"RAMBUF_IDATA0" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA1" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA2" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA3" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA4" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA5" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA6" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA7" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA8" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA9" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA10" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA11" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA12" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA13" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA14" , EINT_NA, DRV_FIXED),"RAMBUF_IDATA15" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA0" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA1" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA2" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA3" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA4" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA5" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA6" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA7" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA8" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA9" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA10" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA11" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA12" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA13" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA14" , EINT_NA, DRV_FIXED),"RAMBUF_ODATA15" , EINT_NA, DRV_FIXED),"RAMBUF_BE0" , EINT_NA, DRV_FIXED),"RAMBUF_BE1" , EINT_NA, DRV_FIXED),"AP2PT_INT" , EINT_NA, DRV_FIXED),"AP2PT_INT_CLR" , EINT_NA, DRV_FIXED),"PT2AP_INT" , EINT_NA, DRV_FIXED),"PT2AP_INT_CLR" , EINT_NA, DRV_FIXED),"AP2UP_INT" , EINT_NA, DRV_FIXED),"AP2UP_INT_CLR" , EINT_NA, DRV_FIXED),"UP2AP_INT" , EINT_NA, DRV_FIXED),"UP2AP_INT_CLR" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR0" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR1" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR2" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR3" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR4" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR5" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR6" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR7" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR8" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR9" , EINT_NA, DRV_FIXED),"RAMBUF_ADDR10" , EINT_NA, DRV_FIXED),"RAMBUF_RW" , EINT_NA, DRV_FIXED),"RAMBUF_LAST" , EINT_NA, DRV_FIXED),"RAMBUF_HP" , EINT_NA, DRV_FIXED),"RAMBUF_REQ" , EINT_NA, DRV_FIXED),"RAMBUF_ALE" , EINT_NA, DRV_FIXED),"RAMBUF_DLE" , EINT_NA, DRV_FIXED),"RAMBUF_WDLE" , EINT_NA, DRV_FIXED),"RAMBUF_O_CLK" , EINT_NA, DRV_FIXED),"I2S2_MCLK" , 100, DRV_GRP1),"I2S3_DATA" , 101, DRV_GRP1),"I2S3_DATA_IN" , 102, DRV_GRP1),"I2S3_BCK" , 103, DRV_GRP1),"I2S3_LRCK" , 104, DRV_GRP1),"I2S3_MCLK" , 105, DRV_GRP1),"I2S4_DATA" , 106, DRV_GRP1),"I2S4_DATA_IN" , 107, DRV_GRP1),"I2S4_BCK" , 108, DRV_GRP1),"I2S4_LRCK" , 109, DRV_GRP1),"I2S4_MCLK" , 110, DRV_GRP1),"SPI1_CLK" , 111, DRV_GRP3),"SPDIF_OUT" , 112, DRV_GRP1),"SPDIF_IN0" , 113, DRV_GRP1),"SPDIF_IN1" , 114, DRV_GRP1),"PWM0" , 115, DRV_GRP1),"PWM1" , 116, DRV_GRP1),"PWM2" , 117, DRV_GRP1),"PWM3" , 118, DRV_GRP1),"PWM4" , 119, DRV_GRP1),"AUD_EXT_CK1" , 120, DRV_GRP1),"AUD_EXT_CK2" , 121, DRV_GRP1),"AUD_CLOCK" , EINT_NA, DRV_GRP3),"DVP_RESET" , EINT_NA, DRV_GRP3),"DVP_CLOCK" , EINT_NA, DRV_GRP3),"DVP_CS" , EINT_NA, DRV_GRP3),"DVP_CK" , EINT_NA, DRV_GRP3),"DVP_DI" , EINT_NA, DRV_GRP3),"DVP_DO" , EINT_NA, DRV_GRP3),"AP_CS" , EINT_NA, DRV_GRP3),"AP_CK" , EINT_NA, DRV_GRP3),"AP_DI" , EINT_NA, DRV_GRP3),"AP_DO" , EINT_NA, DRV_GRP3),"DVD_BCLK" , EINT_NA, DRV_GRP3),"T8032_CLK" , EINT_NA, DRV_GRP3),"AP_BCLK" , EINT_NA, DRV_GRP3),"HOST_CS" , EINT_NA, DRV_GRP3),"HOST_CK" , EINT_NA, DRV_GRP3),"HOST_DO0" , EINT_NA, DRV_GRP3),"HOST_DO1" , EINT_NA, DRV_GRP3),"SLV_CS" , EINT_NA, DRV_GRP3),"SLV_CK" , EINT_NA, DRV_GRP3),"SLV_DI0" , EINT_NA, DRV_GRP3),"SLV_DI1" , EINT_NA, DRV_GRP3),"AP2DSP_INT" , EINT_NA, DRV_GRP3),"AP2DSP_INT_CLR" , EINT_NA, DRV_GRP3),"DSP2AP_INT" , EINT_NA, DRV_GRP3),"DSP2AP_INT_CLR" , EINT_NA, DRV_GRP3),"EXT_SDIO3" , 122, DRV_GRP1),"EXT_SDIO2" , 123, DRV_GRP1),"EXT_SDIO1" , 124, DRV_GRP1),"EXT_SDIO0" , 125, DRV_GRP1),"EXT_XCS" , 126, DRV_GRP1),"EXT_SCK" , 127, DRV_GRP1),"URTS2" , 128, DRV_GRP1),"UCTS2" , 129, DRV_GRP1),"HDMI_SDA_RX" , 130, DRV_FIXED),"HDMI_SCL_RX" , 131, DRV_FIXED),"MHL_SENCE" , 132, DRV_FIXED),"HDMI_HPD_CBUS_RX" , 69, DRV_FIXED),"HDMI_TESTOUTP_RX" , 133, DRV_GRP1),"MSDC0E_RSTB" , 134, DRV_GRP4),"MSDC0E_DAT7" , 135, DRV_GRP4),"MSDC0E_DAT6" , 136, DRV_GRP4),"MSDC0E_DAT5" , 137, DRV_GRP4),"MSDC0E_DAT4" , 138, DRV_GRP4),"MSDC0E_DAT3" , 139, DRV_GRP4),"MSDC0E_DAT2" , 140, DRV_GRP4),"MSDC0E_DAT1" , 141, DRV_GRP4),"MSDC0E_DAT0" , 142, DRV_GRP4),"MSDC0E_CMD" , 143, DRV_GRP4),"MSDC0E_CLK" , 144, DRV_GRP4),"MSDC0E_DSL" , 145, DRV_GRP4),"MSDC1_INS" , 146, DRV_GRP4),"G2_TXEN" , 8, DRV_GRP1),"G2_TXD3" , 9, DRV_GRP1),"G2_TXD2" , 10, DRV_GRP1),"G2_TXD1" , 11, DRV_GRP1),"G2_TXD0" , EINT_NA, DRV_GRP1),"G2_TXC" , EINT_NA, DRV_GRP1),"G2_RXC" , EINT_NA, DRV_GRP1),"G2_RXD0" , EINT_NA, DRV_GRP1),"G2_RXD1" , EINT_NA, DRV_GRP1),"G2_RXD2" , EINT_NA, DRV_GRP1),"G2_RXD3" , EINT_NA, DRV_GRP1),"ESW_INT" , 168, DRV_GRP1),"G2_RXDV" , EINT_NA, DRV_GRP1),"MDC" , EINT_NA, DRV_GRP1),"MDIO" , EINT_NA, DRV_GRP1),"ESW_RST" , EINT_NA, DRV_GRP1),"JTAG_RESET" , 147, DRV_GRP3),"USB3_RES_BOND" , EINT_NA, DRV_GRP1),/* List all groups consisting of these pins dedicated to the enablement of * certain hardware block and the corresponding mode for all of the pins. * The hardware probably has multiple combinations of these pinouts. /* AUDIO EXT CLK */ static int mt7623_aud_ext_clk0_pins[] = { 208, };static int mt7623_aud_ext_clk0_funcs[] = { 1, };static int mt7623_aud_ext_clk1_pins[] = { 209, };static int mt7623_aud_ext_clk1_funcs[] = { 1, };/* DISP PWM */ static int mt7623_disp_pwm_0_pins[] = { 72, };static int mt7623_disp_pwm_0_funcs[] = { 5, };static int mt7623_disp_pwm_1_pins[] = { 203, };static int mt7623_disp_pwm_1_funcs[] = { 2, };static int mt7623_disp_pwm_2_pins[] = { 208, };static int mt7623_disp_pwm_2_funcs[] = { 5, };/* ESW */ static int mt7623_esw_int_pins[] = { 273, };static int mt7623_esw_int_funcs[] = { 1, };static int mt7623_esw_rst_pins[] = { 277, };static int mt7623_esw_rst_funcs[] = { 1, };/* EPHY */ static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };/* EXT_SDIO */ static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };/* HDMI RX */ static int mt7623_hdmi_rx_pins[] = { 247, 248, };static int mt7623_hdmi_rx_funcs[] = { 1, 1 };static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };/* HDMI TX */ static int mt7623_hdmi_cec_pins[] = { 122, };static int mt7623_hdmi_cec_funcs[] = { 1, };static int mt7623_hdmi_htplg_pins[] = { 123, };static int mt7623_hdmi_htplg_funcs[] = { 1, };static int mt7623_hdmi_i2c_pins[] = { 124, 125, };static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };/* I2C */ static int mt7623_i2c0_pins[] = { 75, 76, };static int mt7623_i2c0_funcs[] = { 1, 1, };static int mt7623_i2c1_0_pins[] = { 57, 58, };static int mt7623_i2c1_0_funcs[] = { 1, 1, };static int mt7623_i2c1_1_pins[] = { 242, 243, };static int mt7623_i2c1_1_funcs[] = { 4, 4, };static int mt7623_i2c1_2_pins[] = { 85, 86, };static int mt7623_i2c1_2_funcs[] = { 3, 3, };static int mt7623_i2c1_3_pins[] = { 105, 106, };static int mt7623_i2c1_3_funcs[] = { 3, 3, };static int mt7623_i2c1_4_pins[] = { 124, 125, };static int mt7623_i2c1_4_funcs[] = { 4, 4, };static int mt7623_i2c2_0_pins[] = { 77, 78, };static int mt7623_i2c2_0_funcs[] = { 1, 1, };static int mt7623_i2c2_1_pins[] = { 89, 90, };static int mt7623_i2c2_1_funcs[] = { 3, 3, };static int mt7623_i2c2_2_pins[] = { 109, 110, };static int mt7623_i2c2_2_funcs[] = { 3, 3, };static int mt7623_i2c2_3_pins[] = { 122, 123, };static int mt7623_i2c2_3_funcs[] = { 4, 4, };/* I2S */ static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };static int mt7623_i2s2_data_in_pins[] = { 51, };static int mt7623_i2s2_data_in_funcs[] = { 1, };static int mt7623_i2s2_data_0_pins[] = { 203, };static int mt7623_i2s2_data_0_funcs[] = { 9, };static int mt7623_i2s2_data_1_pins[] = { 38, };static int mt7623_i2s2_data_1_funcs[] = { 4, };static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };static int mt7623_i2s3_data_in_pins[] = { 190, };static int mt7623_i2s3_data_in_funcs[] = { 1, };static int mt7623_i2s3_data_0_pins[] = { 204, };static int mt7623_i2s3_data_0_funcs[] = { 9, };static int mt7623_i2s3_data_1_pins[] = { 2, };static int mt7623_i2s3_data_1_funcs[] = { 0, };static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };/* IR */ static int mt7623_ir_pins[] = { 46, };static int mt7623_ir_funcs[] = { 1, };/* LCD */ static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };static int mt7623_dsi_te_pins[] = { 84, };static int mt7623_dsi_te_funcs[] = { 1, };static int mt7623_lcm_rst_pins[] = { 83, };static int mt7623_lcm_rst_funcs[] = { 1, };/* MDC/MDIO */ static int mt7623_mdc_mdio_pins[] = { 275, 276, };static int mt7623_mdc_mdio_funcs[] = { 1, 1, };/* MSDC */ static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };static int mt7623_msdc1_ins_pins[] = { 261, };static int mt7623_msdc1_ins_funcs[] = { 1, };static int mt7623_msdc1_wp_0_pins[] = { 29, };static int mt7623_msdc1_wp_0_funcs[] = { 1, };static int mt7623_msdc1_wp_1_pins[] = { 55, };static int mt7623_msdc1_wp_1_funcs[] = { 3, };static int mt7623_msdc1_wp_2_pins[] = { 209, };static int mt7623_msdc1_wp_2_funcs[] = { 2, };static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };/* NAND */ static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,static int mt7623_nandc_ceb0_pins[] = { 45, };static int mt7623_nandc_ceb0_funcs[] = { 1, };static int mt7623_nandc_ceb1_pins[] = { 44, };static int mt7623_nandc_ceb1_funcs[] = { 1, };/* RTC */ static int mt7623_rtc_pins[] = { 10, };static int mt7623_rtc_funcs[] = { 1, };/* OTG */ static int mt7623_otg_iddig0_0_pins[] = { 29, };static int mt7623_otg_iddig0_0_funcs[] = { 1, };static int mt7623_otg_iddig0_1_pins[] = { 44, };static int mt7623_otg_iddig0_1_funcs[] = { 2, };static int mt7623_otg_iddig0_2_pins[] = { 236, };static int mt7623_otg_iddig0_2_funcs[] = { 2, };static int mt7623_otg_iddig1_0_pins[] = { 27, };static int mt7623_otg_iddig1_0_funcs[] = { 2, };static int mt7623_otg_iddig1_1_pins[] = { 47, };static int mt7623_otg_iddig1_1_funcs[] = { 2, };static int mt7623_otg_iddig1_2_pins[] = { 238, };static int mt7623_otg_iddig1_2_funcs[] = { 2, };static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };/* PCIE */ static int mt7623_pcie0_0_perst_pins[] = { 208, };static int mt7623_pcie0_0_perst_funcs[] = { 3, };static int mt7623_pcie0_1_perst_pins[] = { 22, };static int mt7623_pcie0_1_perst_funcs[] = { 2, };static int mt7623_pcie1_0_perst_pins[] = { 209, };static int mt7623_pcie1_0_perst_funcs[] = { 3, };static int mt7623_pcie1_1_perst_pins[] = { 23, };static int mt7623_pcie1_1_perst_funcs[] = { 2, };static int mt7623_pcie2_0_perst_pins[] = { 24, };static int mt7623_pcie2_0_perst_funcs[] = { 2, };static int mt7623_pcie2_1_perst_pins[] = { 29, };static int mt7623_pcie2_1_perst_funcs[] = { 6, };static int mt7623_pcie0_0_wake_pins[] = { 28, };static int mt7623_pcie0_0_wake_funcs[] = { 6, };static int mt7623_pcie0_1_wake_pins[] = { 251, };static int mt7623_pcie0_1_wake_funcs[] = { 6, };static int mt7623_pcie1_0_wake_pins[] = { 27, };static int mt7623_pcie1_0_wake_funcs[] = { 6, };static int mt7623_pcie1_1_wake_pins[] = { 253, };static int mt7623_pcie1_1_wake_funcs[] = { 6, };static int mt7623_pcie2_0_wake_pins[] = { 26, };static int mt7623_pcie2_0_wake_funcs[] = { 6, };static int mt7623_pcie2_1_wake_pins[] = { 255, };static int mt7623_pcie2_1_wake_funcs[] = { 6, };static int mt7623_pcie0_clkreq_pins[] = { 250, };static int mt7623_pcie0_clkreq_funcs[] = { 6, };static int mt7623_pcie1_clkreq_pins[] = { 252, };static int mt7623_pcie1_clkreq_funcs[] = { 6, };static int mt7623_pcie2_clkreq_pins[] = { 254, };static int mt7623_pcie2_clkreq_funcs[] = { 6, };/* the pcie_*_rev are only used for MT7623 */ static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };/* PCM */ static int mt7623_pcm_clk_0_pins[] = { 18, };static int mt7623_pcm_clk_0_funcs[] = { 1, };static int mt7623_pcm_clk_1_pins[] = { 17, };static int mt7623_pcm_clk_1_funcs[] = { 3, };static int mt7623_pcm_clk_2_pins[] = { 35, };static int mt7623_pcm_clk_2_funcs[] = { 3, };static int mt7623_pcm_clk_3_pins[] = { 50, };static int mt7623_pcm_clk_3_funcs[] = { 3, };static int mt7623_pcm_clk_4_pins[] = { 74, };static int mt7623_pcm_clk_4_funcs[] = { 3, };static int mt7623_pcm_clk_5_pins[] = { 191, };static int mt7623_pcm_clk_5_funcs[] = { 3, };static int mt7623_pcm_clk_6_pins[] = { 196, };static int mt7623_pcm_clk_6_funcs[] = { 3, };static int mt7623_pcm_sync_0_pins[] = { 19, };static int mt7623_pcm_sync_0_funcs[] = { 1, };static int mt7623_pcm_sync_1_pins[] = { 30, };static int mt7623_pcm_sync_1_funcs[] = { 3, };static int mt7623_pcm_sync_2_pins[] = { 36, };static int mt7623_pcm_sync_2_funcs[] = { 3, };static int mt7623_pcm_sync_3_pins[] = { 52, };static int mt7623_pcm_sync_3_funcs[] = { 31, };static int mt7623_pcm_sync_4_pins[] = { 73, };static int mt7623_pcm_sync_4_funcs[] = { 3, };static int mt7623_pcm_sync_5_pins[] = { 192, };static int mt7623_pcm_sync_5_funcs[] = { 3, };static int mt7623_pcm_sync_6_pins[] = { 197, };static int mt7623_pcm_sync_6_funcs[] = { 3, };static int mt7623_pcm_rx_0_pins[] = { 20, };static int mt7623_pcm_rx_0_funcs[] = { 1, };static int mt7623_pcm_rx_1_pins[] = { 16, };static int mt7623_pcm_rx_1_funcs[] = { 3, };static int mt7623_pcm_rx_2_pins[] = { 34, };static int mt7623_pcm_rx_2_funcs[] = { 3, };static int mt7623_pcm_rx_3_pins[] = { 51, };static int mt7623_pcm_rx_3_funcs[] = { 3, };static int mt7623_pcm_rx_4_pins[] = { 72, };static int mt7623_pcm_rx_4_funcs[] = { 3, };static int mt7623_pcm_rx_5_pins[] = { 190, };static int mt7623_pcm_rx_5_funcs[] = { 3, };static int mt7623_pcm_rx_6_pins[] = { 195, };static int mt7623_pcm_rx_6_funcs[] = { 3, };static int mt7623_pcm_tx_0_pins[] = { 21, };static int mt7623_pcm_tx_0_funcs[] = { 1, };static int mt7623_pcm_tx_1_pins[] = { 32, };static int mt7623_pcm_tx_1_funcs[] = { 3, };static int mt7623_pcm_tx_2_pins[] = { 33, };static int mt7623_pcm_tx_2_funcs[] = { 3, };static int mt7623_pcm_tx_3_pins[] = { 38, };static int mt7623_pcm_tx_3_funcs[] = { 3, };static int mt7623_pcm_tx_4_pins[] = { 49, };static int mt7623_pcm_tx_4_funcs[] = { 3, };static int mt7623_pcm_tx_5_pins[] = { 189, };static int mt7623_pcm_tx_5_funcs[] = { 3, };static int mt7623_pcm_tx_6_pins[] = { 194, };static int mt7623_pcm_tx_6_funcs[] = { 3, };/* PWM */ static int mt7623_pwm_ch1_0_pins[] = { 203, };static int mt7623_pwm_ch1_0_funcs[] = { 1, };static int mt7623_pwm_ch1_1_pins[] = { 208, };static int mt7623_pwm_ch1_1_funcs[] = { 2, };static int mt7623_pwm_ch1_2_pins[] = { 72, };static int mt7623_pwm_ch1_2_funcs[] = { 4, };static int mt7623_pwm_ch1_3_pins[] = { 88, };static int mt7623_pwm_ch1_3_funcs[] = { 3, };static int mt7623_pwm_ch1_4_pins[] = { 108, };static int mt7623_pwm_ch1_4_funcs[] = { 3, };static int mt7623_pwm_ch2_0_pins[] = { 204, };static int mt7623_pwm_ch2_0_funcs[] = { 1, };static int mt7623_pwm_ch2_1_pins[] = { 53, };static int mt7623_pwm_ch2_1_funcs[] = { 5, };static int mt7623_pwm_ch2_2_pins[] = { 88, };static int mt7623_pwm_ch2_2_funcs[] = { 6, };static int mt7623_pwm_ch2_3_pins[] = { 108, };static int mt7623_pwm_ch2_3_funcs[] = { 6, };static int mt7623_pwm_ch2_4_pins[] = { 209, };static int mt7623_pwm_ch2_4_funcs[] = { 5, };static int mt7623_pwm_ch3_0_pins[] = { 205, };static int mt7623_pwm_ch3_0_funcs[] = { 1, };static int mt7623_pwm_ch3_1_pins[] = { 55, };static int mt7623_pwm_ch3_1_funcs[] = { 5, };static int mt7623_pwm_ch3_2_pins[] = { 89, };static int mt7623_pwm_ch3_2_funcs[] = { 6, };static int mt7623_pwm_ch3_3_pins[] = { 109, };static int mt7623_pwm_ch3_3_funcs[] = { 6, };static int mt7623_pwm_ch4_0_pins[] = { 206, };static int mt7623_pwm_ch4_0_funcs[] = { 1, };static int mt7623_pwm_ch4_1_pins[] = { 90, };static int mt7623_pwm_ch4_1_funcs[] = { 6, };static int mt7623_pwm_ch4_2_pins[] = { 110, };static int mt7623_pwm_ch4_2_funcs[] = { 6, };static int mt7623_pwm_ch4_3_pins[] = { 124, };static int mt7623_pwm_ch4_3_funcs[] = { 5, };static int mt7623_pwm_ch5_0_pins[] = { 207, };static int mt7623_pwm_ch5_0_funcs[] = { 1, };static int mt7623_pwm_ch5_1_pins[] = { 125, };static int mt7623_pwm_ch5_1_funcs[] = { 5, };/* PWRAP */ static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };/* SPDIF */ static int mt7623_spdif_in0_0_pins[] = { 56, };static int mt7623_spdif_in0_0_funcs[] = { 3, };static int mt7623_spdif_in0_1_pins[] = { 201, };static int mt7623_spdif_in0_1_funcs[] = { 1, };static int mt7623_spdif_in1_0_pins[] = { 54, };static int mt7623_spdif_in1_0_funcs[] = { 3, };static int mt7623_spdif_in1_1_pins[] = { 202, };static int mt7623_spdif_in1_1_funcs[] = { 1, };static int mt7623_spdif_out_pins[] = { 202, };static int mt7623_spdif_out_funcs[] = { 1, };/* SPI */ static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };/* UART */ static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };/* Watchdog */ static int mt7623_watchdog_0_pins[] = { 11, };static int mt7623_watchdog_0_funcs[] = { 1, };static int mt7623_watchdog_1_pins[] = { 121, };static int mt7623_watchdog_1_funcs[] = { 5, };static const struct group_desc mt7623_groups[] = {"aud_ext_clk0" , mt7623_aud_ext_clk0),"aud_ext_clk1" , mt7623_aud_ext_clk1),"dsi_te" , mt7623_dsi_te),"disp_pwm_0" , mt7623_disp_pwm_0),"disp_pwm_1" , mt7623_disp_pwm_1),"disp_pwm_2" , mt7623_disp_pwm_2),"ephy" , mt7623_ephy),"esw_int" , mt7623_esw_int),"esw_rst" , mt7623_esw_rst),"ext_sdio" , mt7623_ext_sdio),"hdmi_cec" , mt7623_hdmi_cec),"hdmi_htplg" , mt7623_hdmi_htplg),"hdmi_i2c" , mt7623_hdmi_i2c),"hdmi_rx" , mt7623_hdmi_rx),"hdmi_rx_i2c" , mt7623_hdmi_rx_i2c),"i2c0" , mt7623_i2c0),"i2c1_0" , mt7623_i2c1_0),"i2c1_1" , mt7623_i2c1_1),"i2c1_2" , mt7623_i2c1_2),"i2c1_3" , mt7623_i2c1_3),"i2c1_4" , mt7623_i2c1_4),"i2c2_0" , mt7623_i2c2_0),"i2c2_1" , mt7623_i2c2_1),"i2c2_2" , mt7623_i2c2_2),"i2c2_3" , mt7623_i2c2_3),"i2s0" , mt7623_i2s0),"i2s1" , mt7623_i2s1),"i2s4" , mt7623_i2s4),"i2s5" , mt7623_i2s5),"i2s2_bclk_lrclk_mclk" , mt7623_i2s2_bclk_lrclk_mclk),"i2s3_bclk_lrclk_mclk" , mt7623_i2s3_bclk_lrclk_mclk),"i2s2_data_in" , mt7623_i2s2_data_in),"i2s3_data_in" , mt7623_i2s3_data_in),"i2s2_data_0" , mt7623_i2s2_data_0),"i2s2_data_1" , mt7623_i2s2_data_1),"i2s3_data_0" , mt7623_i2s3_data_0),"i2s3_data_1" , mt7623_i2s3_data_1),"ir" , mt7623_ir),"lcm_rst" , mt7623_lcm_rst),"mdc_mdio" , mt7623_mdc_mdio),"mipi_tx" , mt7623_mipi_tx),"msdc0" , mt7623_msdc0),"msdc1" , mt7623_msdc1),"msdc1_ins" , mt7623_msdc1_ins),"msdc1_wp_0" , mt7623_msdc1_wp_0),"msdc1_wp_1" , mt7623_msdc1_wp_1),"msdc1_wp_2" , mt7623_msdc1_wp_2),"msdc2" , mt7623_msdc2),"msdc3" , mt7623_msdc3),"nandc" , mt7623_nandc),"nandc_ceb0" , mt7623_nandc_ceb0),"nandc_ceb1" , mt7623_nandc_ceb1),"otg_iddig0_0" , mt7623_otg_iddig0_0),"otg_iddig0_1" , mt7623_otg_iddig0_1),"otg_iddig0_2" , mt7623_otg_iddig0_2),"otg_iddig1_0" , mt7623_otg_iddig1_0),"otg_iddig1_1" , mt7623_otg_iddig1_1),"otg_iddig1_2" , mt7623_otg_iddig1_2),"otg_drv_vbus0_0" , mt7623_otg_drv_vbus0_0),"otg_drv_vbus0_1" , mt7623_otg_drv_vbus0_1),"otg_drv_vbus0_2" , mt7623_otg_drv_vbus0_2),"otg_drv_vbus1_0" , mt7623_otg_drv_vbus1_0),"otg_drv_vbus1_1" , mt7623_otg_drv_vbus1_1),"otg_drv_vbus1_2" , mt7623_otg_drv_vbus1_2),"pcie0_0_perst" , mt7623_pcie0_0_perst),"pcie0_1_perst" , mt7623_pcie0_1_perst),"pcie1_0_perst" , mt7623_pcie1_0_perst),"pcie1_1_perst" , mt7623_pcie1_1_perst),"pcie1_1_perst" , mt7623_pcie1_1_perst),"pcie0_0_rev_perst" , mt7623_pcie0_0_rev_perst),"pcie0_1_rev_perst" , mt7623_pcie0_1_rev_perst),"pcie1_0_rev_perst" , mt7623_pcie1_0_rev_perst),"pcie1_1_rev_perst" , mt7623_pcie1_1_rev_perst),"pcie2_0_rev_perst" , mt7623_pcie2_0_rev_perst),"pcie2_1_rev_perst" , mt7623_pcie2_1_rev_perst),"pcie2_0_perst" , mt7623_pcie2_0_perst),"pcie2_1_perst" , mt7623_pcie2_1_perst),"pcie0_0_wake" , mt7623_pcie0_0_wake),"pcie0_1_wake" , mt7623_pcie0_1_wake),"pcie1_0_wake" , mt7623_pcie1_0_wake),"pcie1_1_wake" , mt7623_pcie1_1_wake),"pcie2_0_wake" , mt7623_pcie2_0_wake),"pcie2_1_wake" , mt7623_pcie2_1_wake),"pcie0_clkreq" , mt7623_pcie0_clkreq),"pcie1_clkreq" , mt7623_pcie1_clkreq),"pcie2_clkreq" , mt7623_pcie2_clkreq),"pcm_clk_0" , mt7623_pcm_clk_0),"pcm_clk_1" , mt7623_pcm_clk_1),"pcm_clk_2" , mt7623_pcm_clk_2),"pcm_clk_3" , mt7623_pcm_clk_3),"pcm_clk_4" , mt7623_pcm_clk_4),"pcm_clk_5" , mt7623_pcm_clk_5),"pcm_clk_6" , mt7623_pcm_clk_6),"pcm_sync_0" , mt7623_pcm_sync_0),"pcm_sync_1" , mt7623_pcm_sync_1),"pcm_sync_2" , mt7623_pcm_sync_2),"pcm_sync_3" , mt7623_pcm_sync_3),"pcm_sync_4" , mt7623_pcm_sync_4),"pcm_sync_5" , mt7623_pcm_sync_5),"pcm_sync_6" , mt7623_pcm_sync_6),"pcm_rx_0" , mt7623_pcm_rx_0),"pcm_rx_1" , mt7623_pcm_rx_1),"pcm_rx_2" , mt7623_pcm_rx_2),"pcm_rx_3" , mt7623_pcm_rx_3),"pcm_rx_4" , mt7623_pcm_rx_4),"pcm_rx_5" , mt7623_pcm_rx_5),"pcm_rx_6" , mt7623_pcm_rx_6),"pcm_tx_0" , mt7623_pcm_tx_0),"pcm_tx_1" , mt7623_pcm_tx_1),"pcm_tx_2" , mt7623_pcm_tx_2),"pcm_tx_3" , mt7623_pcm_tx_3),"pcm_tx_4" , mt7623_pcm_tx_4),"pcm_tx_5" , mt7623_pcm_tx_5),"pcm_tx_6" , mt7623_pcm_tx_6),"pwm_ch1_0" , mt7623_pwm_ch1_0),"pwm_ch1_1" , mt7623_pwm_ch1_1),"pwm_ch1_2" , mt7623_pwm_ch1_2),"pwm_ch1_3" , mt7623_pwm_ch1_3),"pwm_ch1_4" , mt7623_pwm_ch1_4),"pwm_ch2_0" , mt7623_pwm_ch2_0),"pwm_ch2_1" , mt7623_pwm_ch2_1),"pwm_ch2_2" , mt7623_pwm_ch2_2),"pwm_ch2_3" , mt7623_pwm_ch2_3),"pwm_ch2_4" , mt7623_pwm_ch2_4),"pwm_ch3_0" , mt7623_pwm_ch3_0),"pwm_ch3_1" , mt7623_pwm_ch3_1),"pwm_ch3_2" , mt7623_pwm_ch3_2),"pwm_ch3_3" , mt7623_pwm_ch3_3),"pwm_ch4_0" , mt7623_pwm_ch4_0),"pwm_ch4_1" , mt7623_pwm_ch4_1),"pwm_ch4_2" , mt7623_pwm_ch4_2),"pwm_ch4_3" , mt7623_pwm_ch4_3),"pwm_ch5_0" , mt7623_pwm_ch5_0),"pwm_ch5_1" , mt7623_pwm_ch5_1),"pwrap" , mt7623_pwrap),"rtc" , mt7623_rtc),"spdif_in0_0" , mt7623_spdif_in0_0),"spdif_in0_1" , mt7623_spdif_in0_1),"spdif_in1_0" , mt7623_spdif_in1_0),"spdif_in1_1" , mt7623_spdif_in1_1),"spdif_out" , mt7623_spdif_out),"spi0" , mt7623_spi0),"spi1" , mt7623_spi1),"spi2" , mt7623_spi2),"uart0_0_txd_rxd" , mt7623_uart0_0_txd_rxd),"uart0_1_txd_rxd" , mt7623_uart0_1_txd_rxd),"uart0_2_txd_rxd" , mt7623_uart0_2_txd_rxd),"uart0_3_txd_rxd" , mt7623_uart0_3_txd_rxd),"uart1_0_txd_rxd" , mt7623_uart1_0_txd_rxd),"uart1_1_txd_rxd" , mt7623_uart1_1_txd_rxd),"uart1_2_txd_rxd" , mt7623_uart1_2_txd_rxd),"uart2_0_txd_rxd" , mt7623_uart2_0_txd_rxd),"uart2_1_txd_rxd" , mt7623_uart2_1_txd_rxd),"uart3_txd_rxd" , mt7623_uart3_txd_rxd),"uart0_rts_cts" , mt7623_uart0_rts_cts),"uart1_rts_cts" , mt7623_uart1_rts_cts),"uart2_rts_cts" , mt7623_uart2_rts_cts),"uart3_rts_cts" , mt7623_uart3_rts_cts),"watchdog_0" , mt7623_watchdog_0),"watchdog_1" , mt7623_watchdog_1),/* Joint those groups owning the same capability in user point of view which * allows that people tend to use through the device tree. static const char *mt7623_aud_clk_groups[] = { "aud_ext_clk0" ,"aud_ext_clk1" , };static const char *mt7623_disp_pwm_groups[] = { "disp_pwm_0" , "disp_pwm_1" ,"disp_pwm_2" , };static const char *mt7623_ethernet_groups[] = { "esw_int" , "esw_rst" ,"ephy" , "mdc_mdio" , };static const char *mt7623_ext_sdio_groups[] = { "ext_sdio" , };static const char *mt7623_hdmi_groups[] = { "hdmi_cec" , "hdmi_htplg" ,"hdmi_i2c" , "hdmi_rx" ,"hdmi_rx_i2c" , };static const char *mt7623_i2c_groups[] = { "i2c0" , "i2c1_0" , "i2c1_1" ,"i2c1_2" , "i2c1_3" , "i2c1_4" ,"i2c2_0" , "i2c2_1" , "i2c2_2" ,"i2c2_3" , };static const char *mt7623_i2s_groups[] = { "i2s0" , "i2s1" ,"i2s2_bclk_lrclk_mclk" ,"i2s3_bclk_lrclk_mclk" ,"i2s4" , "i2s5" ,"i2s2_data_in" , "i2s3_data_in" ,"i2s2_data_0" , "i2s2_data_1" ,"i2s3_data_0" , "i2s3_data_1" , };static const char *mt7623_ir_groups[] = { "ir" , };static const char *mt7623_lcd_groups[] = { "dsi_te" , "lcm_rst" , "mipi_tx" , };static const char *mt7623_msdc_groups[] = { "msdc0" , "msdc1" , "msdc1_ins" ,"msdc1_wp_0" , "msdc1_wp_1" ,"msdc1_wp_2" , "msdc2" ,"msdc3" , };static const char *mt7623_nandc_groups[] = { "nandc" , "nandc_ceb0" ,"nandc_ceb1" , };static const char *mt7623_otg_groups[] = { "otg_iddig0_0" , "otg_iddig0_1" ,"otg_iddig0_2" , "otg_iddig1_0" ,"otg_iddig1_1" , "otg_iddig1_2" ,"otg_drv_vbus0_0" ,"otg_drv_vbus0_1" ,"otg_drv_vbus0_2" ,"otg_drv_vbus1_0" ,"otg_drv_vbus1_1" ,"otg_drv_vbus1_2" , };static const char *mt7623_pcie_groups[] = { "pcie0_0_perst" , "pcie0_1_perst" ,"pcie1_0_perst" , "pcie1_1_perst" ,"pcie2_0_perst" , "pcie2_1_perst" ,"pcie0_0_rev_perst" ,"pcie0_1_rev_perst" ,"pcie1_0_rev_perst" ,"pcie1_1_rev_perst" ,"pcie2_0_rev_perst" ,"pcie2_1_rev_perst" ,"pcie0_0_wake" , "pcie0_1_wake" ,"pcie2_0_wake" , "pcie2_1_wake" ,"pcie0_clkreq" , "pcie1_clkreq" ,"pcie2_clkreq" , };static const char *mt7623_pcm_groups[] = { "pcm_clk_0" , "pcm_clk_1" ,"pcm_clk_2" , "pcm_clk_3" ,"pcm_clk_4" , "pcm_clk_5" ,"pcm_clk_6" , "pcm_sync_0" ,"pcm_sync_1" , "pcm_sync_2" ,"pcm_sync_3" , "pcm_sync_4" ,"pcm_sync_5" , "pcm_sync_6" ,"pcm_rx_0" , "pcm_rx_1" ,"pcm_rx_2" , "pcm_rx_3" ,"pcm_rx_4" , "pcm_rx_5" ,"pcm_rx_6" , "pcm_tx_0" ,"pcm_tx_1" , "pcm_tx_2" ,"pcm_tx_3" , "pcm_tx_4" ,"pcm_tx_5" , "pcm_tx_6" , };static const char *mt7623_pwm_groups[] = { "pwm_ch1_0" , "pwm_ch1_1" ,"pwm_ch1_2" , "pwm_ch2_0" ,"pwm_ch2_1" , "pwm_ch2_2" ,"pwm_ch3_0" , "pwm_ch3_1" ,"pwm_ch3_2" , "pwm_ch4_0" ,"pwm_ch4_1" , "pwm_ch4_2" ,"pwm_ch4_3" , "pwm_ch5_0" ,"pwm_ch5_1" , "pwm_ch5_2" ,"pwm_ch6_0" , "pwm_ch6_1" ,"pwm_ch6_2" , "pwm_ch6_3" ,"pwm_ch7_0" , "pwm_ch7_1" ,"pwm_ch7_2" , };static const char *mt7623_pwrap_groups[] = { "pwrap" , };static const char *mt7623_rtc_groups[] = { "rtc" , };static const char *mt7623_spi_groups[] = { "spi0" , "spi2" , "spi2" , };static const char *mt7623_spdif_groups[] = { "spdif_in0_0" , "spdif_in0_1" ,"spdif_in1_0" , "spdif_in1_1" ,"spdif_out" , };static const char *mt7623_uart_groups[] = { "uart0_0_txd_rxd" ,"uart0_1_txd_rxd" ,"uart0_2_txd_rxd" ,"uart0_3_txd_rxd" ,"uart1_0_txd_rxd" ,"uart1_1_txd_rxd" ,"uart1_2_txd_rxd" ,"uart2_0_txd_rxd" ,"uart2_1_txd_rxd" ,"uart3_txd_rxd" ,"uart0_rts_cts" ,"uart1_rts_cts" ,"uart2_rts_cts" ,"uart3_rts_cts" , };static const char *mt7623_wdt_groups[] = { "watchdog_0" , "watchdog_1" , };static const struct function_desc mt7623_functions[] = {"audck" , mt7623_aud_clk),"disp" , mt7623_disp_pwm),"eth" , mt7623_ethernet),"sdio" , mt7623_ext_sdio),"hdmi" , mt7623_hdmi),"i2c" , mt7623_i2c),"i2s" , mt7623_i2s),"ir" , mt7623_ir),"lcd" , mt7623_lcd),"msdc" , mt7623_msdc),"nand" , mt7623_nandc),"otg" , mt7623_otg),"pcie" , mt7623_pcie),"pcm" , mt7623_pcm),"pwm" , mt7623_pwm),"pwrap" , mt7623_pwrap),"rtc" , mt7623_rtc),"spi" , mt7623_spi),"spdif" , mt7623_spdif),"uart" , mt7623_uart),"watchdog" , mt7623_wdt),static const struct mtk_eint_hw mt7623_eint_hw = {static struct mtk_pin_soc mt7623_data = {true ,/* * There are some specific pins have mux functions greater than 8, * and if we want to switch thees high modes we need to disable * bonding constraints firstly. static void mt7623_bonding_disable(struct platform_device *pdev)struct mtk_pinctrl *hw = platform_get_drvdata(pdev);static const struct of_device_id mt7623_pctrl_match[] = {"mediatek,mt7623-moore-pinctrl" , },static int mt7623_pinctrl_probe(struct platform_device *pdev)int err;if (err)return err;return 0;static struct platform_driver mtk_pinctrl_driver = {"mt7623-moore-pinctrl" ,static int __init mtk_pinctrl_init(void )return platform_driver_register(&mtk_pinctrl_driver);
Messung V0.5 in Prozent C=91 H=99 G=94
