// SPDX-License-Identifier: GPL-2.0-only /* * PIC32 pinctrl driver * * Joshua Henderson, <joshua.henderson@microchip.com> * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. #include <linux/clk.h>#include <linux/gpio/driver.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/irq.h>#include <linux/of.h>#include <linux/pinctrl/pinconf.h>#include <linux/pinctrl/pinconf-generic.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>#include <linux/platform_device.h>#include <linux/seq_file.h>#include <linux/slab.h>#include <linux/spinlock.h>#include <asm /mach-pic32/pic32.h>#include "pinctrl-utils.h" #include "pinctrl-pic32.h" #define PINS_PER_BANK 16#define PIC32_CNCON_EDGE 11#define PIC32_CNCON_ON 15#define PIN_CONFIG_MICROCHIP_DIGITAL (PIN_CONFIG_END + 1)#define PIN_CONFIG_MICROCHIP_ANALOG (PIN_CONFIG_END + 2)static const struct pinconf_generic_params pic32_mpp_bindings[] = {"microchip,digital" , PIN_CONFIG_MICROCHIP_DIGITAL, 0},"microchip,analog" , PIN_CONFIG_MICROCHIP_ANALOG, 0},#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)struct pic32_function {const char *name;const char * const *groups;unsigned int ngroups;struct pic32_pin_group {const char *name;unsigned int pin;struct pic32_desc_function *functions;struct pic32_desc_function {const char *name;struct pic32_gpio_bank {void __iomem *reg_base;int instance;struct gpio_chip gpio_chip;struct clk *clk;struct pic32_pinctrl {void __iomem *reg_base;struct device *dev;struct pinctrl_dev *pctldev;const struct pinctrl_pin_desc *pins;unsigned int npins;const struct pic32_function *functions;unsigned int nfunctions;const struct pic32_pin_group *groups;unsigned int ngroups;struct pic32_gpio_bank *gpio_banks;unsigned int nbanks;struct clk *clk;static const struct pinctrl_pin_desc pic32_pins[] = {"A0" ),"A1" ),"A2" ),"A3" ),"A4" ),"A5" ),"A6" ),"A7" ),"A8" ),"A9" ),"A10" ),"A11" ),"A12" ),"A13" ),"A14" ),"A15" ),"B0" ),"B1" ),"B2" ),"B3" ),"B4" ),"B5" ),"B6" ),"B7" ),"B8" ),"B9" ),"B10" ),"B11" ),"B12" ),"B13" ),"B14" ),"B15" ),"C1" ),"C2" ),"C3" ),"C4" ),"C12" ),"C13" ),"C14" ),"C15" ),"D0" ),"D1" ),"D2" ),"D3" ),"D4" ),"D5" ),"D6" ),"D7" ),"D9" ),"D10" ),"D11" ),"D12" ),"D13" ),"D14" ),"D15" ),"E0" ),"E1" ),"E2" ),"E3" ),"E4" ),"E5" ),"E6" ),"E7" ),"E8" ),"E9" ),"F0" ),"F1" ),"F2" ),"F3" ),"F4" ),"F5" ),"F8" ),"F12" ),"F13" ),"G0" ),"G1" ),"G6" ),"G7" ),"G8" ),"G9" ),"G12" ),"G13" ),"G14" ),"G15" ),"H0" ),"H1" ),"H2" ),"H3" ),"H4" ),"H5" ),"H6" ),"H7" ),"H8" ),"H9" ),"H10" ),"H11" ),"H12" ),"H13" ),"H14" ),"H15" ),"J0" ),"J1" ),"J2" ),"J3" ),"J4" ),"J5" ),"J6" ),"J7" ),"J8" ),"J9" ),"J10" ),"J11" ),"J12" ),"J13" ),"J14" ),"J15" ),"K0" ),"K1" ),"K2" ),"K3" ),"K4" ),"K5" ),"K6" ),"K7" ),static const char * const pic32_input0_group[] = {"D2" , "G8" , "F4" , "F1" , "B9" , "B10" , "C14" , "B5" ,"C1" , "D14" , "G1" , "A14" , "D6" ,static const char * const pic32_input1_group[] = {"D3" , "G7" , "F5" , "D11" , "F0" , "B1" , "E5" , "C13" ,"B3" , "C4" , "G0" , "A15" , "D7" ,static const char * const pic32_input2_group[] = {"D9" , "G6" , "B8" , "B15" , "D4" , "B0" , "E3" , "B7" ,"F12" , "D12" , "F8" , "C3" , "E9" ,static const char * const pic32_input3_group[] = {"G9" , "B14" , "D0" , "B6" , "D5" , "B2" , "F3" , "F13" ,"F2" , "C2" , "E8" ,static const char * const pic32_output0_group[] = {"D2" , "G8" , "F4" , "D10" , "F1" , "B9" , "B10" , "C14" ,"B5" , "C1" , "D14" , "G1" , "A14" , "D6" ,static const char * const pic32_output0_1_group[] = {"D2" , "G8" , "F4" , "D10" , "F1" , "B9" , "B10" , "C14" ,"B5" , "C1" , "D14" , "G1" , "A14" , "D6" ,"D3" , "G7" , "F5" , "D11" , "F0" , "B1" , "E5" , "C13" ,"B3" , "C4" , "D15" , "G0" , "A15" , "D7" ,static const char *const pic32_output1_group[] = {"D3" , "G7" , "F5" , "D11" , "F0" , "B1" , "E5" , "C13" ,"B3" , "C4" , "D15" , "G0" , "A15" , "D7" ,static const char *const pic32_output1_3_group[] = {"D3" , "G7" , "F5" , "D11" , "F0" , "B1" , "E5" , "C13" ,"B3" , "C4" , "D15" , "G0" , "A15" , "D7" ,"G9" , "B14" , "D0" , "B6" , "D5" , "B2" , "F3" , "F13" ,"C2" , "E8" , "F2" ,static const char * const pic32_output2_group[] = {"D9" , "G6" , "B8" , "B15" , "D4" , "B0" , "E3" , "B7" ,"F12" , "D12" , "F8" , "C3" , "E9" ,static const char * const pic32_output2_3_group[] = {"D9" , "G6" , "B8" , "B15" , "D4" , "B0" , "E3" , "B7" ,"F12" , "D12" , "F8" , "C3" , "E9" ,"G9" , "B14" , "D0" , "B6" , "D5" , "B2" , "F3" , "F13" ,"C2" , "E8" , "F2" ,static const char * const pic32_output3_group[] = {"G9" , "B14" , "D0" , "B6" , "D5" , "B2" , "F3" , "F13" ,"C2" , "E8" , "F2" ,#define FUNCTION(_name, _gr) \#_ name, \## _gr## _group, \## _gr## _group), \static const struct pic32_function pic32_functions[] = {#define PIC32_PINCTRL_GROUP(_pin, _name, ...) \#_ name, \struct pic32_desc_function[]){ \#define PIC32_PINCTRL_FUNCTION(_name, _muxreg, _muxval) \#_ name, \static const struct pic32_pin_group pic32_groups[] = {static inline struct pic32_gpio_bank *irqd_to_bank(struct irq_data *d)return gpiochip_get_data(irq_data_get_irq_chip_data(d));static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl,unsigned pin)return &pctl->gpio_banks[pin / PINS_PER_BANK];static int pic32_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);return pctl->ngroups;static const char *pic32_pinctrl_get_group_name(struct pinctrl_dev *pctldev,unsigned group)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);return pctl->groups[group].name;static int pic32_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,unsigned group,const unsigned **pins,unsigned *num_pins)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);return 0;static const struct pinctrl_ops pic32_pinctrl_ops = {static int pic32_pinmux_get_functions_count(struct pinctrl_dev *pctldev)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);return pctl->nfunctions;static const char *struct pinctrl_dev *pctldev, unsigned func)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);return pctl->functions[func].name;static int pic32_pinmux_get_function_groups(struct pinctrl_dev *pctldev,unsigned func,const char * const **groups,unsigned * const num_groups)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);return 0;static int pic32_pinmux_enable(struct pinctrl_dev *pctldev,unsigned func, unsigned group)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);const struct pic32_pin_group *pg = &pctl->groups[group];const struct pic32_function *pf = &pctl->functions[func];const char *fname = pf->name;struct pic32_desc_function *functions = pg->functions;while (functions->name) {if (!strcmp(functions->name, fname)) {"setting function %s reg 0x%x = %d\n" ,return 0;"cannot mux pin %u to function %u\n" , group, func);return -EINVAL;static int pic32_gpio_request_enable(struct pinctrl_dev *pctldev,struct pinctrl_gpio_range *range,unsigned offset)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);struct pic32_gpio_bank *bank = gpiochip_get_data(range->gc);"requesting gpio %d in bank %d with mask 0x%x\n" ,return 0;static int pic32_gpio_direction_input(struct gpio_chip *chip,unsigned offset)struct pic32_gpio_bank *bank = gpiochip_get_data(chip);return 0;static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset)struct pic32_gpio_bank *bank = gpiochip_get_data(chip);return !!(readl(bank->reg_base + PORT_REG) & BIT(offset));static int pic32_gpio_set(struct gpio_chip *chip, unsigned int offset,int value)struct pic32_gpio_bank *bank = gpiochip_get_data(chip);if (value)else return 0;static int pic32_gpio_direction_output(struct gpio_chip *chip,unsigned offset, int value)struct pic32_gpio_bank *bank = gpiochip_get_data(chip);return 0;static int pic32_gpio_set_direction(struct pinctrl_dev *pctldev,struct pinctrl_gpio_range *range,unsigned offset, bool input)struct gpio_chip *chip = range->gc;if (input)else return 0;static const struct pinmux_ops pic32_pinmux_ops = {static int pic32_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,unsigned long *config)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);unsigned param = pinconf_to_config_param(*config);switch (param) {case PIN_CONFIG_BIAS_PULL_UP:break ;case PIN_CONFIG_BIAS_PULL_DOWN:break ;case PIN_CONFIG_MICROCHIP_DIGITAL:break ;case PIN_CONFIG_MICROCHIP_ANALOG:break ;case PIN_CONFIG_DRIVE_OPEN_DRAIN:break ;case PIN_CONFIG_INPUT_ENABLE:break ;case PIN_CONFIG_OUTPUT:break ;default :"Property %u not supported\n" , param);return -ENOTSUPP;return 0;static int pic32_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,unsigned long *configs, unsigned num_configs)struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);unsigned param;unsigned int i;"setting pin %d bank %d mask 0x%x\n" ,for (i = 0; i < num_configs; i++) {switch (param) {case PIN_CONFIG_BIAS_PULL_UP:" pullup\n" );break ;case PIN_CONFIG_BIAS_PULL_DOWN:" pulldown\n" );break ;case PIN_CONFIG_MICROCHIP_DIGITAL:" digital\n" );break ;case PIN_CONFIG_MICROCHIP_ANALOG:" analog\n" );break ;case PIN_CONFIG_DRIVE_OPEN_DRAIN:" opendrain\n" );break ;case PIN_CONFIG_INPUT_ENABLE:break ;case PIN_CONFIG_OUTPUT:break ;default :"Property %u not supported\n" ,return -ENOTSUPP;return 0;static const struct pinconf_ops pic32_pinconf_ops = {true ,static struct pinctrl_desc pic32_pinctrl_desc = {"pic32-pinctrl" ,static int pic32_gpio_get_direction(struct gpio_chip *chip, unsigned offset)struct pic32_gpio_bank *bank = gpiochip_get_data(chip);if (readl(bank->reg_base + TRIS_REG) & BIT(offset))return GPIO_LINE_DIRECTION_IN;return GPIO_LINE_DIRECTION_OUT;static void pic32_gpio_irq_ack(struct irq_data *data)struct pic32_gpio_bank *bank = irqd_to_bank(data);static void pic32_gpio_irq_mask(struct irq_data *data)struct pic32_gpio_bank *bank = irqd_to_bank(data);static void pic32_gpio_irq_unmask(struct irq_data *data)struct pic32_gpio_bank *bank = irqd_to_bank(data);static unsigned int pic32_gpio_irq_startup(struct irq_data *data)struct gpio_chip *chip = irq_data_get_irq_chip_data(data);return 0;static int pic32_gpio_irq_set_type(struct irq_data *data, unsigned int type)struct pic32_gpio_bank *bank = irqd_to_bank(data);switch (type & IRQ_TYPE_SENSE_MASK) {case IRQ_TYPE_EDGE_RISING:/* enable RISE */ /* disable FALL */ /* enable EDGE */ break ;case IRQ_TYPE_EDGE_FALLING:/* disable RISE */ /* enable FALL */ /* enable EDGE */ break ;case IRQ_TYPE_EDGE_BOTH:/* enable RISE */ /* enable FALL */ /* enable EDGE */ break ;default :return -EINVAL;return 0;static u32 pic32_gpio_get_pending(struct gpio_chip *gc, unsigned long status)struct pic32_gpio_bank *bank = gpiochip_get_data(gc);if ((mask & cnen_rise) || (mask && cnne_fall))return pending;static void pic32_gpio_irq_handler(struct irq_desc *desc)struct gpio_chip *gc = irq_desc_get_handler_data(desc);struct pic32_gpio_bank *bank = gpiochip_get_data(gc);struct irq_chip *chip = irq_desc_get_chip(desc);unsigned long pending;unsigned int pin;#define GPIO_BANK(_bank, _npins) \"GPIO" #_ bank, \static struct pic32_gpio_bank pic32_gpio_banks[] = {static void pic32_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)struct pic32_gpio_bank *bank = irqd_to_bank(data);"GPIO%d" , bank->instance);static const struct irq_chip pic32_gpio_irq_chip = {static int pic32_pinctrl_probe(struct platform_device *pdev)struct pic32_pinctrl *pctl;int ret;sizeof (*pctl), GFP_KERNEL);if (!pctl)return -ENOMEM;if (IS_ERR(pctl->reg_base))return PTR_ERR(pctl->reg_base);if (IS_ERR(pctl->clk)) {"clk get failed\n" );return ret;if (ret) {"clk enable failed\n" );return ret;if (IS_ERR(pctl->pctldev)) {"Failed to register pinctrl device\n" );return PTR_ERR(pctl->pctldev);return 0;static int pic32_gpio_probe(struct platform_device *pdev)struct device_node *np = pdev->dev.of_node;struct pic32_gpio_bank *bank;int irq, ret;struct gpio_irq_chip *girq;if (of_property_read_u32(np, "microchip,gpio-bank" , &id)) {"microchip,gpio-bank property not found\n" );return -EINVAL;if (id >= ARRAY_SIZE(pic32_gpio_banks)) {"invalid microchip,gpio-bank property\n" );return -EINVAL;if (IS_ERR(bank->reg_base))return PTR_ERR(bank->reg_base);if (irq < 0)return irq;if (IS_ERR(bank->clk)) {"clk get failed\n" );return ret;if (ret) {"clk enable failed\n" );return ret;sizeof (*girq->parents),if (!girq->parents)return -ENOMEM;if (ret < 0) {"Failed to add GPIO chip %u: %d\n" ,return ret;return 0;static const struct of_device_id pic32_pinctrl_of_match[] = {"microchip,pic32mzda-pinctrl" , },static struct platform_driver pic32_pinctrl_driver = {"pic32-pinctrl" ,true ,static const struct of_device_id pic32_gpio_of_match[] = {"microchip,pic32mzda-gpio" , },static struct platform_driver pic32_gpio_driver = {"pic32-gpio" ,true ,static int __init pic32_gpio_register(void )return platform_driver_register(&pic32_gpio_driver);static int __init pic32_pinctrl_register(void )return platform_driver_register(&pic32_pinctrl_driver);
Messung V0.5 in Prozent C=92 H=93 G=92
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