// SPDX-License-Identifier: GPL-2.0 /* * Pinctrl / GPIO driver for StarFive JH7100 SoC * * Copyright ( C ) 2020 Shanghai StarFive Technology Co . , Ltd . * Copyright ( C ) 2021 Emil Renner Berthing < kernel @ esmil . dk > #include <linux/bits.h>#include <linux/clk.h>#include <linux/gpio/driver.h>#include <linux/io.h>#include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/reset.h>#include <linux/seq_file.h>#include <linux/spinlock.h>#include <linux/pinctrl/consumer.h>#include <linux/pinctrl/pinconf.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>#include "../core.h" #include "../pinctrl-utils.h" #include "../pinmux.h" #include "../pinconf.h" #define DRIVER_NAME "pinctrl-starfive" /* * Refer to Section 12 . GPIO Registers in the JH7100 data sheet : * https : //github.com/starfive-tech/JH7100_Docs #define NR_GPIOS 64 /* * Global enable for GPIO interrupts . If bit 0 is set to 1 the GPIO interrupts * are enabled . If set to 0 the GPIO interrupts are disabled . #define GPIOEN 0 x000/* * The following 32 - bit registers come in pairs , but only the offset of the * first register is defined . The first controls ( interrupts for ) GPIO 0 - 31 and * the second GPIO 32 - 63 . /* * Interrupt Type . If set to 1 the interrupt is edge - triggered . If set to 0 the * interrupt is level - triggered . #define GPIOIS 0 x010/* * Edge - Trigger Interrupt Type . If set to 1 the interrupt gets triggered on * both positive and negative edges . If set to 0 the interrupt is triggered by a * single edge . #define GPIOIBE 0 x018/* * Interrupt Trigger Polarity . If set to 1 the interrupt is triggered on a * rising edge ( edge - triggered ) or high level ( level - triggered ) . If set to 0 the * interrupt is triggered on a falling edge ( edge - triggered ) or low level * ( level - triggered ) . #define GPIOIEV 0 x020/* * Interrupt Mask . If set to 1 the interrupt is enabled ( unmasked ) . If set to 0 * the interrupt is disabled ( masked ) . Note that the current documentation is * wrong and says the exct opposite of this . #define GPIOIE 0 x028/* * Clear Edge - Triggered Interrupts . Write a 1 to clear the edge - triggered * interrupt . #define GPIOIC 0 x030/* * Edge - Triggered Interrupt Status . A 1 means the configured edge was detected . #define GPIORIS 0 x038/* * Interrupt Status after Masking . A 1 means the configured edge or level was * detected and not masked . #define GPIOMIS 0 x040/* * Data Value . Dynamically reflects the value of the GPIO pin . If 1 the pin is * a digital 1 and if 0 the pin is a digital 0 . #define GPIODIN 0 x048/* * From the data sheet section 12 . 2 , there are 64 32 - bit output data registers * and 64 output enable registers . Output data and output enable registers for * a given GPIO are contiguous . Eg . GPO0_DOUT_CFG is 0 x50 and GPO0_DOEN_CFG is * 0 x54 while GPO1_DOUT_CFG is 0 x58 and GPO1_DOEN_CFG is 0 x5c . The stride * between GPIO registers is effectively 8 , thus : GPOn_DOUT_CFG is 0 x50 + 8 n * and GPOn_DOEN_CFG is 0 x54 + 8 n . #define GPON_DOUT_CFG 0 x050#define GPON_DOEN_CFG 0 x054/* * From Section 12 . 3 , there are 75 input signal configuration registers which * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0 x250 and ending with * GPI_USB_OVER_CURRENT_CFG 0 x378 #define GPI_CFG_OFFSET 0 x250/* * Pad Control Bits . There are 16 pad control bits for each pin located in 103 * 32 - bit registers controlling PAD_GPIO [ 0 ] to PAD_GPIO [ 63 ] followed by * PAD_FUNC_SHARE [ 0 ] to PAD_FUNC_SHARE [ 141 ] . Odd numbered pins use the upper 16 * bit of each register . #define PAD_SLEW_RATE_MASK GENMASK(11 , 9 )#define PAD_SLEW_RATE_POS 9 #define PAD_BIAS_STRONG_PULL_UP BIT(8 )#define PAD_INPUT_ENABLE BIT(7 )#define PAD_INPUT_SCHMITT_ENABLE BIT(6 )#define PAD_BIAS_DISABLE BIT(5 )#define PAD_BIAS_PULL_DOWN BIT(4 )#define PAD_BIAS_MASK \#define PAD_DRIVE_STRENGTH_MASK GENMASK(3 , 0 )#define PAD_DRIVE_STRENGTH_POS 0 /* * From Section 11 , the IO_PADSHARE_SEL register can be programmed to select * one of seven pre - defined multiplexed signal groups on PAD_FUNC_SHARE and * PAD_GPIO pads . This is a global setting . #define IO_PADSHARE_SEL 0 x1a0/* * This just needs to be some number such that when * sfp - > gpio . pin_base = PAD_INVALID_GPIO then * starfive_pin_to_gpio ( sfp , validpin ) is never a valid GPIO number . * That is it should underflow and return something > = NR_GPIOS . #define PAD_INVALID_GPIO 0 x10000/* * The packed pinmux values from the device tree look like this : * * | 31 - 24 | 23 - 16 | 15 - 8 | 7 | 6 | 5 - 0 | * | dout | doen | din | dout rev | doen rev | gpio nr | * * . . but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this : * * | 31 | 30 - 8 | 7 - 0 | * | dout / doen rev | unused | dout / doen | static unsigned int starfive_pinmux_to_gpio(u32 v)return v & (NR_GPIOS - 1 );static u32 starfive_pinmux_to_dout(u32 v)return ((v & BIT(7 )) << (31 - 7 )) | ((v >> 24 ) & GENMASK(7 , 0 ));static u32 starfive_pinmux_to_doen(u32 v)return ((v & BIT(6 )) << (31 - 6 )) | ((v >> 16 ) & GENMASK(7 , 0 ));static u32 starfive_pinmux_to_din(u32 v)return (v >> 8 ) & GENMASK(7 , 0 );/* * The maximum GPIO output current depends on the chosen drive strength : * * DS : 0 1 2 3 4 5 6 7 * mA : 14 . 2 21 . 2 28 . 2 35 . 2 42 . 2 49 . 1 56 . 0 62 . 8 * * After rounding that is 7 * DS + 14 mA static u32 starfive_drive_strength_to_max_mA(u16 ds)return 7 * ds + 14 ;static u16 starfive_drive_strength_from_max_mA(u32 i)return (clamp(i, 14 U, 63 U) - 14 ) / 7 ;struct starfive_pinctrl {struct gpio_chip gc;struct pinctrl_gpio_range gpios;void __iomem *base;void __iomem *padctl;struct pinctrl_dev *pctl;struct mutex mutex; /* serialize adding groups and functions */ static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,unsigned int pin)return pin - sfp->gpios.pin_base;static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,unsigned int gpio)return sfp->gpios.pin_base + gpio;static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)struct gpio_chip *gc = irq_data_get_irq_chip_data(d);return container_of(gc, struct starfive_pinctrl, gc);static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)struct gpio_chip *gc = irq_desc_get_handler_data(desc);return container_of(gc, struct starfive_pinctrl, gc);static const struct pinctrl_pin_desc starfive_pins[] = {0 ), "GPIO[0]" ),1 ), "GPIO[1]" ),2 ), "GPIO[2]" ),3 ), "GPIO[3]" ),4 ), "GPIO[4]" ),5 ), "GPIO[5]" ),6 ), "GPIO[6]" ),7 ), "GPIO[7]" ),8 ), "GPIO[8]" ),9 ), "GPIO[9]" ),10 ), "GPIO[10]" ),11 ), "GPIO[11]" ),12 ), "GPIO[12]" ),13 ), "GPIO[13]" ),14 ), "GPIO[14]" ),15 ), "GPIO[15]" ),16 ), "GPIO[16]" ),17 ), "GPIO[17]" ),18 ), "GPIO[18]" ),19 ), "GPIO[19]" ),20 ), "GPIO[20]" ),21 ), "GPIO[21]" ),22 ), "GPIO[22]" ),23 ), "GPIO[23]" ),24 ), "GPIO[24]" ),25 ), "GPIO[25]" ),26 ), "GPIO[26]" ),27 ), "GPIO[27]" ),28 ), "GPIO[28]" ),29 ), "GPIO[29]" ),30 ), "GPIO[30]" ),31 ), "GPIO[31]" ),32 ), "GPIO[32]" ),33 ), "GPIO[33]" ),34 ), "GPIO[34]" ),35 ), "GPIO[35]" ),36 ), "GPIO[36]" ),37 ), "GPIO[37]" ),38 ), "GPIO[38]" ),39 ), "GPIO[39]" ),40 ), "GPIO[40]" ),41 ), "GPIO[41]" ),42 ), "GPIO[42]" ),43 ), "GPIO[43]" ),44 ), "GPIO[44]" ),45 ), "GPIO[45]" ),46 ), "GPIO[46]" ),47 ), "GPIO[47]" ),48 ), "GPIO[48]" ),49 ), "GPIO[49]" ),50 ), "GPIO[50]" ),51 ), "GPIO[51]" ),52 ), "GPIO[52]" ),53 ), "GPIO[53]" ),54 ), "GPIO[54]" ),55 ), "GPIO[55]" ),56 ), "GPIO[56]" ),57 ), "GPIO[57]" ),58 ), "GPIO[58]" ),59 ), "GPIO[59]" ),60 ), "GPIO[60]" ),61 ), "GPIO[61]" ),62 ), "GPIO[62]" ),63 ), "GPIO[63]" ),0 ), "FUNC_SHARE[0]" ),1 ), "FUNC_SHARE[1]" ),2 ), "FUNC_SHARE[2]" ),3 ), "FUNC_SHARE[3]" ),4 ), "FUNC_SHARE[4]" ),5 ), "FUNC_SHARE[5]" ),6 ), "FUNC_SHARE[6]" ),7 ), "FUNC_SHARE[7]" ),8 ), "FUNC_SHARE[8]" ),9 ), "FUNC_SHARE[9]" ),10 ), "FUNC_SHARE[10]" ),11 ), "FUNC_SHARE[11]" ),12 ), "FUNC_SHARE[12]" ),13 ), "FUNC_SHARE[13]" ),14 ), "FUNC_SHARE[14]" ),15 ), "FUNC_SHARE[15]" ),16 ), "FUNC_SHARE[16]" ),17 ), "FUNC_SHARE[17]" ),18 ), "FUNC_SHARE[18]" ),19 ), "FUNC_SHARE[19]" ),20 ), "FUNC_SHARE[20]" ),21 ), "FUNC_SHARE[21]" ),22 ), "FUNC_SHARE[22]" ),23 ), "FUNC_SHARE[23]" ),24 ), "FUNC_SHARE[24]" ),25 ), "FUNC_SHARE[25]" ),26 ), "FUNC_SHARE[26]" ),27 ), "FUNC_SHARE[27]" ),28 ), "FUNC_SHARE[28]" ),29 ), "FUNC_SHARE[29]" ),30 ), "FUNC_SHARE[30]" ),31 ), "FUNC_SHARE[31]" ),32 ), "FUNC_SHARE[32]" ),33 ), "FUNC_SHARE[33]" ),34 ), "FUNC_SHARE[34]" ),35 ), "FUNC_SHARE[35]" ),36 ), "FUNC_SHARE[36]" ),37 ), "FUNC_SHARE[37]" ),38 ), "FUNC_SHARE[38]" ),39 ), "FUNC_SHARE[39]" ),40 ), "FUNC_SHARE[40]" ),41 ), "FUNC_SHARE[41]" ),42 ), "FUNC_SHARE[42]" ),43 ), "FUNC_SHARE[43]" ),44 ), "FUNC_SHARE[44]" ),45 ), "FUNC_SHARE[45]" ),46 ), "FUNC_SHARE[46]" ),47 ), "FUNC_SHARE[47]" ),48 ), "FUNC_SHARE[48]" ),49 ), "FUNC_SHARE[49]" ),50 ), "FUNC_SHARE[50]" ),51 ), "FUNC_SHARE[51]" ),52 ), "FUNC_SHARE[52]" ),53 ), "FUNC_SHARE[53]" ),54 ), "FUNC_SHARE[54]" ),55 ), "FUNC_SHARE[55]" ),56 ), "FUNC_SHARE[56]" ),57 ), "FUNC_SHARE[57]" ),58 ), "FUNC_SHARE[58]" ),59 ), "FUNC_SHARE[59]" ),60 ), "FUNC_SHARE[60]" ),61 ), "FUNC_SHARE[61]" ),62 ), "FUNC_SHARE[62]" ),63 ), "FUNC_SHARE[63]" ),64 ), "FUNC_SHARE[64]" ),65 ), "FUNC_SHARE[65]" ),66 ), "FUNC_SHARE[66]" ),67 ), "FUNC_SHARE[67]" ),68 ), "FUNC_SHARE[68]" ),69 ), "FUNC_SHARE[69]" ),70 ), "FUNC_SHARE[70]" ),71 ), "FUNC_SHARE[71]" ),72 ), "FUNC_SHARE[72]" ),73 ), "FUNC_SHARE[73]" ),74 ), "FUNC_SHARE[74]" ),75 ), "FUNC_SHARE[75]" ),76 ), "FUNC_SHARE[76]" ),77 ), "FUNC_SHARE[77]" ),78 ), "FUNC_SHARE[78]" ),79 ), "FUNC_SHARE[79]" ),80 ), "FUNC_SHARE[80]" ),81 ), "FUNC_SHARE[81]" ),82 ), "FUNC_SHARE[82]" ),83 ), "FUNC_SHARE[83]" ),84 ), "FUNC_SHARE[84]" ),85 ), "FUNC_SHARE[85]" ),86 ), "FUNC_SHARE[86]" ),87 ), "FUNC_SHARE[87]" ),88 ), "FUNC_SHARE[88]" ),89 ), "FUNC_SHARE[89]" ),90 ), "FUNC_SHARE[90]" ),91 ), "FUNC_SHARE[91]" ),92 ), "FUNC_SHARE[92]" ),93 ), "FUNC_SHARE[93]" ),94 ), "FUNC_SHARE[94]" ),95 ), "FUNC_SHARE[95]" ),96 ), "FUNC_SHARE[96]" ),97 ), "FUNC_SHARE[97]" ),98 ), "FUNC_SHARE[98]" ),99 ), "FUNC_SHARE[99]" ),100 ), "FUNC_SHARE[100]" ),101 ), "FUNC_SHARE[101]" ),102 ), "FUNC_SHARE[102]" ),103 ), "FUNC_SHARE[103]" ),104 ), "FUNC_SHARE[104]" ),105 ), "FUNC_SHARE[105]" ),106 ), "FUNC_SHARE[106]" ),107 ), "FUNC_SHARE[107]" ),108 ), "FUNC_SHARE[108]" ),109 ), "FUNC_SHARE[109]" ),110 ), "FUNC_SHARE[110]" ),111 ), "FUNC_SHARE[111]" ),112 ), "FUNC_SHARE[112]" ),113 ), "FUNC_SHARE[113]" ),114 ), "FUNC_SHARE[114]" ),115 ), "FUNC_SHARE[115]" ),116 ), "FUNC_SHARE[116]" ),117 ), "FUNC_SHARE[117]" ),118 ), "FUNC_SHARE[118]" ),119 ), "FUNC_SHARE[119]" ),120 ), "FUNC_SHARE[120]" ),121 ), "FUNC_SHARE[121]" ),122 ), "FUNC_SHARE[122]" ),123 ), "FUNC_SHARE[123]" ),124 ), "FUNC_SHARE[124]" ),125 ), "FUNC_SHARE[125]" ),126 ), "FUNC_SHARE[126]" ),127 ), "FUNC_SHARE[127]" ),128 ), "FUNC_SHARE[128]" ),129 ), "FUNC_SHARE[129]" ),130 ), "FUNC_SHARE[130]" ),131 ), "FUNC_SHARE[131]" ),132 ), "FUNC_SHARE[132]" ),133 ), "FUNC_SHARE[133]" ),134 ), "FUNC_SHARE[134]" ),135 ), "FUNC_SHARE[135]" ),136 ), "FUNC_SHARE[136]" ),137 ), "FUNC_SHARE[137]" ),138 ), "FUNC_SHARE[138]" ),139 ), "FUNC_SHARE[139]" ),140 ), "FUNC_SHARE[140]" ),141 ), "FUNC_SHARE[141]" ),#ifdef CONFIG_DEBUG_FSstatic void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,struct seq_file *s,unsigned int pin)struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);unsigned int gpio = starfive_pin_to_gpio(sfp, pin);void __iomem *reg;if (gpio >= NR_GPIOS)return ;8 * gpio;0 x000);0 x004);"dout=%lu%s doen=%lu%s" ,7 , 0 ), (dout & BIT(31 )) ? "r" : "" ,7 , 0 ), (doen & BIT(31 )) ? "r" : "" );#else #define starfive_pin_dbg_show NULL#endif static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,struct device_node *np,struct pinctrl_map **maps,unsigned int *num_maps)struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);struct device *dev = sfp->gc.parent;struct pinctrl_map *map;const char **pgnames;const char *grpname;int ngroups;int *pins;int nmaps;int ret;0 ;0 ;int npinmux = of_property_count_u32_elems(child, "pinmux" );int npins = of_property_count_u32_elems(child, "pins" );if (npinmux > 0 && npins > 0 ) {"invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n" ,return -EINVAL;if (npinmux == 0 && npins == 0 ) {"invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n" ,return -EINVAL;if (npinmux > 0 )2 ;else 1 ;1 ;sizeof (*pgnames), GFP_KERNEL);if (!pgnames)return -ENOMEM;sizeof (*map), GFP_KERNEL);if (!map)return -ENOMEM;0 ;0 ;int npins;int i;"%pOFn.%pOFn" , np, child);if (!grpname) {goto free_map;if ((npins = of_property_count_u32_elems(child, "pinmux" )) > 0 ) {sizeof (*pins), GFP_KERNEL);if (!pins) {goto free_map;sizeof (*pinmux), GFP_KERNEL);if (!pinmux) {goto free_map;"pinmux" , pinmux, npins);if (ret)goto free_map;for (i = 0 ; i < npins; i++) {unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);1 ;else if ((npins = of_property_count_u32_elems(child, "pins" )) > 0 ) {sizeof (*pins), GFP_KERNEL);if (!pins) {goto free_map;for (i = 0 ; i < npins; i++) {"pins" , i, &v);if (ret)goto free_map;else {goto free_map;if (ret < 0 ) {"error adding group %s: %d\n" , grpname, ret);goto free_map;if (ret) {"error parsing pin config of group %s: %d\n" ,goto free_map;/* don't create a map if there are no pinconf settings */ if (map[nmaps].data.configs.num_configs == 0 )continue ;1 ;if (ret < 0 ) {"error adding function %s: %d\n" , np->name, ret);goto free_map;return 0 ;return ret;static const struct pinctrl_ops starfive_pinctrl_ops = {static int starfive_set_mux(struct pinctrl_dev *pctldev,unsigned int fsel, unsigned int gsel)struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);struct device *dev = sfp->gc.parent;const struct group_desc *group;const u32 *pinmux;unsigned int i;if (!group)return -EINVAL;for (i = 0 ; i < group->grp.npins; i++) {unsigned int gpio = starfive_pinmux_to_gpio(v);void __iomem *reg_dout;void __iomem *reg_doen;void __iomem *reg_din;unsigned long flags;"GPIO%u: dout=0x%x doen=0x%x din=0x%x\n" ,8 * gpio;8 * gpio;if (din != GPI_NONE)4 * din;else if (reg_din)2 , reg_din);return 0 ;static const struct pinmux_ops starfive_pinmux_ops = {true ,static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,unsigned int pin)void __iomem *reg = sfp->padctl + 4 * (pin / 2 );int shift = 16 * (pin % 2 );return readl_relaxed(reg) >> shift;static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,unsigned int pin,void __iomem *reg = sfp->padctl + 4 * (pin / 2 );int shift = 16 * (pin % 2 );unsigned long flags;"padctl_rmw(%u, 0x%03x, 0x%03x)\n" , pin, _mask, _value);#define PIN_CONFIG_STARFIVE_STRONG_PULL_UP (PIN_CONFIG_END + 1 )static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {"starfive,strong-pull-up" , PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },#ifdef CONFIG_DEBUG_FSstatic const struct pin_config_item starfive_pinconf_custom_conf_items[] = {"input bias strong pull-up" , NULL, false ),#else #define starfive_pinconf_custom_conf_items NULL#endif static int starfive_pinconf_get(struct pinctrl_dev *pctldev,unsigned int pin, unsigned long *config)struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);int param = pinconf_to_config_param(*config);bool enabled;switch (param) {case PIN_CONFIG_BIAS_DISABLE:0 ;break ;case PIN_CONFIG_BIAS_PULL_DOWN:1 ;break ;case PIN_CONFIG_BIAS_PULL_UP:1 ;break ;case PIN_CONFIG_DRIVE_STRENGTH:break ;case PIN_CONFIG_INPUT_ENABLE:break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:break ;case PIN_CONFIG_SLEW_RATE:break ;case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:break ;default :return -ENOTSUPP;return enabled ? 0 : -EINVAL;static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,unsigned int gsel, unsigned long *config)const struct group_desc *group;if (!group)return -EINVAL;return starfive_pinconf_get(pctldev, group->grp.pins[0 ], config);static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,unsigned int gsel,unsigned long *configs,unsigned int num_configs)struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);const struct group_desc *group;int i;if (!group)return -EINVAL;0 ;0 ;for (i = 0 ; i < num_configs; i++) {int param = pinconf_to_config_param(configs[i]);switch (param) {case PIN_CONFIG_BIAS_DISABLE:break ;case PIN_CONFIG_BIAS_PULL_DOWN:if (arg == 0 )return -ENOTSUPP;break ;case PIN_CONFIG_BIAS_PULL_UP:if (arg == 0 )return -ENOTSUPP;break ;case PIN_CONFIG_DRIVE_STRENGTH:break ;case PIN_CONFIG_INPUT_ENABLE:if (arg)else break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:if (arg)else break ;case PIN_CONFIG_SLEW_RATE:break ;case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:if (arg) {else {break ;default :return -ENOTSUPP;for (i = 0 ; i < group->grp.npins; i++)return 0 ;#ifdef CONFIG_DEBUG_FSstatic void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,struct seq_file *s, unsigned int pin)struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);" (0x%03x)" , value);#else #define starfive_pinconf_dbg_show NULL#endif static const struct pinconf_ops starfive_pinconf_ops = {true ,static const struct pinctrl_desc starfive_desc = {static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;if (readl_relaxed(doen) == GPO_ENABLE)return GPIO_LINE_DIRECTION_OUT;return GPIO_LINE_DIRECTION_IN;static int starfive_gpio_direction_input(struct gpio_chip *gc,unsigned int gpio)struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;unsigned long flags;/* enable input and schmitt trigger */ return 0 ;static int starfive_gpio_direction_output(struct gpio_chip *gc,unsigned int gpio, int value)struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;unsigned long flags;/* disable input, schmitt trigger and bias */ return 0 ;static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32 );return !!(readl_relaxed(din) & BIT(gpio % 32 ));static int starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,int value)struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;unsigned long flags;return 0 ;static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,unsigned long config)struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);switch (pinconf_to_config_param(config)) {case PIN_CONFIG_BIAS_DISABLE:break ;case PIN_CONFIG_BIAS_PULL_DOWN:if (arg == 0 )return -ENOTSUPP;break ;case PIN_CONFIG_BIAS_PULL_UP:if (arg == 0 )return -ENOTSUPP;0 ;break ;case PIN_CONFIG_DRIVE_PUSH_PULL:return 0 ;case PIN_CONFIG_INPUT_ENABLE:0 ;break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:0 ;break ;default :return -ENOTSUPP;return 0 ;static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);/* * sfp - > gpios . pin_base depends on the chosen signal group * and is set in starfive_probe ( ) return 0 ;static void starfive_irq_ack(struct irq_data *d)struct starfive_pinctrl *sfp = starfive_from_irq_data(d);void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32 );32 );unsigned long flags;static void starfive_irq_mask(struct irq_data *d)struct starfive_pinctrl *sfp = starfive_from_irq_data(d);void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32 );32 );unsigned long flags;static void starfive_irq_mask_ack(struct irq_data *d)struct starfive_pinctrl *sfp = starfive_from_irq_data(d);void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32 );void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32 );32 );unsigned long flags;static void starfive_irq_unmask(struct irq_data *d)struct starfive_pinctrl *sfp = starfive_from_irq_data(d);void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32 );32 );unsigned long flags;static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)struct starfive_pinctrl *sfp = starfive_from_irq_data(d);void __iomem *base = sfp->base + 4 * (gpio / 32 );32 );unsigned long flags;switch (trigger) {case IRQ_TYPE_EDGE_RISING:/* 1: edge triggered */ 0 ; /* 0: single edge */ /* 1: rising edge */ break ;case IRQ_TYPE_EDGE_FALLING:/* 1: edge triggered */ 0 ; /* 0: single edge */ 0 ; /* 0: falling edge */ break ;case IRQ_TYPE_EDGE_BOTH:/* 1: edge triggered */ /* 1: both edges */ 0 ; /* 0: ignored */ break ;case IRQ_TYPE_LEVEL_HIGH:0 ; /* 0: level triggered */ 0 ; /* 0: ignored */ /* 1: high level */ break ;case IRQ_TYPE_LEVEL_LOW:0 ; /* 0: level triggered */ 0 ; /* 0: ignored */ 0 ; /* 0: low level */ break ;default :return -EINVAL;if (trigger & IRQ_TYPE_EDGE_BOTH)else return 0 ;static const struct irq_chip starfive_irq_chip = {"StarFive GPIO" ,static void starfive_gpio_irq_handler(struct irq_desc *desc)struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);struct irq_chip *chip = irq_desc_get_chip(desc);unsigned long mis;unsigned int pin;0 );32 )4 );32 )32 );static int starfive_gpio_init_hw(struct gpio_chip *gc)struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);/* mask all GPIO interrupts */ 0 , sfp->base + GPIOIE + 0 );0 , sfp->base + GPIOIE + 4 );/* clear edge interrupt flags */ 0 U, sfp->base + GPIOIC + 0 );0 U, sfp->base + GPIOIC + 4 );/* enable GPIO interrupts */ 1 , sfp->base + GPIOEN);return 0 ;static void starfive_disable_clock(void *data)static int starfive_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct starfive_pinctrl *sfp;struct reset_control *rst;struct clk *clk;int ret;sizeof (*sfp), GFP_KERNEL);if (!sfp)return -ENOMEM;"gpio" );if (IS_ERR(sfp->base))return PTR_ERR(sfp->base);"padctl" );if (IS_ERR(sfp->padctl))return PTR_ERR(sfp->padctl);if (IS_ERR(clk))return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n" );if (IS_ERR(rst))return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n" );if (ret)return dev_err_probe(dev, ret, "could not enable clock\n" );if (ret)return ret;/* * We don ' t want to assert reset and risk undoing pin muxing for the * early boot serial console , but let ' s make sure the reset line is * deasserted in case someone runs a really minimal bootloader . if (ret)return dev_err_probe(dev, ret, "could not deassert reset\n" );if (ret)return dev_err_probe(dev, ret, "could not register pinctrl driver\n" );if (!of_property_read_u32(dev->of_node, "starfive,signal-group" , &value)) {if (value > 6 )return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n" , value);switch (value) {case 0 :goto out_pinctrl_enable;case 1 :0 );break ;case 2 :72 );break ;case 3 :70 );break ;case 4 : case 5 : case 6 :0 );break ;default :return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n" , value);1 ;1 ;sizeof (*sfp->gc.irq.parents), GFP_KERNEL);if (!sfp->gc.irq.parents)return -ENOMEM;0 );if (ret < 0 )return ret;0 ] = ret;if (ret)return dev_err_probe(dev, ret, "could not register gpiochip\n" );return pinctrl_enable(sfp->pctl);static const struct of_device_id starfive_of_match[] = {"starfive,jh7100-pinctrl" },/* sentinel */ } static struct platform_driver starfive_pinctrl_driver = {"Pinctrl driver for StarFive SoCs" );"Emil Renner Berthing <kernel@esmil.dk>" );"GPL v2" );
Messung V0.5 in Prozent C=96 H=95 G=95
¤ Dauer der Verarbeitung: 0.18 Sekunden
(vorverarbeitet am 2026-09-29)
¤ *© Formatika GbR, Deutschland
