/* * This file is part of the Chelsio FCoE driver for Linux. * * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE.
*/
int csio_is_hw_ready(struct csio_hw *hw)
{ return csio_match_state(hw, csio_hws_ready);
}
int csio_is_hw_removing(struct csio_hw *hw)
{ return csio_match_state(hw, csio_hws_removing);
}
/* * csio_hw_wait_op_done_val - wait until an operation is completed * @hw: the HW module * @reg: the register to check for completion * @mask: a single-bit field within @reg that indicates completion * @polarity: the value of the field when the operation is completed * @attempts: number of check iterations * @delay: delay in usecs between iterations * @valp: where to store the value of the register at completion time * * Wait until an operation is completed by checking a bit in a register * up to @attempts times. If @valp is not NULL the value of the register * at the time it indicated completion is stored there. Returns 0 if the * operation completes and -EAGAIN otherwise.
*/ int
csio_hw_wait_op_done_val(struct csio_hw *hw, int reg, uint32_t mask, int polarity, int attempts, int delay, uint32_t *valp)
{
uint32_t val; while (1) {
val = csio_rd_reg32(hw, reg);
if (!!(val & mask) == polarity) { if (valp)
*valp = val; return 0;
}
if (--attempts == 0) return -EAGAIN; if (delay)
udelay(delay);
}
}
/* * csio_hw_tp_wr_bits_indirect - set/clear bits in an indirect TP register * @hw: the adapter * @addr: the indirect TP register address * @mask: specifies the field within the register to modify * @val: new value for the field * * Sets a field of an indirect TP register to the given value.
*/ void
csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsignedint addr, unsignedint mask, unsignedint val)
{
csio_wr_reg32(hw, addr, TP_PIO_ADDR_A);
val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask;
csio_wr_reg32(hw, val, TP_PIO_DATA_A);
}
/* * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
*/ #define EEPROM_MAX_RD_POLL 40 #define EEPROM_MAX_WR_POLL 6 #define EEPROM_STAT_ADDR 0x7bfc #define VPD_BASE 0x400 #define VPD_BASE_OLD 0 #define VPD_LEN 1024 #define VPD_INFO_FLD_HDR_SIZE 3
/* * csio_hw_seeprom_read - read a serial EEPROM location * @hw: hw to read * @addr: EEPROM virtual address * @data: where to store the read data * * Read a 32-bit word from a location in serial EEPROM using the card's PCI * VPD capability. Note that this function must be called with a virtual * address.
*/ staticint
csio_hw_seeprom_read(struct csio_hw *hw, uint32_t addr, uint32_t *data)
{
uint16_t val = 0; int attempts = EEPROM_MAX_RD_POLL;
uint32_t base = hw->params.pci.vpd_cap_addr;
if (addr >= EEPROMVSIZE || (addr & 3)) return -EINVAL;
pci_write_config_word(hw->pdev, base + PCI_VPD_ADDR, (uint16_t)addr);
do {
udelay(10);
pci_read_config_word(hw->pdev, base + PCI_VPD_ADDR, &val);
} while (!(val & PCI_VPD_ADDR_F) && --attempts);
pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data);
*data = le32_to_cpu(*(__le32 *)data);
return 0;
}
/* * Partial EEPROM Vital Product Data structure. Includes only the ID and * VPD-R sections.
*/ struct t4_vpd_hdr {
u8 id_tag;
u8 id_len[2];
u8 id_data[ID_LEN];
u8 vpdr_tag;
u8 vpdr_len[2];
};
/* * csio_hw_get_vpd_keyword_val - Locates an information field keyword in * the VPD * @v: Pointer to buffered vpd data structure * @kw: The keyword to search for * * Returns the value of the information field keyword or * -EINVAL otherwise.
*/ staticint
csio_hw_get_vpd_keyword_val(conststruct t4_vpd_hdr *v, constchar *kw)
{
int32_t i;
int32_t offset , len; const uint8_t *buf = &v->id_tag; const uint8_t *vpdr_len = &v->vpdr_tag;
offset = sizeof(struct t4_vpd_hdr);
len = (uint16_t)vpdr_len[1] + ((uint16_t)vpdr_len[2] << 8);
if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) return -EINVAL;
for (i = offset; (i + VPD_INFO_FLD_HDR_SIZE) <= (offset + len);) { if (memcmp(buf + i , kw, 2) == 0) {
i += VPD_INFO_FLD_HDR_SIZE; return i;
}
i += VPD_INFO_FLD_HDR_SIZE + buf[i+2];
}
return -EINVAL;
}
staticint
csio_pci_capability(struct pci_dev *pdev, int cap, int *pos)
{
*pos = pci_find_capability(pdev, cap); if (*pos) return 0;
return -1;
}
/* * csio_hw_get_vpd_params - read VPD parameters from VPD EEPROM * @hw: HW module * @p: where to store the parameters * * Reads card parameters stored in VPD EEPROM.
*/ staticint
csio_hw_get_vpd_params(struct csio_hw *hw, struct csio_vpd *p)
{ int i, ret, ec, sn, addr;
uint8_t *vpd, csum; conststruct t4_vpd_hdr *v; /* To get around compilation warning from strstrip */ char __always_unused *s;
if (csio_is_valid_vpd(hw)) return 0;
ret = csio_pci_capability(hw->pdev, PCI_CAP_ID_VPD,
&hw->params.pci.vpd_cap_addr); if (ret) return -EINVAL;
vpd = kzalloc(VPD_LEN, GFP_ATOMIC); if (vpd == NULL) return -ENOMEM;
/* * Card information normally starts at VPD_BASE but early cards had * it at 0.
*/
ret = csio_hw_seeprom_read(hw, VPD_BASE, (uint32_t *)(vpd));
addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD;
for (i = 0; i < VPD_LEN; i += 4) {
ret = csio_hw_seeprom_read(hw, addr + i, (uint32_t *)(vpd + i)); if (ret) {
kfree(vpd); return ret;
}
}
/* Reset the VPD flag! */
hw->flags &= (~CSIO_HWF_VPD_VALID);
v = (conststruct t4_vpd_hdr *)vpd;
#define FIND_VPD_KW(var, name) do { \
var = csio_hw_get_vpd_keyword_val(v, name); \ if (var < 0) { \
csio_err(hw, "missing VPD keyword " name "\n"); \
kfree(vpd); \ return -EINVAL; \
} \
} while (0)
FIND_VPD_KW(i, "RV"); for (csum = 0; i >= 0; i--)
csum += vpd[i];
memcpy(p->id, v->id_data, ID_LEN);
s = strstrip(p->id);
memcpy(p->ec, vpd + ec, EC_LEN);
s = strstrip(p->ec);
i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
s = strstrip(p->sn);
csio_valid_vpd_copied(hw);
kfree(vpd); return 0;
}
/* * csio_hw_sf1_read - read data from the serial flash * @hw: the HW module * @byte_cnt: number of bytes to read * @cont: whether another operation will be chained * @lock: whether to lock SF for PL access only * @valp: where to store the read data * * Reads up to 4 bytes of data from the serial flash. The location of * the read needs to be specified prior to calling this by issuing the * appropriate commands to the serial flash.
*/ staticint
csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont,
int32_t lock, uint32_t *valp)
{ int ret;
if (!byte_cnt || byte_cnt > 4) return -EINVAL; if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) return -EBUSY;
/* * csio_hw_sf1_write - write data to the serial flash * @hw: the HW module * @byte_cnt: number of bytes to write * @cont: whether another operation will be chained * @lock: whether to lock SF for PL access only * @val: value to write * * Writes up to 4 bytes of data to the serial flash. The location of * the write needs to be specified prior to calling this by issuing the * appropriate commands to the serial flash.
*/ staticint
csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont,
int32_t lock, uint32_t val)
{ if (!byte_cnt || byte_cnt > 4) return -EINVAL; if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) return -EBUSY;
/* * csio_hw_flash_wait_op - wait for a flash operation to complete * @hw: the HW module * @attempts: max number of polls of the status register * @delay: delay between polls in ms * * Wait for a flash operation to complete by polling the status register.
*/ staticint
csio_hw_flash_wait_op(struct csio_hw *hw, int32_t attempts, int32_t delay)
{ int ret;
uint32_t status;
while (1) {
ret = csio_hw_sf1_write(hw, 1, 1, 1, SF_RD_STATUS); if (ret != 0) return ret;
ret = csio_hw_sf1_read(hw, 1, 0, 1, &status); if (ret != 0) return ret;
if (!(status & 1)) return 0; if (--attempts == 0) return -EAGAIN; if (delay)
msleep(delay);
}
}
/* * csio_hw_read_flash - read words from serial flash * @hw: the HW module * @addr: the start address for the read * @nwords: how many 32-bit words to read * @data: where to store the read data * @byte_oriented: whether to store data as bytes or as words * * Read the specified number of 32-bit words from the serial flash. * If @byte_oriented is set the read data is stored as a byte array * (i.e., big-endian), otherwise as 32-bit words in the platform's * natural endianess.
*/ staticint
csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords,
uint32_t *data, int32_t byte_oriented)
{ int ret;
ret = csio_hw_sf1_write(hw, 4, 1, 0, addr); if (ret != 0) return ret;
ret = csio_hw_sf1_read(hw, 1, 1, 0, data); if (ret != 0) return ret;
for ( ; nwords; nwords--, data++) {
ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data); if (nwords == 1)
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ if (ret) return ret; if (byte_oriented)
*data = (__force __u32) htonl(*data);
} return 0;
}
/* * csio_hw_write_flash - write up to a page of data to the serial flash * @hw: the hw * @addr: the start address to write * @n: length of data to write in bytes * @data: the data to write * * Writes up to a page of data (256 bytes) to the serial flash starting * at the given address. All the data must be written to the same page.
*/ staticint
csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
uint32_t n, const uint8_t *data)
{ int ret = -EINVAL;
uint32_t buf[64];
uint32_t i, c, left, val, offset = addr & 0xff;
if (addr >= hw->params.sf_size || offset + n > SF_PAGE_SIZE) return -EINVAL;
val = swab32(addr) | SF_PROG_PAGE;
ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE); if (ret != 0) goto unlock;
ret = csio_hw_sf1_write(hw, 4, 1, 1, val); if (ret != 0) goto unlock;
for (left = n; left; left -= c) {
c = min(left, 4U); for (val = 0, i = 0; i < c; ++i)
val = (val << 8) + *data++;
ret = csio_hw_sf1_write(hw, c, c != left, 1, val); if (ret) goto unlock;
}
ret = csio_hw_flash_wait_op(hw, 8, 1); if (ret) goto unlock;
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
/* Read the page to verify the write succeeded */
ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); if (ret) return ret;
if (memcmp(data - n, (uint8_t *)buf + offset, n)) {
csio_err(hw, "failed to correctly write the flash page at %#x\n",
addr); return -EINVAL;
}
/* * csio_hw_flash_erase_sectors - erase a range of flash sectors * @hw: the HW module * @start: the first sector to erase * @end: the last sector to erase * * Erases the sectors in the given inclusive range.
*/ staticint
csio_hw_flash_erase_sectors(struct csio_hw *hw, int32_t start, int32_t end)
{ int ret = 0;
while (start <= end) {
ret = csio_hw_sf1_write(hw, 1, 0, 1, SF_WR_ENABLE); if (ret != 0) goto out;
ret = csio_hw_sf1_write(hw, 4, 0, 1,
SF_ERASE_SECTOR | (start << 8)); if (ret != 0) goto out;
ret = csio_hw_flash_wait_op(hw, 14, 500); if (ret != 0) goto out;
start++;
}
out: if (ret)
csio_err(hw, "erase of flash sector %d failed, error %d\n",
start, ret);
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ return 0;
}
/* * csio_hw_get_fw_version - read the firmware version * @hw: HW module * @vers: where to place the version * * Reads the FW version from flash.
*/ staticint
csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers)
{ return csio_hw_read_flash(hw, FLASH_FW_START +
offsetof(struct fw_hdr, fw_ver), 1,
vers, 0);
}
/* * csio_hw_get_tp_version - read the TP microcode version * @hw: HW module * @vers: where to place the version * * Reads the TP microcode version from flash.
*/ staticint
csio_hw_get_tp_version(struct csio_hw *hw, u32 *vers)
{ return csio_hw_read_flash(hw, FLASH_FW_START +
offsetof(struct fw_hdr, tp_microcode_ver), 1,
vers, 0);
}
ret = csio_hw_flash_erase_sectors(hw, FLASH_FW_START_SEC,
FLASH_FW_START_SEC + i - 1); if (ret) {
csio_err(hw, "Flash Erase failed\n"); goto out;
}
/* * We write the correct version at the end so the driver can see a bad * version if the FW write fails. Start by writing a copy of the * first page with a bad version.
*/
memcpy(first_page, fw_data, SF_PAGE_SIZE);
((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
ret = csio_hw_write_flash(hw, FLASH_FW_START, SF_PAGE_SIZE, first_page); if (ret) goto out;
ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID); if (!ret)
ret = csio_hw_sf1_read(hw, 3, 0, 1, &flashid);
csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */ if (ret) return ret;
/* Check to see if it's one of our non-standard supported Flash parts.
*/ for (part = 0; part < ARRAY_SIZE(supported_flash); part++) if (supported_flash[part].vendor_and_model_id == flashid) {
hw->params.sf_size = supported_flash[part].size_mb;
hw->params.sf_nsec =
hw->params.sf_size / SF_SEC_SIZE; goto found;
}
/* Decode Flash part size. The code below looks repetitive with * common encodings, but that's not guaranteed in the JEDEC * specification for the Read JEDEC ID command. The only thing that * we're guaranteed by the JEDEC specification is where the * Manufacturer ID is in the returned result. After that each * Manufacturer ~could~ encode things completely differently. * Note, all Flash parts must have 64KB sectors.
*/
manufacturer = flashid & 0xff; switch (manufacturer) { case 0x20: { /* Micron/Numonix */ /* This Density -> Size decoding table is taken from Micron * Data Sheets.
*/
density = (flashid >> 16) & 0xff; switch (density) { case 0x14 ... 0x19: /* 1MB - 32MB */
size = 1 << density; break; case 0x20: /* 64MB */
size = 1 << 26; break; case 0x21: /* 128MB */
size = 1 << 27; break; case 0x22: /* 256MB */
size = 1 << 28;
} break;
} case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */ /* This Density -> Size decoding table is taken from ISSI * Data Sheets.
*/
density = (flashid >> 16) & 0xff; switch (density) { case 0x16: /* 32 MB */
size = 1 << 25; break; case 0x17: /* 64MB */
size = 1 << 26;
} break;
} case 0xc2: /* Macronix */ case 0xef: /* Winbond */ { /* This Density -> Size decoding table is taken from * Macronix and Winbond Data Sheets.
*/
density = (flashid >> 16) & 0xff; switch (density) { case 0x17: /* 8MB */ case 0x18: /* 16MB */
size = 1 << density;
}
}
}
/* If we didn't recognize the FLASH part, that's no real issue: the * Hardware/Software contract says that Hardware will _*ALWAYS*_ * use a FLASH part which is at least 4MB in size and has 64KB * sectors. The unrecognized FLASH part is likely to be much larger * than 4MB, but that's all we really need.
*/ if (size == 0) {
csio_warn(hw, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
flashid);
size = 1 << 22;
}
/* Firmware has designated us to be master */ if (hw->pfn == mpfn) {
hw->flags |= CSIO_HWF_MASTER;
} elseif (*state == CSIO_DEV_STATE_UNINIT) { /* * If we're not the Master PF then we need to wait around for * the Master PF Driver to finish setting up the adapter. * * Note that we also do this wait if we're a non-Master-capable * PF and there is no current Master PF; a Master PF may show up * momentarily and we wouldn't want to fail pointlessly. (This * can happen when an OS loads lots of different drivers rapidly * at the same time). In this case, the Master PF returned by * the firmware will be PCIE_FW_MASTER_MASK so the test below * will work ...
*/
int waiting = FW_CMD_HELLO_TIMEOUT;
/* * Wait for the firmware to either indicate an error or * initialized state. If we see either of these we bail out * and report the issue to the caller. If we exhaust the * "hello timeout" and we haven't exhausted our retries, try * again. Otherwise bail with a timeout error.
*/ for (;;) {
uint32_t pcie_fw;
/* * If neither Error nor Initialized are indicated * by the firmware keep waiting till we exhaust our * timeout ... and then retry if we haven't exhausted * our retries ...
*/
pcie_fw = csio_rd_reg32(hw, PCIE_FW_A); if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) { if (waiting <= 0) { if (retries-- > 0) goto retry;
rv = -ETIMEDOUT; break;
} continue;
}
/* * We either have an Error or Initialized condition * report errors preferentially.
*/ if (state) { if (pcie_fw & PCIE_FW_ERR_F) {
*state = CSIO_DEV_STATE_ERR;
rv = -ETIMEDOUT;
} elseif (pcie_fw & PCIE_FW_INIT_F)
*state = CSIO_DEV_STATE_INIT;
}
/* * If we arrived before a Master PF was selected and * there's not a valid Master PF, grab its identity * for our caller.
*/ if (mpfn == PCIE_FW_MASTER_M &&
(pcie_fw & PCIE_FW_MASTER_VLD_F))
mpfn = PCIE_FW_MASTER_G(pcie_fw); break;
}
hw->flags &= ~CSIO_HWF_MASTER;
}
switch (*state) { case CSIO_DEV_STATE_UNINIT:
strcpy(state_str, "Initializing"); break; case CSIO_DEV_STATE_INIT:
strcpy(state_str, "Initialized"); break; case CSIO_DEV_STATE_ERR:
strcpy(state_str, "Error"); break; default:
strcpy(state_str, "Unknown"); break;
}
if (hw->pfn == mpfn)
csio_info(hw, "PF: %d, Coming up as MASTER, HW state: %s\n",
hw->pfn, state_str); else
csio_info(hw, "PF: %d, Coming up as SLAVE, Master PF: %d, HW state: %s\n",
hw->pfn, mpfn, state_str);
if (!(caps & FW_CAPS_CONFIG_FCOE_INITIATOR)) {
csio_err(hw, "No FCoE Initiator capability in the firmware.\n"); return -EINVAL;
}
if (!(caps & FW_CAPS_CONFIG_FCOE_CTRL_OFLD)) {
csio_err(hw, "No FCoE Control Offload capability\n"); return -EINVAL;
}
return 0;
}
/* * csio_hw_fw_halt - issue a reset/halt to FW and put uP into RESET * @hw: the HW module * @mbox: mailbox to use for the FW RESET command (if desired) * @force: force uP into RESET even if FW RESET command fails * * Issues a RESET command to firmware (if desired) with a HALT indication * and then puts the microprocessor into RESET state. The RESET command * will only be issued if a legitimate mailbox is provided (mbox <= * PCIE_FW_MASTER_MASK). * * This is generally used in order for the host to safely manipulate the * adapter without fear of conflicting with whatever the firmware might * be doing. The only way out of this state is to RESTART the firmware * ...
*/ staticint
csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
{ enum fw_retval retval = 0;
/* * If a legitimate mailbox is provided, issue a RESET command * with a HALT indication.
*/ if (mbox <= PCIE_FW_MASTER_M) { struct csio_mb *mbp;
/* * Normally we won't complete the operation if the firmware RESET * command fails but if our caller insists we'll go ahead and put the * uP into RESET. This can be useful if the firmware is hung or even * missing ... We'll have to take the risk of putting the uP into * RESET without the cooperation of firmware in that case. * * We also force the firmware's HALT flag to be on in case we bypassed * the firmware RESET command above or we're dealing with old firmware * which doesn't have the HALT capability. This will serve as a flag * for the incoming firmware to know that it's coming out of a HALT * rather than a RESET ... if it's new enough to understand that ...
*/ if (retval == 0 || force) {
csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F,
PCIE_FW_HALT_F);
}
/* * And we always return the result of the firmware RESET command * even when we force the uP into RESET ...
*/ return retval ? -EINVAL : 0;
}
/* * csio_hw_fw_restart - restart the firmware by taking the uP out of RESET * @hw: the HW module * @reset: if we want to do a RESET to restart things * * Restart firmware previously halted by csio_hw_fw_halt(). On successful * return the previous PF Master remains as the new PF Master and there * is no need to issue a new HELLO command, etc. * * We do this in two ways: * * 1. If we're dealing with newer firmware we'll simply want to take * the chip's microprocessor out of RESET. This will cause the * firmware to start up from its start vector. And then we'll loop * until the firmware indicates it's started again (PCIE_FW.HALT * reset to 0) or we timeout. * * 2. If we're dealing with older firmware then we'll need to RESET * the chip since older firmware won't recognize the PCIE_FW.HALT * flag and automatically RESET itself on startup.
*/ staticint
csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
{ if (reset) { /* * Since we're directing the RESET instead of the firmware * doing it automatically, we need to clear the PCIE_FW.HALT * bit.
*/
csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0);
/* * If we've been given a valid mailbox, first try to get the * firmware to do the RESET. If that works, great and we can * return success. Otherwise, if we haven't been given a * valid mailbox or the RESET command failed, fall back to * hitting the chip with a hammer.
*/ if (mbox <= PCIE_FW_MASTER_M) {
csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
msleep(100); if (csio_do_reset(hw, true) == 0) return 0;
}
csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0); for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F)) return 0;
msleep(100);
ms += 100;
} return -ETIMEDOUT;
} return 0;
}
/* * csio_hw_fw_upgrade - perform all of the steps necessary to upgrade FW * @hw: the HW module * @mbox: mailbox to use for the FW RESET command (if desired) * @fw_data: the firmware image to write * @size: image size * @force: force upgrade even if firmware doesn't cooperate * * Perform all of the steps necessary for upgrading an adapter's * firmware image. Normally this requires the cooperation of the * existing firmware in order to halt all existing activities * but if an invalid mailbox token is passed in we skip that step * (though we'll still put the adapter microprocessor into RESET in * that case). * * On successful return the new firmware will have been loaded and * the adapter will have been fully RESET losing all previous setup * state. On unsuccessful return the adapter may be completely hosed ... * positive errno indicates that the adapter is ~probably~ intact, a * negative errno indicates that things are looking bad ...
*/ staticint
csio_hw_fw_upgrade(struct csio_hw *hw, uint32_t mbox, const u8 *fw_data, uint32_t size, int32_t force)
{ conststruct fw_hdr *fw_hdr = (conststruct fw_hdr *)fw_data; int reset, ret;
ret = csio_hw_fw_halt(hw, mbox, force); if (ret != 0 && !force) return ret;
ret = csio_hw_fw_dload(hw, (uint8_t *) fw_data, size); if (ret != 0) return ret;
/* * Older versions of the firmware don't understand the new * PCIE_FW.HALT flag and so won't know to perform a RESET when they * restart. So for newly loaded older firmware we'll have to do the * RESET for it so it starts up on a clean slate. We can tell if * the newly loaded firmware will handle this right by checking * its header flags to see if it advertises the capability.
*/
reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); return csio_hw_fw_restart(hw, mbox, reset);
}
if (cc_fec & FEC_RS)
fw_fec |= FW_PORT_CAP32_FEC_RS; if (cc_fec & FEC_BASER_RS)
fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
return fw_fec;
}
/** * fwcap_to_fwspeed - return highest speed in Port Capabilities * @acaps: advertised Port Capabilities * * Get the highest speed for the port from the advertised Port * Capabilities.
*/
fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
{ #define TEST_SPEED_RETURN(__caps_speed) \ do { \ if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \ return FW_PORT_CAP32_SPEED_##__caps_speed; \
} while (0)
/** * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits * @caps16: a 16-bit Port Capabilities value * * Returns the equivalent 32-bit Port Capabilities value.
*/
fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
{
fw_port_cap32_t caps32 = 0;
#define CAP16_TO_CAP32(__cap) \ do { \ if (caps16 & FW_PORT_CAP_##__cap) \
caps32 |= FW_PORT_CAP32_##__cap; \
} while (0)
/** * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits * @caps32: a 32-bit Port Capabilities value * * Returns the equivalent 16-bit Port Capabilities value. Note that * not all 32-bit Port Capabilities can be represented in the 16-bit * Port Capabilities and some fields/values may not make it.
*/
fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
{
fw_port_cap16_t caps16 = 0;
#define CAP32_TO_CAP16(__cap) \ do { \ if (caps32 & FW_PORT_CAP32_##__cap) \
caps16 |= FW_PORT_CAP_##__cap; \
} while (0)
/** * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value * * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new * 32-bit Port Capabilities value.
*/
fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
{
fw_port_cap32_t linkattr = 0;
/* The format of the Link Status in the old * 16-bit Port Information message isn't the same as the * 16-bit Port Capabilities bitfield used everywhere else.
*/ if (lstatus & FW_PORT_CMD_RXPAUSE_F)
linkattr |= FW_PORT_CAP32_FC_RX; if (lstatus & FW_PORT_CMD_TXPAUSE_F)
linkattr |= FW_PORT_CAP32_FC_TX; if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
linkattr |= FW_PORT_CAP32_SPEED_100M; if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
linkattr |= FW_PORT_CAP32_SPEED_1G; if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
linkattr |= FW_PORT_CAP32_SPEED_10G; if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
linkattr |= FW_PORT_CAP32_SPEED_25G; if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
linkattr |= FW_PORT_CAP32_SPEED_40G; if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
linkattr |= FW_PORT_CAP32_SPEED_100G;
return linkattr;
}
/** * csio_init_link_config - initialize a link's SW state * @lc: pointer to structure holding the link state * @pcaps: link Port Capabilities * @acaps: link current Advertised Port Capabilities * * Initializes the SW state maintained for each link, including the link's * capabilities and default speed/flow-control/autonegotiation settings.
*/ staticvoid csio_init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
fw_port_cap32_t acaps)
{
lc->pcaps = pcaps;
lc->def_acaps = acaps;
lc->lpacaps = 0;
lc->speed_caps = 0;
lc->speed = 0;
lc->requested_fc = PAUSE_RX | PAUSE_TX;
lc->fc = lc->requested_fc;
/* * For Forward Error Control, we default to whatever the Firmware * tells us the Link is currently advertising.
*/
lc->requested_fec = FEC_AUTO;
lc->fec = fwcap_to_cc_fec(lc->def_acaps);
/* If the Port is capable of Auto-Negtotiation, initialize it as * "enabled" and copy over all of the Physical Port Capabilities * to the Advertised Port Capabilities. Otherwise mark it as * Auto-Negotiate disabled and select the highest supported speed * for the link. Note parallel structure in t4_link_l1cfg_core() * and t4_handle_get_port_info().
*/ if (lc->pcaps & FW_PORT_CAP32_ANEG) {
lc->acaps = lc->pcaps & ADVERT_MASK;
lc->autoneg = AUTONEG_ENABLE;
lc->requested_fc |= PAUSE_AUTONEG;
} else {
lc->acaps = 0;
lc->autoneg = AUTONEG_DISABLE;
}
}
/* * Convert driver coding of Pause Frame Flow Control settings into the * Firmware's API.
*/
fw_fc = cc_to_fwcap_pause(lc->requested_fc);
/* * Convert Common Code Forward Error Control settings into the * Firmware's API. If the current Requested FEC has "Automatic" * (IEEE 802.3) specified, then we use whatever the Firmware * sent us as part of it's IEEE 802.3-based interpretation of * the Transceiver Module EPROM FEC parameters. Otherwise we * use whatever is in the current Requested FEC settings.
*/ if (lc->requested_fec & FEC_AUTO)
cc_fec = fwcap_to_cc_fec(lc->def_acaps); else
cc_fec = lc->requested_fec;
fw_fec = cc_to_fwcap_fec(cc_fec);
/* Figure out what our Requested Port Capabilities are going to be. * Note parallel structure in t4_handle_get_port_info() and * init_link_config().
*/ if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
lrcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
lc->fec = cc_fec;
} elseif (lc->autoneg == AUTONEG_DISABLE) {
lrcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
lc->fec = cc_fec;
} else {
lrcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
}
*rcaps = lrcap;
}
/* * csio_enable_ports - Bring up all available ports. * @hw: HW module. *
*/ staticint
csio_enable_ports(struct csio_hw *hw)
{ struct csio_mb *mbp;
u16 fw_caps = FW_CAPS_UNKNOWN; enum fw_retval retval;
uint8_t portid;
fw_port_cap32_t pcaps, acaps, rcaps; int i;
/* * Find out whether we're dealing with a version of * the firmware which has configuration file support.
*/
_param[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
/* * HW initialization: contact FW, obtain config, perform basic init. * * If the firmware we're dealing with has Configuration File support, then * we use that to perform all configuration -- either using the configuration * file stored in flash on the adapter or using a filesystem-local file * if available. * * If we don't have configuration file support in the firmware, then we'll * have to set things up the old fashioned way with hard-coded register * writes and firmware commands ...
*/
/* * Attempt to initialize the HW via a Firmware Configuration File.
*/ staticint
csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param)
{ struct csio_mb *mbp = NULL; struct fw_caps_config_cmd *caps_cmd; unsignedint mtype, maddr; int rv = -EINVAL;
uint32_t finiver = 0, finicsum = 0, cfcsum = 0; char path[64]; char *config_name = NULL;
/* * Reset device if necessary
*/ if (reset) {
rv = csio_do_reset(hw, true); if (rv != 0) goto bye;
}
/* * If we have a configuration file in host , * then use that. Otherwise, use the configuration file stored * in the HW flash ...
*/
spin_unlock_irq(&hw->lock);
rv = csio_hw_flash_config(hw, fw_cfg_param, path);
spin_lock_irq(&hw->lock); if (rv != 0) { /* * config file was not found. Use default * config file from flash.
*/
config_name = "On FLASH";
mtype = FW_MEMTYPE_CF_FLASH;
maddr = hw->chip_ops->chip_flash_cfg_addr(hw);
} else {
config_name = path;
mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param);
maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16;
}
mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); if (!mbp) {
CSIO_INC_STATS(hw, n_err_nomem); return -ENOMEM;
} /* * Tell the firmware to process the indicated Configuration File. * If there are no errors and the caller has provided return value * pointers for the [fini] section version, checksum and computed * checksum, pass those back to the caller.
*/
caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb);
CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
caps_cmd->op_to_write =
htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_READ_F);
caps_cmd->cfvalid_to_len16 =
htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
FW_LEN16(*caps_cmd));
if (csio_mb_issue(hw, mbp)) {
rv = -EINVAL; goto bye;
}
rv = csio_mb_fw_retval(mbp); /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware * Configuration File in FLASH), our last gasp effort is to use the * Firmware Configuration File which is embedded in the * firmware. A very few early versions of the firmware didn't * have one embedded but we can ignore those.
*/ if (rv == ENOENT) {
CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
caps_cmd->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_READ_F);
caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
if (csio_mb_issue(hw, mbp)) {
rv = -EINVAL; goto bye;
}
/* * And now tell the firmware to use the configuration we just loaded.
*/
caps_cmd->op_to_write =
htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
FW_CMD_REQUEST_F |
FW_CMD_WRITE_F);
caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
if (csio_mb_issue(hw, mbp)) {
rv = -EINVAL; goto bye;
}
rv = csio_mb_fw_retval(mbp); if (rv != FW_SUCCESS) {
csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv); goto bye;
}
/* * Note that we're operating with parameters * not supplied by the driver, rather than from hard-wired * initialization constants buried in the driver.
*/
hw->flags |= CSIO_HWF_USING_SOFT_PARAMS;
/* * And finally tell the firmware to initialize itself using the * parameters from the Configuration File.
*/ /* Post event to notify completion of configuration */
csio_post_event(&hw->sm, CSIO_HWE_INIT);
csio_info(hw, "Successfully configure using Firmware " "Configuration File %s, version %#x, computed checksum %#x\n",
config_name, finiver, cfcsum); return 0;
/* * Something bad happened. Return the error ...
*/
bye: if (mbp)
mempool_free(mbp, hw->mb_mempool);
hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS;
csio_warn(hw, "Configuration file error %d\n", rv); return rv;
}
/* Is the given firmware API compatible with the one the driver was compiled * with?
*/ staticint fw_compatible(conststruct fw_hdr *hdr1, conststruct fw_hdr *hdr2)
{
/* short circuit if it's the exact same firmware version */ if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver) return 1;
/* The firmware in the filesystem is usable, but should it be installed? * This routine explains itself in detail if it indicates the filesystem * firmware should be installed.
*/ staticint csio_should_install_fs_fw(struct csio_hw *hw, int card_fw_usable, int k, int c)
{ constchar *reason;
if (!card_fw_usable) {
reason = "incompatible or unusable"; goto install;
}
if (k > c) {
reason = "older than the version supported with this driver"; goto install;
}
return 0;
install:
csio_err(hw, "firmware on card (%u.%u.%u.%u) is %s, " "installing firmware %u.%u.%u.%u on card.\n",
FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
(!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) { /* Common case: the firmware on the card is an exact match and * the filesystem one is an exact match too, or the filesystem * one is absent/incompatible.
*/
} elseif (fs_fw_usable && state == CSIO_DEV_STATE_UNINIT &&
csio_should_install_fs_fw(hw, card_fw_usable,
be32_to_cpu(fs_fw->fw_ver),
be32_to_cpu(card_fw->fw_ver))) {
ret = csio_hw_fw_upgrade(hw, hw->pfn, fw_data,
fw_size, 0); if (ret != 0) {
csio_err(hw, "failed to install firmware: %d\n", ret); goto bye;
}
/* Installed successfully, update the cached header too. */
memcpy(card_fw, fs_fw, sizeof(*card_fw));
card_fw_usable = 1;
*reset = 0; /* already reset as part of load_fw */
}
if (!card_fw_usable) {
uint32_t d, c, k;
d = be32_to_cpu(drv_fw->fw_ver);
c = be32_to_cpu(card_fw->fw_ver);
k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
csio_err(hw, "Cannot find a usable firmware: " "chip state %d, " "driver compiled with %d.%d.%d.%d, " "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
state,
FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
ret = -EINVAL; goto bye;
}
/* We're using whatever's on the card and it's known to be good. */
hw->fwrev = be32_to_cpu(card_fw->fw_ver);
hw->tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
bye: return ret;
}
/* * Returns -EINVAL if attempts to flash the firmware failed, * -ENOMEM if memory allocation failed else returns 0, * if flashing was not attempted because the card had the * latest firmware ECANCELED is returned
*/ staticint
csio_hw_flash_fw(struct csio_hw *hw, int *reset)
{ int ret = -ECANCELED; conststruct firmware *fw; struct fw_info *fw_info; struct fw_hdr *card_fw; struct pci_dev *pci_dev = hw->pdev; struct device *dev = &pci_dev->dev ; const u8 *fw_data = NULL; unsignedint fw_size = 0; constchar *fw_bin_file;
/* This is the firmware whose headers the driver was compiled * against
*/
fw_info = find_fw_info(CHELSIO_CHIP_VERSION(hw->chip_id)); if (fw_info == NULL) {
csio_err(hw, "unable to get firmware info for chip %d.\n",
CHELSIO_CHIP_VERSION(hw->chip_id)); return -EINVAL;
}
/* allocate memory to read the header of the firmware on the * card
*/
card_fw = kmalloc(sizeof(*card_fw), GFP_KERNEL); if (!card_fw) return -ENOMEM;
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