/******************************************************************* * This file is part of the Emulex Linux Device Driver for * * Fibre Channel Host Bus Adapters. * * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term * * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * * Copyright (C) 2004-2016 Emulex. All rights reserved. * * EMULEX and SLI are trademarks of Emulex. * * www.broadcom.com * * Portions Copyright (C) 2004-2005 Christoph Hellwig * * * * This program is free software; you can redistribute it and/or * * modify it under the terms of version 2 of the GNU General * * Public License as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful. * * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * * TO BE LEGALLY INVALID. See the GNU General Public License for * * more details, a copy of which can be found in the file COPYING * * included with this package. *
********************************************************************/
struct lpfc_nvme_qhandle {
uint32_t index; /* WQ index to use */
uint32_t qidx; /* queue index passed to create */
uint32_t cpu_id; /* current cpu id at time of create */
};
/* * set NVME LS request timeouts to 30s. It is larger than the 2*R_A_TOV * set by the spec, which appears to have issues with some devices.
*/ #define LPFC_NVME_LS_TIMEOUT 30
struct lpfc_nvmet_ctx_info { struct list_head nvmet_ctx_list;
spinlock_t nvmet_ctx_list_lock; /* lock per CPU */ struct lpfc_nvmet_ctx_info *nvmet_ctx_next_cpu; struct lpfc_nvmet_ctx_info *nvmet_ctx_start_cpu;
uint16_t nvmet_ctx_list_cnt; char pad[16]; /* pad to a cache-line */
};
/* This retrieves the context info associated with the specified cpu / mrq */ #define lpfc_get_ctx_list(phba, cpu, mrq) \
(phba->sli4_hba.nvmet_ctx_info + ((cpu * phba->cfg_nvmet_mrq) + mrq))
/* Values for state field of struct lpfc_async_xchg_ctx */ #define LPFC_NVME_STE_LS_RCV 1 #define LPFC_NVME_STE_LS_ABORT 2 #define LPFC_NVME_STE_LS_RSP 3 #define LPFC_NVME_STE_RCV 4 #define LPFC_NVME_STE_DATA 5 #define LPFC_NVME_STE_ABORT 6 #define LPFC_NVME_STE_DONE 7 #define LPFC_NVME_STE_FREE 0xff
/* Values for flag field of struct lpfc_async_xchg_ctx */ #define LPFC_NVME_IO_INP 0x1 /* IO is in progress on exchange */ #define LPFC_NVME_ABORT_OP 0x2 /* Abort WQE issued on exchange */ #define LPFC_NVME_XBUSY 0x4 /* XB bit set on IO cmpl */ #define LPFC_NVME_CTX_RLS 0x8 /* ctx free requested */ #define LPFC_NVME_ABTS_RCV 0x10 /* ABTS received on exchange */ #define LPFC_NVME_CTX_REUSE_WQ 0x20 /* ctx reused via WQ */ #define LPFC_NVME_DEFER_WQFULL 0x40 /* Waiting on a free WQE */ #define LPFC_NVME_TNOTIFY 0x80 /* notify transport of abts */
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:
Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.