// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2015 Atmel * * Alexandre Belloni <alexandre.belloni@free-electrons.com * Boris Brezillon <boris.brezillon@free-electrons.com #define pr_fmt(fmt) "AT91: " fmt#include <linux/io.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/of_platform.h>#include <linux/slab.h>#include <linux/sys_soc.h>#include "soc.h" #define AT91_DBGU_CIDR 0x40#define AT91_DBGU_EXID 0x44#define AT91_CHIPID_CIDR 0x00#define AT91_CHIPID_EXID 0x04#define AT91_CIDR_VERSION(x, m) ((x) & (m))#define AT91_CIDR_VERSION_MASK GENMASK(4, 0)#define AT91_CIDR_VERSION_MASK_SAMA7G5 GENMASK(3, 0)#define AT91_CIDR_EXT BIT(31)#define AT91_CIDR_MATCH_MASK GENMASK(30, 5)#define AT91_CIDR_MASK_SAMA7G5 GENMASK(27, 5)static const struct at91_soc socs[] __initconst = {#ifdef CONFIG_SOC_AT91RM9200"at91rm9200 BGA" , "at91rm9200" ),#endif #ifdef CONFIG_SOC_AT91SAM9"at91sam9260" , NULL),"at91sam9261" , NULL),"at91sam9263" , NULL),"at91sam9g20" , NULL),"at91sam9rl64" , NULL),"at91sam9m11" , "at91sam9g45" ),"at91sam9m10" , "at91sam9g45" ),"at91sam9g46" , "at91sam9g45" ),"at91sam9g45" , "at91sam9g45" ),"at91sam9g15" , "at91sam9x5" ),"at91sam9g35" , "at91sam9x5" ),"at91sam9x35" , "at91sam9x5" ),"at91sam9g25" , "at91sam9x5" ),"at91sam9x25" , "at91sam9x5" ),"at91sam9cn12" , "at91sam9n12" ),"at91sam9n12" , "at91sam9n12" ),"at91sam9cn11" , "at91sam9n12" ),"at91sam9xe128" , "at91sam9xe128" ),"at91sam9xe256" , "at91sam9xe256" ),"at91sam9xe512" , "at91sam9xe512" ),#endif #ifdef CONFIG_SOC_SAM9X60"sam9x60" , "sam9x60" ),"sam9x60 64MiB DDR2 SiP" , "sam9x60" ),"sam9x60 128MiB DDR2 SiP" , "sam9x60" ),"sam9x60 8MiB SDRAM SiP" , "sam9x60" ),#endif #ifdef CONFIG_SOC_SAM9X7"sam9x70" , "sam9x7" ),"sam9x72" , "sam9x7" ),"sam9x75" , "sam9x7" ),"sam9x75 16MB DDR2 SiP" , "sam9x7" ),"sam9x75 64MB DDR2 SiP" , "sam9x7" ),"sam9x75 125MB DDR3L SiP " , "sam9x7" ),"sam9x75 250MB DDR3L SiP" , "sam9x7" ),#endif #ifdef CONFIG_SOC_SAMA5"sama5d21" , "sama5d2" ),"sama5d22" , "sama5d2" ),"sama5d225c 16MiB SiP" , "sama5d2" ),"sama5d23" , "sama5d2" ),"sama5d24" , "sama5d2" ),"sama5d24" , "sama5d2" ),"sama5d26" , "sama5d2" ),"sama5d27" , "sama5d2" ),"sama5d27" , "sama5d2" ),"sama5d27c 128MiB SiP" , "sama5d2" ),"sama5d27c 64MiB SiP" , "sama5d2" ),"sama5d27c 128MiB LPDDR2 SiP" , "sama5d2" ),"sama5d27c 256MiB LPDDR2 SiP" , "sama5d2" ),"sama5d28" , "sama5d2" ),"sama5d28" , "sama5d2" ),"sama5d28c 128MiB SiP" , "sama5d2" ),"sama5d28c 128MiB LPDDR2 SiP" , "sama5d2" ),"sama5d28c 256MiB LPDDR2 SiP" , "sama5d2" ),"sama5d29" , "sama5d2" ),"sama5d31" , "sama5d3" ),"sama5d33" , "sama5d3" ),"sama5d34" , "sama5d3" ),"sama5d35" , "sama5d3" ),"sama5d36" , "sama5d3" ),"sama5d41" , "sama5d4" ),"sama5d42" , "sama5d4" ),"sama5d43" , "sama5d4" ),"sama5d44" , "sama5d4" ),#endif #ifdef CONFIG_SOC_SAMV7"same70q21" , "same7" ),"same70q20" , "same7" ),"same70q19" , "same7" ),"sams70q21" , "sams7" ),"sams70q20" , "sams7" ),"sams70q19" , "sams7" ),"samv71q21" , "samv7" ),"samv71q20" , "samv7" ),"samv71q19" , "samv7" ),"samv70q20" , "samv7" ),"samv70q19" , "samv7" ),#endif #ifdef CONFIG_SOC_SAMA7"sama7d65" , "sama7d6" ),"sama7g51" , "sama7g5" ),"sama7g52" , "sama7g5" ),"sama7g53" , "sama7g5" ),"sama7g54" , "sama7g5" ),"SAMA7G54 1Gb DDR3L SiP" , "sama7g5" ),"SAMA7G54 2Gb DDR3L SiP" , "sama7g5" ),"SAMA7G54 4Gb DDR3L SiP" , "sama7g5" ),#endif /* sentinel */ }, static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)struct device_node *np;void __iomem *regs;"atmel,at91rm9200-dbgu" );if (!np)"atmel,at91sam9260-dbgu" );if (!np)return -ENODEV;if (!regs) {"Could not map DBGU iomem range" );return -ENXIO;return 0;static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)struct device_node *np;void __iomem *regs;static const struct of_device_id chipids[] = {"atmel,sama5d2-chipid" },"microchip,sama7d65-chipid" },"microchip,sama7g5-chipid" },if (!np)return -ENODEV;if (!regs) {"Could not map DBGU iomem range" );return -ENXIO;return 0;struct soc_device * __init at91_soc_init(const struct at91_soc *socs)struct soc_device_attribute *soc_dev_attr;const struct at91_soc *soc;struct soc_device *soc_dev;int ret;/* * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more * in the dbgu device but in the chipid device whose purpose is only * to expose these two registers. if (ret)if (ret) {if (ret == -ENODEV)"Could not find identification node" );return NULL;for (soc = socs; soc->name; soc++) {if (soc->cidr_match != (cidr & soc->cidr_mask))continue ;if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)break ;if (!soc->name) {"Could not find matching SoC description\n" );return NULL;sizeof (*soc_dev_attr), GFP_KERNEL);if (!soc_dev_attr)return NULL;"%X" ,if (IS_ERR(soc_dev)) {"Could not register SoC device\n" );return NULL;if (soc->family)"Detected SoC family: %s\n" , soc->family);"Detected SoC: %s, revision %X\n" , soc->name,return soc_dev;static const struct of_device_id at91_soc_allowed_list[] __initconst = {"atmel,at91rm9200" , },"atmel,at91sam9" , },"atmel,sama5" , },"atmel,samv7" , },"microchip,sama7d65" , },"microchip,sama7g5" , },static int __init atmel_soc_device_init(void )struct device_node *np __free(device_node) = of_find_node_by_path("/" );if (!of_match_node(at91_soc_allowed_list, np))return 0;return 0;
Messung V0.5 C=97 H=96 G=96
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