// SPDX-License-Identifier: GPL-2.0 /* * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) * * Copyright (C) 2002 - 2011 Paul Mundt * Copyright (C) 2015 Glider bvba * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). * * based off of the old drivers/char/sh-sci.c by: * * Copyright (C) 1999, 2000 Niibe Yutaka * Copyright (C) 2000 Sugioka Toshinobu * Modified to support multiple serial ports. Stuart Menefy (May 2000). * Modified to support SecureEdge. David McCullough (2002) * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). * Removed SH7300 support (Jul 2007).
*/ #undef DEBUG
/* Iterate over all supported sampling rates, from high to low */ #define for_each_sr(_sr, _port) \ for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
/* * The "offset" here is rather misleading, in that it refers to an enum * value relative to the port mapping rather than the fixed offset * itself, which needs to be manually retrieved from the platform's * register map for the given port.
*/ staticunsignedint sci_serial_in(struct uart_port *p, int offset)
{ conststruct plat_sci_reg *reg = sci_getreg(p, offset);
staticinlineunsignedlong port_rx_irq_mask(struct uart_port *port)
{ /* * Not all ports (such as SCIFA) will support REIE. Rather than * special-casing the port type, we check the port initialization * IRQ enable mask to see whether the IRQ is desired at all. If * it's unset, it's logically inferred that there's no point in * testing for it.
*/ return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
}
#ifdef CONFIG_SERIAL_SH_SCI_DMA if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
u16 new, scr = sci_serial_in(port, SCSCR); if (s->chan_tx) new = scr | SCSCR_TDRQE; else new = scr & ~SCSCR_TDRQE; if (new != scr)
sci_serial_out(port, SCSCR, new);
}
if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
dma_submit_error(s->cookie_tx)) { if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) /* Switch irq from SCIF to DMA */
disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE ||
s->type == PORT_SCIFA || s->type == PORT_SCIFB) { /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
ctrl = sci_serial_in(port, SCSCR);
/* * For SCI, TE (transmit enable) must be set after setting TIE * (transmit interrupt enable) or in the same instruction to start * the transmit process.
*/ if (s->type == PORT_SCI)
ctrl |= SCSCR_TE;
if (s->type == PORT_SCI) { /* Just store the mask */
sci_serial_out(port, SCxSR, mask);
} elseif (s->params->overrun_mask == SCIFA_ORER) { /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ /* Only clear the status bits we want to clear */
sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
} else { /* Store the mask, clear parity/framing errors */
sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
}
}
do {
status = sci_serial_in(port, SCxSR); if (status & SCxSR_ERRORS(port)) {
s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); continue;
} break;
} while (1);
if (!(status & SCxSR_RDxF(port))) return NO_POLL_CHAR;
/* * Use port-specific handler if provided.
*/ if (s->cfg->ops && s->cfg->ops->init_pins) {
s->cfg->ops->init_pins(port, cflag); return;
}
if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {
u16 data = sci_serial_in(port, SCPDR);
u16 ctrl = sci_serial_in(port, SCPCR);
/* Enable RXD and TXD pin functions */
ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); if (s->has_rtscts) { /* RTS# is output, active low, unless autorts */ if (!(port->mctrl & TIOCM_RTS)) {
ctrl |= SCPCR_RTSC;
data |= SCPDR_RTSD;
} elseif (!s->autorts) {
ctrl |= SCPCR_RTSC;
data &= ~SCPDR_RTSD;
} else { /* Enable RTS# pin function */
ctrl &= ~SCPCR_RTSC;
} /* Enable CTS# pin function */
ctrl &= ~SCPCR_CTSC;
}
sci_serial_out(port, SCPDR, data);
sci_serial_out(port, SCPCR, ctrl);
} elseif (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
u16 status = sci_serial_in(port, SCSPTR);
/* RTS# is always output; and active low, unless autorts */
status |= SCSPTR_RTSIO; if (!(port->mctrl & TIOCM_RTS))
status |= SCSPTR_RTSDT; elseif (!s->autorts)
status &= ~SCSPTR_RTSDT; /* CTS# and SCK are inputs */
status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
sci_serial_out(port, SCSPTR, status);
}
}
status = sci_serial_in(port, SCxSR); if (!(status & SCxSR_RDxF(port))) return;
while (1) { /* Don't copy more bytes than there is room for in the buffer */
count = tty_buffer_request_room(tport, sci_rxfill(port));
/* If for any reason we can't copy more data, we're done! */ if (count == 0) break;
if (s->type == PORT_SCI) { char c = sci_serial_in(port, SCxRDR); if (uart_handle_sysrq_char(port, c))
count = 0; else
tty_insert_flip_char(tport, c, TTY_NORMAL);
} else { for (i = 0; i < count; i++) { char c;
if (s->type == PORT_SCIF ||
s->type == PORT_HSCIF) {
status = sci_serial_in(port, SCxSR);
c = sci_serial_in(port, SCxRDR);
} else {
c = sci_serial_in(port, SCxRDR);
status = sci_serial_in(port, SCxSR);
} if (uart_handle_sysrq_char(port, c)) {
count--; i--; continue;
}
/* Store data and status */ if (status & SCxSR_FER(port)) {
flag = TTY_FRAME;
port->icount.frame++;
} elseif (status & SCxSR_PER(port)) {
flag = TTY_PARITY;
port->icount.parity++;
} else
flag = TTY_NORMAL;
if (copied) { /* Tell the rest of the system the news. New characters! */
tty_flip_buffer_push(tport);
} else { /* TTY buffers full; read from RX reg to prevent lockup */
sci_serial_in(port, SCxRDR);
sci_serial_in(port, SCxSR); /* dummy read */
s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
}
}
if (s->type != SCI_PORT_RSCI) {
reg = sci_getreg(port, s->params->overrun_reg); if (!reg->size) return 0;
}
status = s->ops->read_reg(port, s->params->overrun_reg); if (status & s->params->overrun_mask) {
status &= ~s->params->overrun_mask;
s->ops->write_reg(port, s->params->overrun_reg, status);
/* Direct new serial port interrupts back to CPU */
scr = sci_serial_in(port, SCSCR); if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||
s->regtype == SCIx_RZ_SCIFA_REGTYPE) {
enable_irq(s->irqs[SCIx_RXI_IRQ]); if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)
s->ops->set_rtrg(port, s->rx_trigger); else
scr &= ~SCSCR_RDRQE;
}
sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
}
fail: /* Switch to PIO */ if (!port_lock_held)
uart_port_lock_irqsave(port, &flags); if (i)
dmaengine_terminate_async(chan);
sci_dma_rx_chan_invalidate(s);
sci_start_rx(port); if (!port_lock_held)
uart_port_unlock_irqrestore(port, flags); return -EAGAIN;
}
/* * DMA is idle now. * Port xmit buffer is already mapped, and it is one page... Just adjust * offsets and lengths. Since it is a circular buffer, we have to * transmit till the end, and then the rest. Take the port lock to get a * consistent xmit buffer state.
*/
uart_port_lock_irq(port);
s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
UART_XMIT_SIZE);
buf = s->tx_dma_addr + tail; if (!s->tx_dma_len) { /* Transmit buffer has been flushed */
uart_port_unlock_irq(port); return;
}
active = sci_dma_rx_find_active(s); if (active < 0) {
uart_port_unlock_irqrestore(port, flags); return HRTIMER_NORESTART;
}
status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); if (status == DMA_COMPLETE) {
uart_port_unlock_irqrestore(port, flags);
dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
s->active_rx, active);
/* Let packet complete handler take care of the packet */ return HRTIMER_NORESTART;
}
dmaengine_pause(chan);
/* * sometimes DMA transfer doesn't stop even if it is stopped and * data keeps on coming until transaction is complete so check * for DMA_COMPLETE again * Let packet complete handler take care of the packet
*/
status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); if (status == DMA_COMPLETE) {
uart_port_unlock_irqrestore(port, flags);
dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); return HRTIMER_NORESTART;
}
dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
/* * DMA on console may interfere with Kernel log messages which use * plain putchar(). So, simply don't use it with a console.
*/ if (uart_console(port)) return;
if (!port->dev->of_node) return;
s->cookie_tx = -EINVAL;
/* * Don't request a dma channel if no channel was specified * in the device tree.
*/ if (!of_property_present(port->dev->of_node, "dmas")) return;
/* * In uart_flush_buffer(), the xmit circular buffer has just been * cleared, so we have to reset tx_dma_len accordingly, and stop any * pending transfers
*/
s->tx_dma_len = 0; if (s->chan_tx) {
dmaengine_terminate_async(s->chan_tx);
s->cookie_tx = -EINVAL;
}
}
/* I think sci_receive_chars has to be called irrespective * of whether the I_IXOFF is set, otherwise, how is the interrupt * to be disabled?
*/
s->ops->receive_chars(port);
/* * Modem control is a bit of a mixed bag for SCI(F) ports. Generally * CTS/RTS is supported in hardware by at least one port and controlled * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently * handled via the ->init_pins() op, which is a bit of a one-way street, * lacking any ability to defer pin control -- this will later be * converted over to the GPIO framework). * * Other modes (such as loopback) are supported generically on certain * port types, but not others. For these it's sufficient to test for the * existence of the support register and simply ignore the port type.
*/ staticvoid sci_set_mctrl(struct uart_port *port, unsignedint mctrl)
{ struct sci_port *s = to_sci_port(port);
if (mctrl & TIOCM_LOOP) { conststruct plat_sci_reg *reg;
/* * Standard loopback mode for SCFCR ports.
*/
reg = sci_getreg(port, SCFCR); if (reg->size)
sci_serial_out(port, SCFCR,
sci_serial_in(port, SCFCR) | SCFCR_LOOP);
}
mctrl_gpio_set(s->gpios, mctrl);
if (!s->has_rtscts) return;
if (!(mctrl & TIOCM_RTS)) { /* Disable Auto RTS */ if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)
sci_serial_out(port, SCFCR,
sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
/* check whether the port has SCSPTR */ if (!sci_getreg(port, SCSPTR)->size) { /* * Not supported by hardware. Most parts couple break and rx * interrupts together, with break detection always enabled.
*/ return;
}
/* * Find the combination of sample rate and clock select with the * smallest deviation from the desired baud rate. * Prefer high sample rates to maximise the receive margin. * * M: Receive margin (%) * N: Ratio of bit rate to clock (N = sampling rate) * D: Clock duty (D = 0 to 1.0) * L: Frame length (L = 9 to 12) * F: Absolute value of clock frequency deviation * * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - * (|D - 0.5| / N * (1 + F))| * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
*/
for_each_sr(sr, s) { for (c = 0; c <= 3; c++) { /* integerized formulas from HSCIF documentation */
prediv = sr << (2 * c + 1);
/* * We need to calculate: * * br = freq / (prediv * bps) clamped to [1..256] * err = freq / (br * prediv) - bps * * Watch out for overflow when calculating the desired * sampling clock rate!
*/ if (bps > UINT_MAX / prediv) break;
/* * earlyprintk comes here early on with port->uartclk set to zero. * the clock framework is not up and running at this point so here * we assume that 115200 is the maximum baud rate. please note that * the baud rate is not programmed during earlyprintk - it is assumed * that the previous boot loader has enabled required clocks and * setup the baud rate generator hardware for us already.
*/ if (!port->uartclk) {
baud = uart_get_baud_rate(port, termios, old, 0, 115200); goto done;
}
for (i = 0; i < SCI_NUM_CLKS; i++)
max_freq = max(max_freq, s->clk_rates[i]);
done: if (best_clk >= 0)
dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
s->clks[best_clk], baud, min_err);
sci_port_enable(s);
/* * Program the optional External Baud Rate Generator (BRG) first. * It controls the mux to select (H)SCK or frequency divided clock.
*/ if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
sci_serial_out(port, SCDL, dl);
sci_serial_out(port, SCCKS, sccks);
}
/* byte size and parity */
bits = tty_get_frame_size(termios->c_cflag);
if (sci_getreg(port, SEMR)->size)
sci_serial_out(port, SEMR, 0);
if (best_clk >= 0) { if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) switch (srr + 1) { case 5: smr_val |= SCSMR_SRC_5; break; case 7: smr_val |= SCSMR_SRC_7; break; case 11: smr_val |= SCSMR_SRC_11; break; case 13: smr_val |= SCSMR_SRC_13; break; case 16: smr_val |= SCSMR_SRC_16; break; case 17: smr_val |= SCSMR_SRC_17; break; case 19: smr_val |= SCSMR_SRC_19; break; case 27: smr_val |= SCSMR_SRC_27; break;
}
smr_val |= cks;
sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
sci_serial_out(port, SCSMR, smr_val);
sci_serial_out(port, SCBRR, brr); if (sci_getreg(port, HSSRR)->size) { unsignedint hssrr = srr | HSCIF_SRE; /* Calculate deviation from intended rate at the * center of the last stop bit in sampling clocks.
*/ int last_stop = bits * 2 - 1; int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
(int)(srr + 1),
2 * (int)baud);
if (abs(deviation) >= 2) { /* At least two sampling clocks off at the * last stop bit; we can increase the error * margin by shifting the sampling point.
*/ int shift = clamp(deviation / 2, -8, 7);
if ((port->flags & UPF_HARD_FLOW) &&
(termios->c_cflag & CRTSCTS)) { /* There is no CTS interrupt to restart the hardware */
port->status |= UPSTAT_AUTOCTS; /* MCE is enabled when RTS is raised */
s->autorts = true;
}
/* * As we've done a sci_reset() above, ensure we don't * interfere with the FIFOs while toggling MCE. As the * reset values could still be set, simply mask them out.
*/
ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
/* * For SCI, TE (transmit enable) must be set after setting TIE * (transmit interrupt enable) or in the same instruction to * start the transmitting process. So skip setting TE here for SCI.
*/ if (s->type != PORT_SCI)
scr_val |= SCSCR_TE;
scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
sci_serial_out(port, SCSCR, scr_val | s->hscif_tot); if ((srr + 1 == 5) &&
(s->type == PORT_SCIFA || s->type == PORT_SCIFB)) { /* * In asynchronous mode, when the sampling rate is 1/5, first * received data may become invalid on some SCIFA and SCIFB. * To avoid this problem wait more than 1 serial data time (1 * bit time x serial data number) after setting SCSCR.RE = 1.
*/
udelay(DIV_ROUND_UP(10 * 1000000, baud));
}
switch (s->type) { case PORT_IRDA: return"irda"; case PORT_SCI: return"sci"; case PORT_SCIF: return"scif"; case PORT_SCIFA: return"scifa"; case PORT_SCIFB: return"scifb"; case PORT_HSCIF: return"hscif";
}
/* * Nothing to do if there's already an established membase.
*/ if (port->membase) return 0;
if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
port->membase = ioremap(port->mapbase, sport->reg_size); if (unlikely(!port->membase)) {
dev_err(port->dev, "can't remap port#%d\n", port->line); return -ENXIO;
}
} else { /* * For the simple (and majority of) cases where we don't * need to do any remapping, just cast the cookie * directly.
*/
port->membase = (void __iomem *)(uintptr_t)port->mapbase;
}
int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
{ if (ser->baud_base < 2400) /* No paper tape reader for Mitch.. */ return -EINVAL;
for (i = 0; i < SCI_NUM_CLKS; i++) { constchar *name = clk_names[i];
clk = devm_clk_get_optional(dev, name); if (IS_ERR(clk)) return PTR_ERR(clk);
if (!clk && sci_port->type == SCI_PORT_RSCI &&
(i == SCI_FCK || i == SCI_BRG_INT)) { return dev_err_probe(dev, -ENODEV, "failed to get %s\n",
name);
}
if (!clk && i == SCI_FCK) { /* * Not all SH platforms declare a clock lookup entry * for SCI devices, in which case we need to get the * global "peripheral_clk" clock.
*/
clk = devm_clk_get(dev, "peripheral_clk"); if (IS_ERR(clk)) return dev_err_probe(dev, PTR_ERR(clk), "failed to get %s\n",
name);
}
if (!clk)
dev_dbg(dev, "failed to get %s\n", name); else
dev_dbg(dev, "clk %s is %pC rate %lu\n", name,
clk, clk_get_rate(clk));
sci_port->clks[i] = clk;
} return 0;
}
if (cfg->regtype != SCIx_PROBE_REGTYPE) return &sci_port_params[cfg->regtype];
switch (cfg->type) { case PORT_SCI:
regtype = SCIx_SCI_REGTYPE; break; case PORT_IRDA:
regtype = SCIx_IRDA_REGTYPE; break; case PORT_SCIFA:
regtype = SCIx_SCIFA_REGTYPE; break; case PORT_SCIFB:
regtype = SCIx_SCIFB_REGTYPE; break; case PORT_SCIF: /* * The SH-4 is a bit of a misnomer here, although that's * where this particular port layout originated. This * configuration (or some slight variation thereof) * remains the dominant model for all SCIFs.
*/
regtype = SCIx_SH4_SCIF_REGTYPE; break; case PORT_HSCIF:
regtype = SCIx_HSCIF_REGTYPE; break; default:
pr_err("Can't probe register map for given port\n"); return NULL;
}
for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { if (i)
sci_port->irqs[i] = platform_get_irq_optional(dev, i); else
sci_port->irqs[i] = platform_get_irq(dev, i);
}
/* * The fourth interrupt on SCI and RSCI port is transmit end interrupt, so * shuffle the interrupts.
*/ if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI)
swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
/* The SCI generates several interrupts. They can be muxed together or * connected to different interrupt lines. In the muxed case only one * interrupt resource is specified as there is only one interrupt ID. * In the non-muxed case, up to 6 interrupt signals might be generated * from the SCI, however those signals might have their own individual * interrupt ID numbers, or muxed together with another interrupt.
*/ if (sci_port->irqs[0] < 0) return -ENXIO;
if (sci_port->irqs[1] < 0) for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
sci_port->irqs[i] = sci_port->irqs[0];
switch (p->type) { case PORT_SCIFB:
sci_port->rx_trigger = 48; break; case PORT_HSCIF:
sci_port->rx_trigger = 64; break; case PORT_SCIFA:
sci_port->rx_trigger = 32; break; case PORT_SCIF: if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) /* RX triggering not implemented for this IP */
sci_port->rx_trigger = 1; else
sci_port->rx_trigger = 8; break; case SCI_PORT_RSCI:
sci_port->rx_trigger = 15; break; default:
sci_port->rx_trigger = 1; break;
}
/* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't * match the SoC datasheet, this should be investigated. Let platform * data override the sampling rate for now.
*/
sci_port->sampling_rate_mask = p->sampling_rate
? SCI_SR(p->sampling_rate)
: sci_port->params->sampling_rate_mask;
if (!early) {
ret = sci_init_clocks(sci_port, &dev->dev); if (ret < 0) return ret;
}
if (p->type == PORT_SCI && !dev->dev.of_node) { if (sci_port->reg_size >= 0x20)
port->regshift = 2; else
port->regshift = 1;
}
/* * The UART port needs an IRQ value, so we peg this to the RX IRQ * for the multi-IRQ ports, which is where we are primarily * concerned with the shutdown path synchronization. * * For the muxed case there's nothing more to do.
*/
port->irq = sci_port->irqs[SCIx_RXI_IRQ];
port->irqflags = 0;
/* * Print a string to the serial port trying not to disturb * any possible real use of the port...
*/ staticvoid serial_console_write(struct console *co, constchar *s, unsigned count)
{ struct sci_port *sci_port = &sci_ports[co->index]; struct uart_port *port = &sci_port->port; conststruct sci_common_regs *regs = sci_port->params->common_regs; unsignedint bits;
u32 ctrl; unsignedlong flags; int locked = 1;
staticint early_serial_console_setup(struct console *co, char *options)
{ /* * This early console is always registered using the earlyprintk= * parameter, which does not call add_preferred_console(). Thus * @options is always NULL and the options for this early console * are passed using a custom buffer.
*/
WARN_ON(options);
if (s->port.fifosize > 1)
device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
type == SCI_PORT_RSCI)
device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
}
if (!IS_ENABLED(CONFIG_OF) || !np) return ERR_PTR(-EINVAL);
data = of_device_get_match_data(&pdev->dev);
rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), "failed to get reset ctrl\n"));
ret = reset_control_deassert(rstc); if (ret) {
dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); return ERR_PTR(ret);
}
ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); if (ret) {
dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
ret); return ERR_PTR(ret);
}
p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); if (!p) return ERR_PTR(-ENOMEM);
/* Get the line number from the aliases node. */
id = of_alias_get_id(np, "serial"); if (id < 0 && ~sci_ports_in_use)
id = ffz(sci_ports_in_use); if (id < 0) {
dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); return ERR_PTR(-EINVAL);
} if (id >= ARRAY_SIZE(sci_ports)) {
dev_err(&pdev->dev, "serial%d out of range\n", id); return ERR_PTR(-EINVAL);
}
if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) { /* * In case: * - this is the earlycon port (mapped on index 0 in sci_ports[]) and * - it now maps to an alias other than zero and * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is * available in bootargs) * * we need to avoid disabling clocks and PM domains through the runtime * PM APIs called in __device_attach(). For this, increment the runtime * PM reference counter (the clocks and PM domains were already enabled * by the bootloader). Otherwise the earlycon may access the HW when it * has no clocks enabled leading to failures (infinite loop in * sci_poll_put_char()).
*/
pm_runtime_get_noresume(&dev->dev);
/* * Skip cleanup the sci_port[0] in early_console_exit(), this * port is the same as the earlycon one.
*/
sci_uart_earlycon_dev_probing = true;
}
/* * If we've come here via earlyprintk initialization, head off to * the special early probe. We don't have sufficient device state * to make it beyond this yet.
*/ #ifdef CONFIG_SUPERH if (is_sh_early_platform_device(dev)) return sci_probe_earlyprintk(dev); #endif
if (dev->dev.of_node) {
p = sci_parse_dt(dev, &dev_id); if (IS_ERR(p)) return PTR_ERR(p);
sp = &sci_ports[dev_id];
} else {
p = dev->dev.platform_data; if (p == NULL) {
dev_err(&dev->dev, "no platform data supplied\n"); return -EINVAL;
}
sp->suspend_regs = devm_kzalloc(&dev->dev,
sp->ops->suspend_regs_size(),
GFP_KERNEL); if (!sp->suspend_regs) return -ENOMEM;
/* * In case: * - the probed port alias is zero (as the one used by earlycon), and * - the earlycon is still active (e.g., "earlycon keep_bootcon" in * bootargs) * * defer the probe of this serial. This is a debug scenario and the user * must be aware of it. * * Except when the probed port is the same as the earlycon port.
*/
res = platform_get_resource(dev, IORESOURCE_MEM, 0); if (!res) return -ENODEV;
if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start) return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
platform_set_drvdata(dev, sp);
ret = sci_probe_single(dev, dev_id, p, sp, res); if (ret) return ret;
if (sp->port.fifosize > 1) {
ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); if (ret) return ret;
} if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB ||
sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) {
ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); if (ret) { if (sp->port.fifosize > 1) {
device_remove_file(&dev->dev,
&dev_attr_rx_fifo_trigger);
} return ret;
}
}
if (sport) { if (!console_suspend_enabled && uart_console(&sport->port)) { if (sport->ops->console_restore)
sport->ops->console_restore(&sport->port);
} else { int ret = reset_control_deassert(sport->rstc);
/* * Clean the slot used by earlycon. A new SCI device might * map to this slot.
*/ if (!sci_uart_earlycon_dev_probing) {
memset(sci_port, 0, sizeof(*sci_port));
sci_uart_earlycon = false;
}
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