/* USB_CONF - bitmasks */ /* Reset USB device configuration. */ #define USB_CONF_CFGRST BIT(0) /* Set Configuration. */ #define USB_CONF_CFGSET BIT(1) /* Disconnect USB device in SuperSpeed. */ #define USB_CONF_USB3DIS BIT(3) /* Disconnect USB device in HS/FS */ #define USB_CONF_USB2DIS BIT(4) /* Little Endian access - default */ #define USB_CONF_LENDIAN BIT(5) /* * Big Endian access. Driver assume that byte order for * SFRs access always is as Little Endian so this bit * is not used.
*/ #define USB_CONF_BENDIAN BIT(6) /* Device software reset. */ #define USB_CONF_SWRST BIT(7) /* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/ #define USB_CONF_DSING BIT(8) /* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */ #define USB_CONF_DMULT BIT(9) /* DMA clock turn-off enable. */ #define USB_CONF_DMAOFFEN BIT(10) /* DMA clock turn-off disable. */ #define USB_CONF_DMAOFFDS BIT(11) /* Clear Force Full Speed. */ #define USB_CONF_CFORCE_FS BIT(12) /* Set Force Full Speed. */ #define USB_CONF_SFORCE_FS BIT(13) /* Device enable. */ #define USB_CONF_DEVEN BIT(14) /* Device disable. */ #define USB_CONF_DEVDS BIT(15) /* L1 LPM state entry enable (used in HS/FS mode). */ #define USB_CONF_L1EN BIT(16) /* L1 LPM state entry disable (used in HS/FS mode). */ #define USB_CONF_L1DS BIT(17) /* USB 2.0 clock gate disable. */ #define USB_CONF_CLK2OFFEN BIT(18) /* USB 2.0 clock gate enable. */ #define USB_CONF_CLK2OFFDS BIT(19) /* L0 LPM state entry request (used in HS/FS mode). */ #define USB_CONF_LGO_L0 BIT(20) /* USB 3.0 clock gate disable. */ #define USB_CONF_CLK3OFFEN BIT(21) /* USB 3.0 clock gate enable. */ #define USB_CONF_CLK3OFFDS BIT(22) /* Bit 23 is reserved*/ /* U1 state entry enable (used in SS mode). */ #define USB_CONF_U1EN BIT(24) /* U1 state entry disable (used in SS mode). */ #define USB_CONF_U1DS BIT(25) /* U2 state entry enable (used in SS mode). */ #define USB_CONF_U2EN BIT(26) /* U2 state entry disable (used in SS mode). */ #define USB_CONF_U2DS BIT(27) /* U0 state entry request (used in SS mode). */ #define USB_CONF_LGO_U0 BIT(28) /* U1 state entry request (used in SS mode). */ #define USB_CONF_LGO_U1 BIT(29) /* U2 state entry request (used in SS mode). */ #define USB_CONF_LGO_U2 BIT(30) /* SS.Inactive state entry request (used in SS mode) */ #define USB_CONF_LGO_SSINACT BIT(31)
/* USB_STS - bitmasks */ /* * Configuration status. * 1 - device is in the configured state. * 0 - device is not configured.
*/ #define USB_STS_CFGSTS_MASK BIT(0) #define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK) /* * On-chip memory overflow. * 0 - On-chip memory status OK. * 1 - On-chip memory overflow.
*/ #define USB_STS_OV_MASK BIT(1) #define USB_STS_OV(p) ((p) & USB_STS_OV_MASK) /* * SuperSpeed connection status. * 0 - USB in SuperSpeed mode disconnected. * 1 - USB in SuperSpeed mode connected.
*/ #define USB_STS_USB3CONS_MASK BIT(2) #define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK) /* * DMA transfer configuration status. * 0 - single request. * 1 - multiple TRB chain * Supported only for controller version < DEV_VER_V3
*/ #define USB_STS_DTRANS_MASK BIT(3) #define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK) /* * Device speed. * 0 - Undefined (value after reset). * 1 - Low speed * 2 - Full speed * 3 - High speed * 4 - Super speed
*/ #define USB_STS_USBSPEED_MASK GENMASK(6, 4) #define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4) #define USB_STS_LS (0x1 << 4) #define USB_STS_FS (0x2 << 4) #define USB_STS_HS (0x3 << 4) #define USB_STS_SS (0x4 << 4) #define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4)) #define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS) #define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS) #define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS) #define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS) /* * Endianness for SFR access. * 0 - Little Endian order (default after hardware reset). * 1 - Big Endian order
*/ #define USB_STS_ENDIAN_MASK BIT(7) #define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK) /* * HS/FS clock turn-off status. * 0 - hsfs clock is always on. * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled * (default after hardware reset).
*/ #define USB_STS_CLK2OFF_MASK BIT(8) #define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK) /* * PCLK clock turn-off status. * 0 - pclk clock is always on. * 1 - pclk clock turn-off in U3 (SS mode) is enabled * (default after hardware reset).
*/ #define USB_STS_CLK3OFF_MASK BIT(9) #define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK) /* * Controller in reset state. * 0 - Internal reset is active. * 1 - Internal reset is not active and controller is fully operational.
*/ #define USB_STS_IN_RST_MASK BIT(10) #define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK) /* * Status of the "TDL calculation basing on TRB" feature. * 0 - disabled * 1 - enabled * Supported only for DEV_VER_V2 controller version.
*/ #define USB_STS_TDL_TRB_ENABLED BIT(11) /* * Device enable Status. * 0 - USB device is disabled (VBUS input is disconnected from internal logic). * 1 - USB device is enabled (VBUS input is connected to the internal logic).
*/ #define USB_STS_DEVS_MASK BIT(14) #define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK) /* * Address status. * 0 - USB device is default state. * 1 - USB device is at least in address state.
*/ #define USB_STS_ADDRESSED_MASK BIT(15) #define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK) /* * L1 LPM state enable status (used in HS/FS mode). * 0 - Entering to L1 LPM state disabled. * 1 - Entering to L1 LPM state enabled.
*/ #define USB_STS_L1ENS_MASK BIT(16) #define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK) /* * Internal VBUS connection status (used both in HS/FS and SS mode). * 0 - internal VBUS is not detected. * 1 - internal VBUS is detected.
*/ #define USB_STS_VBUSS_MASK BIT(17) #define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK) /* * HS/FS LPM state (used in FS/HS mode). * 0 - L0 State * 1 - L1 State * 2 - L2 State * 3 - L3 State
*/ #define USB_STS_LPMST_MASK GENMASK(19, 18) #define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18)) #define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18)) #define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18)) #define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18)) /* * Disable HS status (used in FS/HS mode). * 0 - the disconnect bit for HS/FS mode is set . * 1 - the disconnect bit for HS/FS mode is not set.
*/ #define USB_STS_USB2CONS_MASK BIT(20) #define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK) /* * HS/FS mode connection status (used in FS/HS mode). * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled. * 1 - High Speed operations in USB2.0 (FS/HS).
*/ #define USB_STS_DISABLE_HS_MASK BIT(21) #define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK) /* * U1 state enable status (used in SS mode). * 0 - Entering to U1 state disabled. * 1 - Entering to U1 state enabled.
*/ #define USB_STS_U1ENS_MASK BIT(24) #define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK) /* * U2 state enable status (used in SS mode). * 0 - Entering to U2 state disabled. * 1 - Entering to U2 state enabled.
*/ #define USB_STS_U2ENS_MASK BIT(25) #define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK) /* * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current * SuperSpeed link state
*/ #define USB_STS_LST_MASK GENMASK(29, 26) #define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26)) #define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26)) #define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26)) #define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26)) #define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26)) #define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26)) #define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26)) #define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26)) #define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26)) #define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26)) #define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26)) #define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26)) /* * DMA clock turn-off status. * 0 - DMA clock is always on (default after hardware reset). * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
*/ #define USB_STS_DMAOFF_MASK BIT(30) #define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK) /* * SFR Endian status. * 0 - Little Endian order (default after hardware reset). * 1 - Big Endian order.
*/ #define USB_STS_ENDIAN2_MASK BIT(31) #define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK)
/* USB_CMD - bitmasks */ /* Set Function Address */ #define USB_CMD_SET_ADDR BIT(0) /* * Function Address This field is saved to the device only when the field * SET_ADDR is set '1 ' during write to USB_CMD register. * Software is responsible for entering the address of the device during * SET_ADDRESS request service. This field should be set immediately after * the SETUP packet is decoded, and prior to confirmation of the status phase
*/ #define USB_CMD_FADDR_MASK GENMASK(7, 1) #define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK) /* Send Function Wake Device Notification TP (used only in SS mode). */ #define USB_CMD_SDNFW BIT(8) /* Set Test Mode (used only in HS/FS mode). */ #define USB_CMD_STMODE BIT(9) /* Test mode selector (used only in HS/FS mode) */ #define USB_STS_TMODE_SEL_MASK GENMASK(11, 10) #define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK) /* * Send Latency Tolerance Message Device Notification TP (used only * in SS mode).
*/ #define USB_CMD_SDNLTM BIT(12) /* Send Custom Transaction Packet (used only in SS mode) */ #define USB_CMD_SPKT BIT(13) /*Device Notification 'Function Wake' - Interface value (only in SS mode. */ #define USB_CMD_DNFW_INT_MASK GENMASK(23, 16) #define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK) /* * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0] * (used only in SS mode).
*/ #define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16) #define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
/* USB_ITPN - bitmasks */ /* * ITP(SS) / SOF (HS/FS) number * In SS mode this field represent number of last ITP received from host. * In HS/FS mode this field represent number of last SOF received from host.
*/ #define USB_ITPN_MASK GENMASK(13, 0) #define USB_ITPN(p) ((p) & USB_ITPN_MASK)
/* USB_PWR- bitmasks */ /*Power Shut Off capability enable*/ #define PUSB_PWR_PSO_EN BIT(0) /*Power Shut Off capability disable*/ #define PUSB_PWR_PSO_DS BIT(1) /* * Enables turning-off Reference Clock. * This bit is optional and implemented only when support for OTG is * implemented (indicated by OTG_READY bit set to '1').
*/ #define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8) /* * Status bit indicating that operation required by STB_CLK_SWITCH_EN write * is completed
*/ #define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9) /* This bit informs if Fast Registers Access is enabled. */ #define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30) /* Fast Registers Access Enable. */ #define PUSB_PWR_FST_REG_ACCESS BIT(31)
/* USB_CONF2- bitmasks */ /* * Writing 1 disables TDL calculation basing on TRB feature in controller * for DMULT mode. * Bit supported only for DEV_VER_V2 version.
*/ #define USB_CONF2_DIS_TDL_TRB BIT(1) /* * Writing 1 enables TDL calculation basing on TRB feature in controller * for DMULT mode. * Bit supported only for DEV_VER_V2 version.
*/ #define USB_CONF2_EN_TDL_TRB BIT(2)
/* * USB2 PHY Interface enable * These field informs if USB2 PHY interface is implemented: * 0x0 - interface NOT implemented, * 0x1 - interface implemented
*/ #define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24)) /* * USB2 PHY Interface type * These field reflects type of USB2 PHY interface implemented: * 0x0 - UTMI, * 0x1 - ULPI
*/ #define DEV_U2PHY_ULPI(p) ((p) & BIT(25)) /* * USB2 PHY Interface width * These field reflects width of USB2 PHY interface implemented: * 0x0 - 8 bit interface, * 0x1 - 16 bit interface, * Note: The ULPI interface is always 8bit wide.
*/ #define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26)) /* * OTG Ready * 0x0 - pure device mode * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
*/ #define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
/* * When set, indicates that controller supports automatic internal TDL * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode * Supported only for DEV_VER_V2 controller version.
*/ #define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
/* USB_CAP2- bitmasks */ /* * The actual size of the connected On-chip RAM memory in kB: * - 0 means 256 kB (max supported mem size) * - value other than 0 reflects the mem size in kB
*/ #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0)) /* * Max supported mem size * These field reflects width of on-chip RAM address bus width, * which determines max supported mem size: * 0x0-0x7 - reserved, * 0x8 - support for 4kB mem, * 0x9 - support for 8kB mem, * 0xA - support for 16kB mem, * 0xB - support for 32kB mem, * 0xC - support for 64kB mem, * 0xD - support for 128kB mem, * 0xE - support for 256kB mem, * 0xF - reserved
*/ #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
/* DBG_LINK1- bitmasks */ /* * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum * time required for decoding the received LFPS as an LFPS.U1_Exit.
*/ #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0)) /* * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for * phytxelecidle deassertion when LFPS.U1_Exit
*/ #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8) #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8)) /* * RXDET_BREAK_DIS value This parameter configures terminating the Far-end * Receiver termination detection sequence: * 0: it is possible that USBSS_DEV will terminate Farend receiver * termination detection sequence * 1: USBSS_DEV will not terminate Far-end receiver termination * detection sequence
*/ #define DBG_LINK1_RXDET_BREAK_DIS BIT(16) /* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */ #define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17)) /* * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically * cleared. Writing '0' has no effect
*/ #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24) /* * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically * cleared. Writing '0' has no effect
*/ #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25) /* * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes * the RXDET_BREAK_DIS field value to the device. This bit is automatically * cleared. Writing '0' has no effect
*/ #define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26) /* * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes * the LFPS_GEN_PING field value to the device. This bit is automatically * cleared. Writing '0' has no effect."
*/ #define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
#if TRBS_PER_SEGMENT < 2 #error"Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2." #endif
#define TRBS_PER_STREAM_SEGMENT 2
#if TRBS_PER_STREAM_SEGMENT < 2 #error"Incorrect TRBS_PER_STREAMS_SEGMENT. Minimal Transfer Ring size is 2." #endif
/* *Only for ISOC endpoints - maximum number of TRBs is calculated as * pow(2, bInterval-1) * number of usb requests. It is limitation made by * driver to save memory. Controller must prepare TRB for each ITP even * if bInterval > 1. It's the reason why driver needs so many TRBs for * isochronous endpoints.
*/ #define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8)
#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT) /** * struct cdns3_trb - represent Transfer Descriptor block. * @buffer: pointer to buffer data * @length: length of data * @control: control flags. * * This structure describes transfer block serviced by DMA module.
*/ struct cdns3_trb {
__le32 buffer;
__le32 length;
__le32 control;
};
/* TRB type IDs */ /* bulk, interrupt, isoc , and control data stage */ #define TRB_NORMAL 1 /* TRB for linking ring segments */ #define TRB_LINK 6
/* Cycle bit - indicates TRB ownership by driver or hw*/ #define TRB_CYCLE BIT(0) /* * When set to '1', the device will toggle its interpretation of the Cycle bit
*/ #define TRB_TOGGLE BIT(1) /* * The controller will set it if OUTSMM (OUT size mismatch) is detected, * this bit is for normal TRB
*/ #define TRB_SMM BIT(1)
/* * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was * processed while USB short packet was received. No more buffers defined by * the TD will be used. DMA will automatically advance to next TD. * - Shall be set to 0 by Software when putting TRB on the Transfer Ring * - Shall be set to 1 by Controller when Short Packet condition for this TRB * is detected independent if ISP is set or not.
*/ #define TRB_SP BIT(1)
/* Interrupt on short packet*/ #define TRB_ISP BIT(2) /*Setting this bit enables FIFO DMA operation mode*/ #define TRB_FIFO_MODE BIT(3) /* Set PCIe no snoop attribute */ #define TRB_CHAIN BIT(4) /* Interrupt on completion */ #define TRB_IOC BIT(5)
/** * struct cdns3_endpoint - extended device side representation of USB endpoint. * @endpoint: usb endpoint * @pending_req_list: list of requests queuing on transfer ring. * @deferred_req_list: list of requests waiting for queuing on transfer ring. * @wa2_descmiss_req_list: list of requests internally allocated by driver. * @trb_pool: transfer ring - array of transaction buffers * @trb_pool_dma: dma address of transfer ring * @cdns3_dev: device associated with this endpoint * @name: a human readable name e.g. ep1out * @flags: specify the current state of endpoint * @descmis_req: internal transfer object used for getting data from on-chip * buffer. It can happen only if function driver doesn't send usb_request * object on time. * @dir: endpoint direction * @num: endpoint number (1 - 15) * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK * @interval: interval between packets used for ISOC endpoint. * @free_trbs: number of free TRBs in transfer ring * @num_trbs: number of all TRBs in transfer ring * @alloc_ring_size: size of the allocated TRB ring * @pcs: producer cycle state * @ccs: consumer cycle state * @enqueue: enqueue index in transfer ring * @dequeue: dequeue index in transfer ring * @trb_burst_size: number of burst used in trb.
*/ struct cdns3_endpoint { struct usb_ep endpoint; struct list_head pending_req_list; struct list_head deferred_req_list; struct list_head wa2_descmiss_req_list; int wa2_counter;
/** * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer * @buf: aligned to 8 bytes data buffer. Buffer address used in * TRB shall be aligned to 8. * @dma: dma address * @size: size of buffer * @in_use: inform if this buffer is associated with usb_request * @list: used to adding instance of this object to list
*/ struct cdns3_aligned_buf { void *buf;
dma_addr_t dma;
u32 size; enum dma_data_direction dir; unsigned in_use:1; struct list_head list;
};
/** * struct cdns3_request - extended device side representation of usb_request * object . * @request: generic usb_request object describing single I/O request. * @priv_ep: extended representation of usb_ep object * @trb: the first TRB association with this request * @start_trb: number of the first TRB in transfer ring * @end_trb: number of the last TRB in transfer ring * @aligned_buf: object holds information about aligned buffer associated whit * this endpoint * @flags: flag specifying special usage of request * @list: used by internally allocated request to add to wa2_descmiss_req_list. * @finished_trb: number of trb has already finished per request * @num_of_trb: how many trbs in this request
*/ struct cdns3_request { struct usb_request request; struct cdns3_endpoint *priv_ep; struct cdns3_trb *trb; int start_trb; int end_trb; struct cdns3_aligned_buf *aligned_buf; #define REQUEST_PENDING BIT(0) #define REQUEST_INTERNAL BIT(1) #define REQUEST_INTERNAL_CH BIT(2) #define REQUEST_ZLP BIT(3) #define REQUEST_UNALIGNED BIT(4)
u32 flags; struct list_head list; int finished_trb; int num_of_trb;
};
/*Stages used during enumeration process.*/ #define CDNS3_SETUP_STAGE 0x0 #define CDNS3_DATA_STAGE 0x1 #define CDNS3_STATUS_STAGE 0x2
/** * struct cdns3_device - represent USB device. * @dev: pointer to device structure associated whit this controller * @sysdev: pointer to the DMA capable device * @gadget: device side representation of the peripheral controller * @gadget_driver: pointer to the gadget driver * @dev_ver: device controller version. * @lock: for synchronizing * @regs: base address for device side registers * @setup_buf: used while processing usb control requests * @setup_dma: dma address for setup_buf * @zlp_buf - zlp buffer * @ep0_stage: ep0 stage during enumeration process. * @ep0_data_dir: direction for control transfer * @eps: array of pointers to all endpoints with exclusion ep0 * @aligned_buf_list: list of aligned buffers internally allocated by driver * @aligned_buf_wq: workqueue freeing no longer used aligned buf. * @selected_ep: actually selected endpoint. It's used only to improve * performance. * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP. * @u1_allowed: allow device transition to u1 state * @u2_allowed: allow device transition to u2 state * @is_selfpowered: device is self powered * @setup_pending: setup packet is processing by gadget driver * @hw_configured_flag: hardware endpoint configuration was set. * @wake_up_flag: allow device to remote up the host * @status_completion_no_call: indicate that driver is waiting for status s * stage completion. It's used in deferred SET_CONFIGURATION request. * @onchip_buffers: number of available on-chip buffers. * @onchip_used_size: actual size of on-chip memory assigned to endpoints. * @pending_status_wq: workqueue handling status stage for deferred requests. * @pending_status_request: request for which status stage was deferred
*/ struct cdns3_device { struct device *dev; struct device *sysdev;
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