Quelle  amlogic,s4-pll-clkc.h

/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
 * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
 * Author: Yu Tu <yu.tu@amlogic.com>
 */

#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H

#define CLKID_FIXED_PLL_DCO  0
#define CLKID_FIXED_PLL   1
#define CLKID_FCLK_DIV2_DIV  2
#define CLKID_FCLK_DIV2   3
#define CLKID_FCLK_DIV3_DIV  4
#define CLKID_FCLK_DIV3   5
#define CLKID_FCLK_DIV4_DIV  6
#define CLKID_FCLK_DIV4   7
#define CLKID_FCLK_DIV5_DIV  8
#define CLKID_FCLK_DIV5   9
#define CLKID_FCLK_DIV7_DIV  10
#define CLKID_FCLK_DIV7   11
#define CLKID_FCLK_DIV2P5_DIV  12
#define CLKID_FCLK_DIV2P5  13
#define CLKID_GP0_PLL_DCO  14
#define CLKID_GP0_PLL   15
#define CLKID_HIFI_PLL_DCO  16
#define CLKID_HIFI_PLL   17
#define CLKID_HDMI_PLL_DCO  18
#define CLKID_HDMI_PLL_OD  19
#define CLKID_HDMI_PLL   20
#define CLKID_MPLL_50M_DIV  21
#define CLKID_MPLL_50M   22
#define CLKID_MPLL_PREDIV  23
#define CLKID_MPLL0_DIV   24
#define CLKID_MPLL0   25
#define CLKID_MPLL1_DIV   26
#define CLKID_MPLL1   27
#define CLKID_MPLL2_DIV   28
#define CLKID_MPLL2   29
#define CLKID_MPLL3_DIV   30
#define CLKID_MPLL3   31

#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */