struct imx_dma_data { int dma_request; /* DMA request line */ int dma_request2; /* secondary DMA request line */ enum sdma_peripheral_type peripheral_type; int priority;
};
/** * struct sdma_peripheral_config - SDMA config for audio * @n_fifos_src: Number of FIFOs for recording * @n_fifos_dst: Number of FIFOs for playback * @stride_fifos_src: FIFO address stride for recording, 0 means all FIFOs are * continuous, 1 means 1 word stride between FIFOs. All stride * between FIFOs should be same. * @stride_fifos_dst: FIFO address stride for playback * @words_per_fifo: numbers of words per FIFO fetch/fill, 1 means * one channel per FIFO, 2 means 2 channels per FIFO.. * If 'n_fifos_src = 4' and 'words_per_fifo = 2', it * means the first two words(channels) fetch from FIFO0 * and then jump to FIFO1 for next two words, and so on * after the last FIFO3 fetched, roll back to FIFO0. * @sw_done: Use software done. Needed for PDM (micfil) * * Some i.MX Audio devices (SAI, micfil) have multiple successive FIFO * registers. For multichannel recording/playback the SAI/micfil have * one FIFO register per channel and the SDMA engine has to read/write * the next channel from/to the next register and wrap around to the * first register when all channels are handled. The number of active * channels must be communicated to the SDMA engine using this struct.
*/ struct sdma_peripheral_config { int n_fifos_src; int n_fifos_dst; int stride_fifos_src; int stride_fifos_dst; int words_per_fifo; bool sw_done;
};
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