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Quelle  mlx5_ifc.h   Sprache: C

 
/*
 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
*/

#ifndef MLX5_IFC_H
#define MLX5_IFC_H

#include "mlx5_ifc_fpga.h"

enum {
 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
 MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
 MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
 MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
};

enum {
 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
 MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
 MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
 MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
};

enum {
 MLX5_SHARED_RESOURCE_UID = 0xffff,
};

enum {
 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
 MLX5_OBJ_TYPE_STC = 0x0040,
 MLX5_OBJ_TYPE_RTC = 0x0041,
 MLX5_OBJ_TYPE_STE = 0x0042,
 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
 MLX5_OBJ_TYPE_MKEY = 0xff01,
 MLX5_OBJ_TYPE_QP = 0xff02,
 MLX5_OBJ_TYPE_PSV = 0xff03,
 MLX5_OBJ_TYPE_RMP = 0xff04,
 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 MLX5_OBJ_TYPE_RQ = 0xff06,
 MLX5_OBJ_TYPE_SQ = 0xff07,
 MLX5_OBJ_TYPE_TIR = 0xff08,
 MLX5_OBJ_TYPE_TIS = 0xff09,
 MLX5_OBJ_TYPE_DCT = 0xff0a,
 MLX5_OBJ_TYPE_XRQ = 0xff0b,
 MLX5_OBJ_TYPE_RQT = 0xff0e,
 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 MLX5_OBJ_TYPE_CQ = 0xff10,
 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
};

enum {
 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
  (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
};

enum {
 MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 MLX5_CMD_OP_INIT_HCA                      = 0x102,
 MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
 MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
 MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
 MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
 MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 MLX5_CMD_OP_GEN_EQE                       = 0x304,
 MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 MLX5_CMD_OP_CREATE_QP                     = 0x500,
 MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 MLX5_CMD_OP_2ERR_QP                       = 0x507,
 MLX5_CMD_OP_2RST_QP                       = 0x50a,
 MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 MLX5_CMD_OP_ARM_RQ                        = 0x703,
 MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 MLX5_CMD_OP_NOP                           = 0x80d,
 MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT    = 0x92f,
 MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
 MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
 MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
 MLX5_CMD_OP_MAX
};

/* Valid range for general commands that don't work over an object */
enum {
 MLX5_CMD_OP_GENERAL_START = 0xb00,
 MLX5_CMD_OP_GENERAL_END = 0xd00,
};

enum {
 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
};

enum {
 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
};

struct mlx5_ifc_flow_table_fields_supported_bits {
 u8         outer_dmac[0x1];
 u8         outer_smac[0x1];
 u8         outer_ether_type[0x1];
 u8         outer_ip_version[0x1];
 u8         outer_first_prio[0x1];
 u8         outer_first_cfi[0x1];
 u8         outer_first_vid[0x1];
 u8         outer_ipv4_ttl[0x1];
 u8         outer_second_prio[0x1];
 u8         outer_second_cfi[0x1];
 u8         outer_second_vid[0x1];
 u8         reserved_at_b[0x1];
 u8         outer_sip[0x1];
 u8         outer_dip[0x1];
 u8         outer_frag[0x1];
 u8         outer_ip_protocol[0x1];
 u8         outer_ip_ecn[0x1];
 u8         outer_ip_dscp[0x1];
 u8         outer_udp_sport[0x1];
 u8         outer_udp_dport[0x1];
 u8         outer_tcp_sport[0x1];
 u8         outer_tcp_dport[0x1];
 u8         outer_tcp_flags[0x1];
 u8         outer_gre_protocol[0x1];
 u8         outer_gre_key[0x1];
 u8         outer_vxlan_vni[0x1];
 u8         outer_geneve_vni[0x1];
 u8         outer_geneve_oam[0x1];
 u8         outer_geneve_protocol_type[0x1];
 u8         outer_geneve_opt_len[0x1];
 u8         source_vhca_port[0x1];
 u8         source_eswitch_port[0x1];

 u8         inner_dmac[0x1];
 u8         inner_smac[0x1];
 u8         inner_ether_type[0x1];
 u8         inner_ip_version[0x1];
 u8         inner_first_prio[0x1];
 u8         inner_first_cfi[0x1];
 u8         inner_first_vid[0x1];
 u8         reserved_at_27[0x1];
 u8         inner_second_prio[0x1];
 u8         inner_second_cfi[0x1];
 u8         inner_second_vid[0x1];
 u8         reserved_at_2b[0x1];
 u8         inner_sip[0x1];
 u8         inner_dip[0x1];
 u8         inner_frag[0x1];
 u8         inner_ip_protocol[0x1];
 u8         inner_ip_ecn[0x1];
 u8         inner_ip_dscp[0x1];
 u8         inner_udp_sport[0x1];
 u8         inner_udp_dport[0x1];
 u8         inner_tcp_sport[0x1];
 u8         inner_tcp_dport[0x1];
 u8         inner_tcp_flags[0x1];
 u8         reserved_at_37[0x9];

 u8         geneve_tlv_option_0_data[0x1];
 u8         geneve_tlv_option_0_exist[0x1];
 u8         reserved_at_42[0x3];
 u8         outer_first_mpls_over_udp[0x4];
 u8         outer_first_mpls_over_gre[0x4];
 u8         inner_first_mpls[0x4];
 u8         outer_first_mpls[0x4];
 u8         reserved_at_55[0x2];
 u8    outer_esp_spi[0x1];
 u8         reserved_at_58[0x2];
 u8         bth_dst_qp[0x1];
 u8         reserved_at_5b[0x5];

 u8         reserved_at_60[0x18];
 u8         metadata_reg_c_7[0x1];
 u8         metadata_reg_c_6[0x1];
 u8         metadata_reg_c_5[0x1];
 u8         metadata_reg_c_4[0x1];
 u8         metadata_reg_c_3[0x1];
 u8         metadata_reg_c_2[0x1];
 u8         metadata_reg_c_1[0x1];
 u8         metadata_reg_c_0[0x1];
};

/* Table 2170 - Flow Table Fields Supported 2 Format */
struct mlx5_ifc_flow_table_fields_supported_2_bits {
 u8         inner_l4_type_ext[0x1];
 u8         outer_l4_type_ext[0x1];
 u8         inner_l4_type[0x1];
 u8         outer_l4_type[0x1];
 u8         reserved_at_4[0xa];
 u8         bth_opcode[0x1];
 u8         reserved_at_f[0x1];
 u8         tunnel_header_0_1[0x1];
 u8         reserved_at_11[0xf];

 u8         reserved_at_20[0xf];
 u8         ipsec_next_header[0x1];
 u8         reserved_at_30[0x10];

 u8         reserved_at_40[0x40];
};

struct mlx5_ifc_flow_table_prop_layout_bits {
 u8         ft_support[0x1];
 u8         reserved_at_1[0x1];
 u8         flow_counter[0x1];
 u8    flow_modify_en[0x1];
 u8         modify_root[0x1];
 u8         identified_miss_table_mode[0x1];
 u8         flow_table_modify[0x1];
 u8         reformat[0x1];
 u8         decap[0x1];
 u8         reset_root_to_default[0x1];
 u8         pop_vlan[0x1];
 u8         push_vlan[0x1];
 u8         reserved_at_c[0x1];
 u8         pop_vlan_2[0x1];
 u8         push_vlan_2[0x1];
 u8    reformat_and_vlan_action[0x1];
 u8    reserved_at_10[0x1];
 u8         sw_owner[0x1];
 u8    reformat_l3_tunnel_to_l2[0x1];
 u8    reformat_l2_to_l3_tunnel[0x1];
 u8    reformat_and_modify_action[0x1];
 u8    ignore_flow_level[0x1];
 u8         reserved_at_16[0x1];
 u8    table_miss_action_domain[0x1];
 u8         termination_table[0x1];
 u8         reformat_and_fwd_to_table[0x1];
 u8         reserved_at_1a[0x2];
 u8         ipsec_encrypt[0x1];
 u8         ipsec_decrypt[0x1];
 u8         sw_owner_v2[0x1];
 u8         reserved_at_1f[0x1];

 u8         termination_table_raw_traffic[0x1];
 u8         reserved_at_21[0x1];
 u8         log_max_ft_size[0x6];
 u8         log_max_modify_header_context[0x8];
 u8         max_modify_header_actions[0x8];
 u8         max_ft_level[0x8];

 u8         reformat_add_esp_trasport[0x1];
 u8         reformat_l2_to_l3_esp_tunnel[0x1];
 u8         reformat_add_esp_transport_over_udp[0x1];
 u8         reformat_del_esp_trasport[0x1];
 u8         reformat_l3_esp_tunnel_to_l2[0x1];
 u8         reformat_del_esp_transport_over_udp[0x1];
 u8         execute_aso[0x1];
 u8         reserved_at_47[0x19];

 u8         reserved_at_60[0x2];
 u8         reformat_insert[0x1];
 u8         reformat_remove[0x1];
 u8         macsec_encrypt[0x1];
 u8         macsec_decrypt[0x1];
 u8         reserved_at_66[0x2];
 u8         reformat_add_macsec[0x1];
 u8         reformat_remove_macsec[0x1];
 u8         reparse[0x1];
 u8         reserved_at_6b[0x1];
 u8         cross_vhca_object[0x1];
 u8         reformat_l2_to_l3_audp_tunnel[0x1];
 u8         reformat_l3_audp_tunnel_to_l2[0x1];
 u8         ignore_flow_level_rtc_valid[0x1];
 u8         reserved_at_70[0x8];
 u8         log_max_ft_num[0x8];

 u8         reserved_at_80[0x10];
 u8         log_max_flow_counter[0x8];
 u8         log_max_destination[0x8];

 u8         reserved_at_a0[0x18];
 u8         log_max_flow[0x8];

 u8         reserved_at_c0[0x40];

 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;

 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
};

struct mlx5_ifc_odp_per_transport_service_cap_bits {
 u8         send[0x1];
 u8         receive[0x1];
 u8         write[0x1];
 u8         read[0x1];
 u8         atomic[0x1];
 u8         srq_receive[0x1];
 u8         reserved_at_6[0x1a];
};

struct mlx5_ifc_ipv4_layout_bits {
 u8         reserved_at_0[0x60];

 u8         ipv4[0x20];
};

struct mlx5_ifc_ipv6_layout_bits {
 u8         ipv6[16][0x8];
};

struct mlx5_ifc_ipv6_simple_layout_bits {
 u8         ipv6_127_96[0x20];
 u8         ipv6_95_64[0x20];
 u8         ipv6_63_32[0x20];
 u8         ipv6_31_0[0x20];
};

union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 u8         reserved_at_0[0x80];
};

enum {
 MLX5_PACKET_L4_TYPE_NONE,
 MLX5_PACKET_L4_TYPE_TCP,
 MLX5_PACKET_L4_TYPE_UDP,
};

enum {
 MLX5_PACKET_L4_TYPE_EXT_NONE,
 MLX5_PACKET_L4_TYPE_EXT_TCP,
 MLX5_PACKET_L4_TYPE_EXT_UDP,
 MLX5_PACKET_L4_TYPE_EXT_ICMP,
};

struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 u8         smac_47_16[0x20];

 u8         smac_15_0[0x10];
 u8         ethertype[0x10];

 u8         dmac_47_16[0x20];

 u8         dmac_15_0[0x10];
 u8         first_prio[0x3];
 u8         first_cfi[0x1];
 u8         first_vid[0xc];

 u8         ip_protocol[0x8];
 u8         ip_dscp[0x6];
 u8         ip_ecn[0x2];
 u8         cvlan_tag[0x1];
 u8         svlan_tag[0x1];
 u8         frag[0x1];
 u8         ip_version[0x4];
 u8         tcp_flags[0x9];

 u8         tcp_sport[0x10];
 u8         tcp_dport[0x10];

 u8         l4_type[0x2];
 u8         l4_type_ext[0x4];
 u8         reserved_at_c6[0xa];
 u8         ipv4_ihl[0x4];
 u8         reserved_at_d4[0x4];
 u8         ttl_hoplimit[0x8];

 u8         udp_sport[0x10];
 u8         udp_dport[0x10];

 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;

 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
};

struct mlx5_ifc_nvgre_key_bits {
 u8 hi[0x18];
 u8 lo[0x8];
};

union mlx5_ifc_gre_key_bits {
 struct mlx5_ifc_nvgre_key_bits nvgre;
 u8 key[0x20];
};

struct mlx5_ifc_fte_match_set_misc_bits {
 u8         gre_c_present[0x1];
 u8         reserved_at_1[0x1];
 u8         gre_k_present[0x1];
 u8         gre_s_present[0x1];
 u8         source_vhca_port[0x4];
 u8         source_sqn[0x18];

 u8         source_eswitch_owner_vhca_id[0x10];
 u8         source_port[0x10];

 u8         outer_second_prio[0x3];
 u8         outer_second_cfi[0x1];
 u8         outer_second_vid[0xc];
 u8         inner_second_prio[0x3];
 u8         inner_second_cfi[0x1];
 u8         inner_second_vid[0xc];

 u8         outer_second_cvlan_tag[0x1];
 u8         inner_second_cvlan_tag[0x1];
 u8         outer_second_svlan_tag[0x1];
 u8         inner_second_svlan_tag[0x1];
 u8         reserved_at_64[0xc];
 u8         gre_protocol[0x10];

 union mlx5_ifc_gre_key_bits gre_key;

 u8         vxlan_vni[0x18];
 u8         bth_opcode[0x8];

 u8         geneve_vni[0x18];
 u8         reserved_at_d8[0x6];
 u8         geneve_tlv_option_0_exist[0x1];
 u8         geneve_oam[0x1];

 u8         reserved_at_e0[0xc];
 u8         outer_ipv6_flow_label[0x14];

 u8         reserved_at_100[0xc];
 u8         inner_ipv6_flow_label[0x14];

 u8         reserved_at_120[0xa];
 u8         geneve_opt_len[0x6];
 u8         geneve_protocol_type[0x10];

 u8         reserved_at_140[0x8];
 u8         bth_dst_qp[0x18];
 u8    inner_esp_spi[0x20];
 u8    outer_esp_spi[0x20];
 u8         reserved_at_1a0[0x60];
};

struct mlx5_ifc_fte_match_mpls_bits {
 u8         mpls_label[0x14];
 u8         mpls_exp[0x3];
 u8         mpls_s_bos[0x1];
 u8         mpls_ttl[0x8];
};

struct mlx5_ifc_fte_match_set_misc2_bits {
 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;

 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;

 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;

 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;

 u8         metadata_reg_c_7[0x20];

 u8         metadata_reg_c_6[0x20];

 u8         metadata_reg_c_5[0x20];

 u8         metadata_reg_c_4[0x20];

 u8         metadata_reg_c_3[0x20];

 u8         metadata_reg_c_2[0x20];

 u8         metadata_reg_c_1[0x20];

 u8         metadata_reg_c_0[0x20];

 u8         metadata_reg_a[0x20];

 u8         reserved_at_1a0[0x8];
 u8         macsec_syndrome[0x8];
 u8         ipsec_syndrome[0x8];
 u8         ipsec_next_header[0x8];

 u8         reserved_at_1c0[0x40];
};

struct mlx5_ifc_fte_match_set_misc3_bits {
 u8         inner_tcp_seq_num[0x20];

 u8         outer_tcp_seq_num[0x20];

 u8         inner_tcp_ack_num[0x20];

 u8         outer_tcp_ack_num[0x20];

 u8    reserved_at_80[0x8];
 u8         outer_vxlan_gpe_vni[0x18];

 u8         outer_vxlan_gpe_next_protocol[0x8];
 u8         outer_vxlan_gpe_flags[0x8];
 u8    reserved_at_b0[0x10];

 u8    icmp_header_data[0x20];

 u8    icmpv6_header_data[0x20];

 u8    icmp_type[0x8];
 u8    icmp_code[0x8];
 u8    icmpv6_type[0x8];
 u8    icmpv6_code[0x8];

 u8         geneve_tlv_option_0_data[0x20];

 u8    gtpu_teid[0x20];

 u8    gtpu_msg_type[0x8];
 u8    gtpu_msg_flags[0x8];
 u8    reserved_at_170[0x10];

 u8    gtpu_dw_2[0x20];

 u8    gtpu_first_ext_dw_0[0x20];

 u8    gtpu_dw_0[0x20];

 u8    reserved_at_1e0[0x20];
};

struct mlx5_ifc_fte_match_set_misc4_bits {
 u8         prog_sample_field_value_0[0x20];

 u8         prog_sample_field_id_0[0x20];

 u8         prog_sample_field_value_1[0x20];

 u8         prog_sample_field_id_1[0x20];

 u8         prog_sample_field_value_2[0x20];

 u8         prog_sample_field_id_2[0x20];

 u8         prog_sample_field_value_3[0x20];

 u8         prog_sample_field_id_3[0x20];

 u8         reserved_at_100[0x100];
};

struct mlx5_ifc_fte_match_set_misc5_bits {
 u8         macsec_tag_0[0x20];

 u8         macsec_tag_1[0x20];

 u8         macsec_tag_2[0x20];

 u8         macsec_tag_3[0x20];

 u8         tunnel_header_0[0x20];

 u8         tunnel_header_1[0x20];

 u8         tunnel_header_2[0x20];

 u8         tunnel_header_3[0x20];

 u8         reserved_at_100[0x100];
};

struct mlx5_ifc_cmd_pas_bits {
 u8         pa_h[0x20];

 u8         pa_l[0x14];
 u8         reserved_at_34[0xc];
};

struct mlx5_ifc_uint64_bits {
 u8         hi[0x20];

 u8         lo[0x20];
};

enum {
 MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
};

struct mlx5_ifc_ads_bits {
 u8         fl[0x1];
 u8         free_ar[0x1];
 u8         reserved_at_2[0xe];
 u8         pkey_index[0x10];

 u8         plane_index[0x8];
 u8         grh[0x1];
 u8         mlid[0x7];
 u8         rlid[0x10];

 u8         ack_timeout[0x5];
 u8         reserved_at_45[0x3];
 u8         src_addr_index[0x8];
 u8         reserved_at_50[0x4];
 u8         stat_rate[0x4];
 u8         hop_limit[0x8];

 u8         reserved_at_60[0x4];
 u8         tclass[0x8];
 u8         flow_label[0x14];

 u8         rgid_rip[16][0x8];

 u8         reserved_at_100[0x4];
 u8         f_dscp[0x1];
 u8         f_ecn[0x1];
 u8         reserved_at_106[0x1];
 u8         f_eth_prio[0x1];
 u8         ecn[0x2];
 u8         dscp[0x6];
 u8         udp_sport[0x10];

 u8         dei_cfi[0x1];
 u8         eth_prio[0x3];
 u8         sl[0x4];
 u8         vhca_port_num[0x8];
 u8         rmac_47_32[0x10];

 u8         rmac_31_0[0x20];
};

struct mlx5_ifc_flow_table_nic_cap_bits {
 u8         nic_rx_multi_path_tirs[0x1];
 u8         nic_rx_multi_path_tirs_fts[0x1];
 u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 u8    reserved_at_3[0x4];
 u8    sw_owner_reformat_supported[0x1];
 u8    reserved_at_8[0x18];

 u8    encap_general_header[0x1];
 u8    reserved_at_21[0xa];
 u8    log_max_packet_reformat_context[0x5];
 u8    reserved_at_30[0x6];
 u8    max_encap_header_size[0xa];
 u8    reserved_at_40[0x1c0];

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;

 u8         reserved_at_e00[0x600];

 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;

 u8         reserved_at_1480[0x80];

 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;

 u8         reserved_at_1580[0x280];

 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;

 u8         reserved_at_1880[0x780];

 u8         sw_steering_nic_rx_action_drop_icm_address[0x40];

 u8         sw_steering_nic_tx_action_drop_icm_address[0x40];

 u8         sw_steering_nic_tx_action_allow_icm_address[0x40];

 u8         reserved_at_20c0[0x5f40];
};

struct mlx5_ifc_port_selection_cap_bits {
 u8         reserved_at_0[0x10];
 u8         port_select_flow_table[0x1];
 u8         reserved_at_11[0x1];
 u8         port_select_flow_table_bypass[0x1];
 u8         reserved_at_13[0xd];

 u8         reserved_at_20[0x1e0];

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;

 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;

 u8         reserved_at_480[0x7b80];
};

enum {
 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
};

struct mlx5_ifc_flow_table_eswitch_cap_bits {
 u8      fdb_to_vport_reg_c_id[0x8];
 u8      reserved_at_8[0x5];
 u8      fdb_uplink_hairpin[0x1];
 u8      fdb_multi_path_any_table_limit_regc[0x1];
 u8      reserved_at_f[0x1];
 u8      fdb_dynamic_tunnel[0x1];
 u8      reserved_at_11[0x1];
 u8      fdb_multi_path_any_table[0x1];
 u8      reserved_at_13[0x2];
 u8      fdb_modify_header_fwd_to_table[0x1];
 u8      fdb_ipv4_ttl_modify[0x1];
 u8      flow_source[0x1];
 u8      reserved_at_18[0x2];
 u8      multi_fdb_encap[0x1];
 u8      egress_acl_forward_to_vport[0x1];
 u8      fdb_multi_path_to_table[0x1];
 u8      reserved_at_1d[0x3];

 u8      reserved_at_20[0x1e0];

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;

 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;

 u8      reserved_at_800[0xC00];

 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;

 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;

 u8      reserved_at_1500[0x300];

 u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];

 u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];

 u8      sw_steering_uplink_icm_address_rx[0x40];

 u8      sw_steering_uplink_icm_address_tx[0x40];

 u8      reserved_at_1900[0x6700];
};

struct mlx5_ifc_wqe_based_flow_table_cap_bits {
 u8         reserved_at_0[0x3];
 u8         log_max_num_ste[0x5];
 u8         reserved_at_8[0x3];
 u8         log_max_num_stc[0x5];
 u8         reserved_at_10[0x3];
 u8         log_max_num_rtc[0x5];
 u8         reserved_at_18[0x3];
 u8         log_max_num_header_modify_pattern[0x5];

 u8         rtc_hash_split_table[0x1];
 u8         rtc_linear_lookup_table[0x1];
 u8         reserved_at_22[0x1];
 u8         stc_alloc_log_granularity[0x5];
 u8         reserved_at_28[0x3];
 u8         stc_alloc_log_max[0x5];
 u8         reserved_at_30[0x3];
 u8         ste_alloc_log_granularity[0x5];
 u8         reserved_at_38[0x3];
 u8         ste_alloc_log_max[0x5];

 u8         reserved_at_40[0xb];
 u8         rtc_reparse_mode[0x5];
 u8         reserved_at_50[0x3];
 u8         rtc_index_mode[0x5];
 u8         reserved_at_58[0x3];
 u8         rtc_log_depth_max[0x5];

 u8         reserved_at_60[0x10];
 u8         ste_format[0x10];

 u8         stc_action_type[0x80];

 u8         header_insert_type[0x10];
 u8         header_remove_type[0x10];

 u8         trivial_match_definer[0x20];

 u8         reserved_at_140[0x1b];
 u8         rtc_max_num_hash_definer_gen_wqe[0x5];

 u8         reserved_at_160[0x18];
 u8         access_index_mode[0x8];

 u8         reserved_at_180[0x10];
 u8         ste_format_gen_wqe[0x10];

 u8         linear_match_definer_reg_c3[0x20];

 u8         fdb_jump_to_tir_stc[0x1];
 u8         reserved_at_1c1[0x1f];
};

struct mlx5_ifc_esw_cap_bits {
 u8         reserved_at_0[0x1d];
 u8         merged_eswitch[0x1];
 u8         reserved_at_1e[0x2];

 u8         reserved_at_20[0x40];

 u8         esw_manager_vport_number_valid[0x1];
 u8         reserved_at_61[0xf];
 u8         esw_manager_vport_number[0x10];

 u8         reserved_at_80[0x780];
};

enum {
 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
};

struct mlx5_ifc_e_switch_cap_bits {
 u8         vport_svlan_strip[0x1];
 u8         vport_cvlan_strip[0x1];
 u8         vport_svlan_insert[0x1];
 u8         vport_cvlan_insert_if_not_exist[0x1];
 u8         vport_cvlan_insert_overwrite[0x1];
 u8         reserved_at_5[0x1];
 u8         vport_cvlan_insert_always[0x1];
 u8         esw_shared_ingress_acl[0x1];
 u8         esw_uplink_ingress_acl[0x1];
 u8         root_ft_on_other_esw[0x1];
 u8         reserved_at_a[0xf];
 u8         esw_functions_changed[0x1];
 u8         reserved_at_1a[0x1];
 u8         ecpf_vport_exists[0x1];
 u8         counter_eswitch_affinity[0x1];
 u8         merged_eswitch[0x1];
 u8         nic_vport_node_guid_modify[0x1];
 u8         nic_vport_port_guid_modify[0x1];

 u8         vxlan_encap_decap[0x1];
 u8         nvgre_encap_decap[0x1];
 u8         reserved_at_22[0x1];
 u8         log_max_fdb_encap_uplink[0x5];
 u8         reserved_at_21[0x3];
 u8         log_max_packet_reformat_context[0x5];
 u8         reserved_2b[0x6];
 u8         max_encap_header_size[0xa];

 u8         reserved_at_40[0xb];
 u8         log_max_esw_sf[0x5];
 u8         esw_sf_base_id[0x10];

 u8         reserved_at_60[0x7a0];

};

struct mlx5_ifc_qos_cap_bits {
 u8         packet_pacing[0x1];
 u8         esw_scheduling[0x1];
 u8         esw_bw_share[0x1];
 u8         esw_rate_limit[0x1];
 u8         reserved_at_4[0x1];
 u8         packet_pacing_burst_bound[0x1];
 u8         packet_pacing_typical_size[0x1];
 u8         reserved_at_7[0x1];
 u8         nic_sq_scheduling[0x1];
 u8         nic_bw_share[0x1];
 u8         nic_rate_limit[0x1];
 u8         packet_pacing_uid[0x1];
 u8         log_esw_max_sched_depth[0x4];
 u8         reserved_at_10[0x10];

 u8         reserved_at_20[0x9];
 u8         esw_cross_esw_sched[0x1];
 u8         reserved_at_2a[0x1];
 u8         log_max_qos_nic_queue_group[0x5];
 u8         reserved_at_30[0x10];

 u8         packet_pacing_max_rate[0x20];

 u8         packet_pacing_min_rate[0x20];

 u8         reserved_at_80[0xb];
 u8         log_esw_max_rate_limit[0x5];
 u8         packet_pacing_rate_table_size[0x10];

 u8         esw_element_type[0x10];
 u8         esw_tsar_type[0x10];

 u8         reserved_at_c0[0x10];
 u8         max_qos_para_vport[0x10];

 u8         max_tsar_bw_share[0x20];

 u8         nic_element_type[0x10];
 u8         nic_tsar_type[0x10];

 u8         reserved_at_120[0x3];
 u8         log_meter_aso_granularity[0x5];
 u8         reserved_at_128[0x3];
 u8         log_meter_aso_max_alloc[0x5];
 u8         reserved_at_130[0x3];
 u8         log_max_num_meter_aso[0x5];
 u8         reserved_at_138[0x8];

 u8         reserved_at_140[0x6c0];
};

struct mlx5_ifc_debug_cap_bits {
 u8         core_dump_general[0x1];
 u8         core_dump_qp[0x1];
 u8         reserved_at_2[0x7];
 u8         resource_dump[0x1];
 u8         reserved_at_a[0x16];

 u8         reserved_at_20[0x2];
 u8         stall_detect[0x1];
 u8         reserved_at_23[0x1d];

 u8         reserved_at_40[0x7c0];
};

struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 u8         csum_cap[0x1];
 u8         vlan_cap[0x1];
 u8         lro_cap[0x1];
 u8         lro_psh_flag[0x1];
 u8         lro_time_stamp[0x1];
 u8         reserved_at_5[0x2];
 u8         wqe_vlan_insert[0x1];
 u8         self_lb_en_modifiable[0x1];
 u8         reserved_at_9[0x2];
 u8         max_lso_cap[0x5];
 u8         multi_pkt_send_wqe[0x2];
 u8    wqe_inline_mode[0x2];
 u8         rss_ind_tbl_cap[0x4];
 u8         reg_umr_sq[0x1];
 u8         scatter_fcs[0x1];
 u8         enhanced_multi_pkt_send_wqe[0x1];
 u8         tunnel_lso_const_out_ip_id[0x1];
 u8         tunnel_lro_gre[0x1];
 u8         tunnel_lro_vxlan[0x1];
 u8         tunnel_stateless_gre[0x1];
 u8         tunnel_stateless_vxlan[0x1];

 u8         swp[0x1];
 u8         swp_csum[0x1];
 u8         swp_lso[0x1];
 u8         cqe_checksum_full[0x1];
 u8         tunnel_stateless_geneve_tx[0x1];
 u8         tunnel_stateless_mpls_over_udp[0x1];
 u8         tunnel_stateless_mpls_over_gre[0x1];
 u8         tunnel_stateless_vxlan_gpe[0x1];
 u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 u8         tunnel_stateless_ip_over_ip[0x1];
 u8         insert_trailer[0x1];
 u8         reserved_at_2b[0x1];
 u8         tunnel_stateless_ip_over_ip_rx[0x1];
 u8         tunnel_stateless_ip_over_ip_tx[0x1];
 u8         reserved_at_2e[0x2];
 u8         max_vxlan_udp_ports[0x8];
 u8         swp_csum_l4_partial[0x1];
 u8         reserved_at_39[0x5];
 u8         max_geneve_opt_len[0x1];
 u8         tunnel_stateless_geneve_rx[0x1];

 u8         reserved_at_40[0x10];
 u8         lro_min_mss_size[0x10];

 u8         reserved_at_60[0x120];

 u8         lro_timer_supported_periods[4][0x20];

 u8         reserved_at_200[0x600];
};

enum {
 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
};

struct mlx5_ifc_roce_cap_bits {
 u8         roce_apm[0x1];
 u8         reserved_at_1[0x3];
 u8         sw_r_roce_src_udp_port[0x1];
 u8         fl_rc_qp_when_roce_disabled[0x1];
 u8         fl_rc_qp_when_roce_enabled[0x1];
 u8         roce_cc_general[0x1];
 u8    qp_ooo_transmit_default[0x1];
 u8         reserved_at_9[0x15];
 u8    qp_ts_format[0x2];

 u8         reserved_at_20[0x60];

 u8         reserved_at_80[0xc];
 u8         l3_type[0x4];
 u8         reserved_at_90[0x8];
 u8         roce_version[0x8];

 u8         reserved_at_a0[0x10];
 u8         r_roce_dest_udp_port[0x10];

 u8         r_roce_max_src_udp_port[0x10];
 u8         r_roce_min_src_udp_port[0x10];

 u8         reserved_at_e0[0x10];
 u8         roce_address_table_size[0x10];

 u8         reserved_at_100[0x700];
};

struct mlx5_ifc_sync_steering_in_bits {
 u8         opcode[0x10];
 u8         uid[0x10];

 u8         reserved_at_20[0x10];
 u8         op_mod[0x10];

 u8         reserved_at_40[0xc0];
};

struct mlx5_ifc_sync_steering_out_bits {
 u8         status[0x8];
 u8         reserved_at_8[0x18];

 u8         syndrome[0x20];

 u8         reserved_at_40[0x40];
};

struct mlx5_ifc_sync_crypto_in_bits {
 u8         opcode[0x10];
 u8         uid[0x10];

 u8         reserved_at_20[0x10];
 u8         op_mod[0x10];

 u8         reserved_at_40[0x20];

 u8         reserved_at_60[0x10];
 u8         crypto_type[0x10];

 u8         reserved_at_80[0x80];
};

struct mlx5_ifc_sync_crypto_out_bits {
 u8         status[0x8];
 u8         reserved_at_8[0x18];

 u8         syndrome[0x20];

 u8         reserved_at_40[0x40];
};

struct mlx5_ifc_device_mem_cap_bits {
 u8         memic[0x1];
 u8         reserved_at_1[0x1f];

 u8         reserved_at_20[0xb];
 u8         log_min_memic_alloc_size[0x5];
 u8         reserved_at_30[0x8];
 u8    log_max_memic_addr_alignment[0x8];

 u8         memic_bar_start_addr[0x40];

 u8         memic_bar_size[0x20];

 u8         max_memic_size[0x20];

 u8         steering_sw_icm_start_address[0x40];

 u8         reserved_at_100[0x8];
 u8         log_header_modify_sw_icm_size[0x8];
 u8         reserved_at_110[0x2];
 u8         log_sw_icm_alloc_granularity[0x6];
 u8         log_steering_sw_icm_size[0x8];

 u8         log_indirect_encap_sw_icm_size[0x8];
 u8         reserved_at_128[0x10];
 u8         log_header_modify_pattern_sw_icm_size[0x8];

 u8         header_modify_sw_icm_start_address[0x40];

 u8         reserved_at_180[0x40];

 u8         header_modify_pattern_sw_icm_start_address[0x40];

 u8         memic_operations[0x20];

 u8         reserved_at_220[0x20];

 u8         indirect_encap_sw_icm_start_address[0x40];

 u8         reserved_at_280[0x580];
};

struct mlx5_ifc_device_event_cap_bits {
 u8         user_affiliated_events[4][0x40];

 u8         user_unaffiliated_events[4][0x40];
};

struct mlx5_ifc_virtio_emulation_cap_bits {
 u8         desc_tunnel_offload_type[0x1];
 u8         eth_frame_offload_type[0x1];
 u8         virtio_version_1_0[0x1];
 u8         device_features_bits_mask[0xd];
 u8         event_mode[0x8];
 u8         virtio_queue_type[0x8];

 u8         max_tunnel_desc[0x10];
 u8         reserved_at_30[0x3];
 u8         log_doorbell_stride[0x5];
 u8         reserved_at_38[0x3];
 u8         log_doorbell_bar_size[0x5];

 u8         doorbell_bar_offset[0x40];

 u8         max_emulated_devices[0x8];
 u8         max_num_virtio_queues[0x18];

 u8         reserved_at_a0[0x20];

 u8    reserved_at_c0[0x13];
 u8         desc_group_mkey_supported[0x1];
 u8         freeze_to_rdy_supported[0x1];
 u8         reserved_at_d5[0xb];

 u8         reserved_at_e0[0x20];

 u8         umem_1_buffer_param_a[0x20];

 u8         umem_1_buffer_param_b[0x20];

 u8         umem_2_buffer_param_a[0x20];

 u8         umem_2_buffer_param_b[0x20];

 u8         umem_3_buffer_param_a[0x20];

 u8         umem_3_buffer_param_b[0x20];

 u8         reserved_at_1c0[0x640];
};

enum {
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
};

enum {
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
};

struct mlx5_ifc_atomic_caps_bits {
 u8         reserved_at_0[0x40];

 u8         atomic_req_8B_endianness_mode[0x2];
 u8         reserved_at_42[0x4];
 u8         supported_atomic_req_8B_endianness_mode_1[0x1];

 u8         reserved_at_47[0x19];

 u8         reserved_at_60[0x20];

 u8         reserved_at_80[0x10];
 u8         atomic_operations[0x10];

 u8         reserved_at_a0[0x10];
 u8         atomic_size_qp[0x10];

 u8         reserved_at_c0[0x10];
 u8         atomic_size_dc[0x10];

 u8         reserved_at_e0[0x720];
};

struct mlx5_ifc_odp_scheme_cap_bits {
 u8         reserved_at_0[0x40];

 u8         sig[0x1];
 u8         reserved_at_41[0x4];
 u8         page_prefetch[0x1];
 u8         reserved_at_46[0x1a];

 u8         reserved_at_60[0x20];

 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;

 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;

 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;

 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;

 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;

 u8         reserved_at_120[0xe0];
};

struct mlx5_ifc_odp_cap_bits {
 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;

 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;

 u8         reserved_at_400[0x200];

 u8         mem_page_fault[0x1];
 u8         reserved_at_601[0x1f];

 u8         reserved_at_620[0x1e0];
};

struct mlx5_ifc_tls_cap_bits {
 u8         tls_1_2_aes_gcm_128[0x1];
 u8         tls_1_3_aes_gcm_128[0x1];
 u8         tls_1_2_aes_gcm_256[0x1];
 u8         tls_1_3_aes_gcm_256[0x1];
 u8         reserved_at_4[0x1c];

 u8         reserved_at_20[0x7e0];
};

struct mlx5_ifc_ipsec_cap_bits {
 u8         ipsec_full_offload[0x1];
 u8         ipsec_crypto_offload[0x1];
 u8         ipsec_esn[0x1];
 u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
 u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
 u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
 u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
 u8         reserved_at_7[0x4];
 u8         log_max_ipsec_offload[0x5];
 u8         reserved_at_10[0x10];

 u8         min_log_ipsec_full_replay_window[0x8];
 u8         max_log_ipsec_full_replay_window[0x8];
 u8         reserved_at_30[0x7d0];
};

struct mlx5_ifc_macsec_cap_bits {
 u8    macsec_epn[0x1];
 u8    reserved_at_1[0x2];
 u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
 u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
 u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
 u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
 u8    reserved_at_7[0x4];
 u8    log_max_macsec_offload[0x5];
 u8    reserved_at_10[0x10];

 u8    min_log_macsec_full_replay_window[0x8];
 u8    max_log_macsec_full_replay_window[0x8];
 u8    reserved_at_30[0x10];

 u8    reserved_at_40[0x7c0];
};

enum {
 MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 MLX5_WQ_TYPE_CYCLIC       = 0x1,
 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
};

enum {
 MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
};

enum {
 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
};

enum {
 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
};

enum {
 MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
};

enum {
 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
};

enum {
 MLX5_CAP_PORT_TYPE_IB  = 0x0,
 MLX5_CAP_PORT_TYPE_ETH = 0x1,
};

enum {
 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
 MLX5_CAP_UMR_FENCE_NONE  = 0x2,
};

enum {
 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0,
 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1,
 MLX5_FLEX_IPV6_OVER_IP_ENABLED  = 1 << 2,
 MLX5_FLEX_PARSER_GENEVE_ENABLED  = 1 << 3,
 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6,
 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
 MLX5_FLEX_PARSER_GTPU_ENABLED  = 1 << 11,
 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
};

enum {
 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3,
 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4,
};

#define MLX5_FC_BULK_SIZE_FACTOR 128

enum mlx5_fc_bulk_alloc_bitmask {
 MLX5_FC_BULK_128   = (1 << 0),
 MLX5_FC_BULK_256   = (1 << 1),
 MLX5_FC_BULK_512   = (1 << 2),
 MLX5_FC_BULK_1024  = (1 << 3),
 MLX5_FC_BULK_2048  = (1 << 4),
 MLX5_FC_BULK_4096  = (1 << 5),
 MLX5_FC_BULK_8192  = (1 << 6),
 MLX5_FC_BULK_16384 = (1 << 7),
};

#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))

#define MLX5_FT_MAX_MULTIPATH_LEVEL 63

enum {
 MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
 MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
 MLX5_STEERING_FORMAT_CONNECTX_8   = 3,
};

struct mlx5_ifc_cmd_hca_cap_bits {
 u8         reserved_at_0[0x6];
 u8         page_request_disable[0x1];
 u8         abs_native_port_num[0x1];
 u8         reserved_at_8[0x8];
 u8         shared_object_to_user_object_allowed[0x1];
 u8         reserved_at_13[0xe];
 u8         vhca_resource_manager[0x1];

 u8         hca_cap_2[0x1];
 u8         create_lag_when_not_master_up[0x1];
 u8         dtor[0x1];
 u8         event_on_vhca_state_teardown_request[0x1];
 u8         event_on_vhca_state_in_use[0x1];
 u8         event_on_vhca_state_active[0x1];
 u8         event_on_vhca_state_allocated[0x1];
 u8         event_on_vhca_state_invalid[0x1];
 u8         reserved_at_28[0x8];
 u8         vhca_id[0x10];

 u8         reserved_at_40[0x40];

 u8         log_max_srq_sz[0x8];
 u8         log_max_qp_sz[0x8];
 u8         event_cap[0x1];
 u8         reserved_at_91[0x2];
 u8         isolate_vl_tc_new[0x1];
 u8         reserved_at_94[0x4];
 u8         prio_tag_required[0x1];
 u8         reserved_at_99[0x2];
 u8         log_max_qp[0x5];

 u8         reserved_at_a0[0x3];
 u8    ece_support[0x1];
 u8    reserved_at_a4[0x5];
 u8         reg_c_preserve[0x1];
 u8         reserved_at_aa[0x1];
 u8         log_max_srq[0x5];
 u8         reserved_at_b0[0x1];
 u8         uplink_follow[0x1];
 u8         ts_cqe_to_dest_cqn[0x1];
 u8         reserved_at_b3[0x6];
 u8         go_back_n[0x1];
 u8         reserved_at_ba[0x6];

 u8         max_sgl_for_optimized_performance[0x8];
 u8         log_max_cq_sz[0x8];
 u8         relaxed_ordering_write_umr[0x1];
 u8         relaxed_ordering_read_umr[0x1];
 u8         reserved_at_d2[0x7];
 u8         virtio_net_device_emualtion_manager[0x1];
 u8         virtio_blk_device_emualtion_manager[0x1];
 u8         log_max_cq[0x5];

 u8         log_max_eq_sz[0x8];
 u8         relaxed_ordering_write[0x1];
 u8         relaxed_ordering_read_pci_enabled[0x1];
 u8         log_max_mkey[0x6];
 u8         reserved_at_f0[0x6];
 u8    terminate_scatter_list_mkey[0x1];
 u8    repeated_mkey[0x1];
 u8         dump_fill_mkey[0x1];
 u8         reserved_at_f9[0x2];
 u8         fast_teardown[0x1];
 u8         log_max_eq[0x4];

 u8         max_indirection[0x8];
 u8         fixed_buffer_size[0x1];
 u8         log_max_mrw_sz[0x7];
 u8         force_teardown[0x1];
 u8         reserved_at_111[0x1];
 u8         log_max_bsf_list_size[0x6];
 u8         umr_extended_translation_offset[0x1];
 u8         null_mkey[0x1];
 u8         log_max_klm_list_size[0x6];

 u8         reserved_at_120[0x2];
 u8    qpc_extension[0x1];
 u8    reserved_at_123[0x7];
 u8         log_max_ra_req_dc[0x6];
 u8         reserved_at_130[0x2];
 u8         eth_wqe_too_small[0x1];
 u8         reserved_at_133[0x6];
 u8         vnic_env_cq_overrun[0x1];
 u8         log_max_ra_res_dc[0x6];

 u8         reserved_at_140[0x5];
 u8         release_all_pages[0x1];
 u8         must_not_use[0x1];
 u8         reserved_at_147[0x2];
 u8         roce_accl[0x1];
 u8         log_max_ra_req_qp[0x6];
 u8         reserved_at_150[0xa];
 u8         log_max_ra_res_qp[0x6];

 u8         end_pad[0x1];
 u8         cc_query_allowed[0x1];
 u8         cc_modify_allowed[0x1];
 u8         start_pad[0x1];
 u8         cache_line_128byte[0x1];
 u8         reserved_at_165[0x4];
 u8         rts2rts_qp_counters_set_id[0x1];
 u8         reserved_at_16a[0x2];
 u8         vnic_env_int_rq_oob[0x1];
 u8         sbcam_reg[0x1];
 u8         reserved_at_16e[0x1];
 u8         qcam_reg[0x1];
 u8         gid_table_size[0x10];

 u8         out_of_seq_cnt[0x1];
 u8         vport_counters[0x1];
 u8         retransmission_q_counters[0x1];
 u8         debug[0x1];
 u8         modify_rq_counter_set_id[0x1];
 u8         rq_delay_drop[0x1];
 u8         max_qp_cnt[0xa];
 u8         pkey_table_size[0x10];

 u8         vport_group_manager[0x1];
 u8         vhca_group_manager[0x1];
 u8         ib_virt[0x1];
 u8         eth_virt[0x1];
 u8         vnic_env_queue_counters[0x1];
 u8         ets[0x1];
 u8         nic_flow_table[0x1];
 u8         eswitch_manager[0x1];
 u8         device_memory[0x1];
 u8         mcam_reg[0x1];
 u8         pcam_reg[0x1];
 u8         local_ca_ack_delay[0x5];
 u8         port_module_event[0x1];
 u8         enhanced_error_q_counters[0x1];
 u8         ports_check[0x1];
 u8         reserved_at_1b3[0x1];
 u8         disable_link_up[0x1];
 u8         beacon_led[0x1];
 u8         port_type[0x2];
 u8         num_ports[0x8];

 u8         reserved_at_1c0[0x1];
 u8         pps[0x1];
 u8         pps_modify[0x1];
 u8         log_max_msg[0x5];
 u8         reserved_at_1c8[0x4];
 u8         max_tc[0x4];
 u8         temp_warn_event[0x1];
 u8         dcbx[0x1];
 u8         general_notification_event[0x1];
 u8         reserved_at_1d3[0x2];
 u8         fpga[0x1];
 u8         rol_s[0x1];
 u8         rol_g[0x1];
 u8         reserved_at_1d8[0x1];
 u8         wol_s[0x1];
 u8         wol_g[0x1];
 u8         wol_a[0x1];
 u8         wol_b[0x1];
 u8         wol_m[0x1];
 u8         wol_u[0x1];
 u8         wol_p[0x1];

 u8         stat_rate_support[0x10];
 u8         reserved_at_1f0[0x1];
 u8         pci_sync_for_fw_update_event[0x1];
 u8         reserved_at_1f2[0x6];
 u8         init2_lag_tx_port_affinity[0x1];
 u8         reserved_at_1fa[0x2];
 u8         wqe_based_flow_table_update_cap[0x1];
 u8         cqe_version[0x4];

 u8         compact_address_vector[0x1];
 u8         striding_rq[0x1];
 u8         reserved_at_202[0x1];
 u8         ipoib_enhanced_offloads[0x1];
 u8         ipoib_basic_offloads[0x1];
 u8         reserved_at_205[0x1];
 u8         repeated_block_disabled[0x1];
 u8         umr_modify_entity_size_disabled[0x1];
 u8         umr_modify_atomic_disabled[0x1];
 u8         umr_indirect_mkey_disabled[0x1];
 u8         umr_fence[0x2];
 u8         dc_req_scat_data_cqe[0x1];
 u8         reserved_at_20d[0x2];
 u8         drain_sigerr[0x1];
 u8         cmdif_checksum[0x2];
 u8         sigerr_cqe[0x1];
 u8         reserved_at_213[0x1];
 u8         wq_signature[0x1];
 u8         sctr_data_cqe[0x1];
 u8         reserved_at_216[0x1];
 u8         sho[0x1];
 u8         tph[0x1];
 u8         rf[0x1];
 u8         dct[0x1];
 u8         qos[0x1];
 u8         eth_net_offloads[0x1];
 u8         roce[0x1];
 u8         atomic[0x1];
 u8         reserved_at_21f[0x1];

 u8         cq_oi[0x1];
 u8         cq_resize[0x1];
 u8         cq_moderation[0x1];
 u8         cq_period_mode_modify[0x1];
 u8         reserved_at_224[0x2];
 u8         cq_eq_remap[0x1];
 u8         pg[0x1];
 u8         block_lb_mc[0x1];
 u8         reserved_at_229[0x1];
 u8         scqe_break_moderation[0x1];
 u8         cq_period_start_from_cqe[0x1];
 u8         cd[0x1];
 u8         reserved_at_22d[0x1];
 u8         apm[0x1];
 u8         vector_calc[0x1];
 u8         umr_ptr_rlky[0x1];
 u8    imaicl[0x1];
 u8    qp_packet_based[0x1];
 u8         reserved_at_233[0x3];
 u8         qkv[0x1];
 u8         pkv[0x1];
 u8         set_deth_sqpn[0x1];
 u8         reserved_at_239[0x3];
 u8         xrc[0x1];
 u8         ud[0x1];
 u8         uc[0x1];
 u8         rc[0x1];

 u8         uar_4k[0x1];
 u8         reserved_at_241[0x7];
 u8         fl_rc_qp_when_roce_disabled[0x1];
 u8         regexp_params[0x1];
 u8         uar_sz[0x6];
 u8         port_selection_cap[0x1];
 u8         nic_cap_reg[0x1];
 u8         umem_uid_0[0x1];
 u8         reserved_at_253[0x5];
 u8         log_pg_sz[0x8];

 u8         bf[0x1];
 u8         driver_version[0x1];
 u8         pad_tx_eth_packet[0x1];
 u8         reserved_at_263[0x3];
 u8         mkey_by_name[0x1];
 u8         reserved_at_267[0x4];

 u8         log_bf_reg_size[0x5];

 u8         disciplined_fr_counter[0x1];
 u8         reserved_at_271[0x2];
 u8    qp_error_syndrome[0x1];
 u8    reserved_at_274[0x2];
 u8         lag_dct[0x2];
 u8         lag_tx_port_affinity[0x1];
 u8         lag_native_fdb_selection[0x1];
 u8         reserved_at_27a[0x1];
 u8         lag_master[0x1];
 u8         num_lag_ports[0x4];

 u8         reserved_at_280[0x10];
 u8         max_wqe_sz_sq[0x10];

 u8         reserved_at_2a0[0x7];
 u8         mkey_pcie_tph[0x1];
 u8         reserved_at_2a8[0x3];
 u8         shampo[0x1];
 u8         reserved_at_2ac[0x4];
 u8         max_wqe_sz_rq[0x10];

 u8         max_flow_counter_31_16[0x10];
 u8         max_wqe_sz_sq_dc[0x10];

 u8         reserved_at_2e0[0x7];
 u8         max_qp_mcg[0x19];

 u8         reserved_at_300[0x10];
 u8         flow_counter_bulk_alloc[0x8];
 u8         log_max_mcg[0x8];

 u8         reserved_at_320[0x3];
 u8         log_max_transport_domain[0x5];
 u8         reserved_at_328[0x2];
 u8    relaxed_ordering_read[0x1];
 u8         log_max_pd[0x5];
 u8         dp_ordering_ooo_all_ud[0x1];
 u8         dp_ordering_ooo_all_uc[0x1];
 u8         dp_ordering_ooo_all_xrc[0x1];
 u8         dp_ordering_ooo_all_dc[0x1];
 u8         dp_ordering_ooo_all_rc[0x1];
 u8         pcie_reset_using_hotreset_method[0x1];
 u8         pci_sync_for_fw_update_with_driver_unload[0x1];
 u8         vnic_env_cnt_steering_fail[0x1];
 u8         vport_counter_local_loopback[0x1];
 u8         q_counter_aggregation[0x1];
 u8         q_counter_other_vport[0x1];
 u8         log_max_xrcd[0x5];

 u8         nic_receive_steering_discard[0x1];
 u8         receive_discard_vport_down[0x1];
 u8         transmit_discard_vport_down[0x1];
 u8         eq_overrun_count[0x1];
 u8         reserved_at_344[0x1];
 u8         invalid_command_count[0x1];
 u8         quota_exceeded_count[0x1];
 u8         reserved_at_347[0x1];
 u8         log_max_flow_counter_bulk[0x8];
 u8         max_flow_counter_15_0[0x10];


 u8         reserved_at_360[0x3];
 u8         log_max_rq[0x5];
 u8         reserved_at_368[0x3];
 u8         log_max_sq[0x5];
 u8         reserved_at_370[0x3];
 u8         log_max_tir[0x5];
 u8         reserved_at_378[0x3];
 u8         log_max_tis[0x5];

 u8         basic_cyclic_rcv_wqe[0x1];
 u8         reserved_at_381[0x2];
 u8         log_max_rmp[0x5];
 u8         reserved_at_388[0x3];
 u8         log_max_rqt[0x5];
 u8         reserved_at_390[0x3];
 u8         log_max_rqt_size[0x5];
 u8         reserved_at_398[0x3];
 u8         log_max_tis_per_sq[0x5];

 u8         ext_stride_num_range[0x1];
 u8         roce_rw_supported[0x1];
 u8         log_max_current_uc_list_wr_supported[0x1];
 u8         log_max_stride_sz_rq[0x5];
 u8         reserved_at_3a8[0x3];
 u8         log_min_stride_sz_rq[0x5];
 u8         reserved_at_3b0[0x3];
 u8         log_max_stride_sz_sq[0x5];
 u8         reserved_at_3b8[0x3];
 u8         log_min_stride_sz_sq[0x5];

 u8         hairpin[0x1];
 u8         reserved_at_3c1[0x2];
 u8         log_max_hairpin_queues[0x5];
 u8         reserved_at_3c8[0x3];
 u8         log_max_hairpin_wq_data_sz[0x5];
 u8         reserved_at_3d0[0x3];
 u8         log_max_hairpin_num_packets[0x5];
 u8         reserved_at_3d8[0x3];
 u8         log_max_wq_sz[0x5];

 u8         nic_vport_change_event[0x1];
 u8         disable_local_lb_uc[0x1];
 u8         disable_local_lb_mc[0x1];
 u8         log_min_hairpin_wq_data_sz[0x5];
 u8         reserved_at_3e8[0x1];
 u8         silent_mode[0x1];
 u8         vhca_state[0x1];
 u8         log_max_vlan_list[0x5];
 u8         reserved_at_3f0[0x3];
 u8         log_max_current_mc_list[0x5];
 u8         reserved_at_3f8[0x3];
 u8         log_max_current_uc_list[0x5];

 u8         general_obj_types[0x40];

 u8         sq_ts_format[0x2];
 u8         rq_ts_format[0x2];
 u8         steering_format_version[0x4];
 u8         create_qp_start_hint[0x18];

 u8         reserved_at_460[0x1];
 u8         ats[0x1];
 u8         cross_vhca_rqt[0x1];
 u8         log_max_uctx[0x5];
 u8         reserved_at_468[0x1];
 u8         crypto[0x1];
 u8         ipsec_offload[0x1];
 u8         log_max_umem[0x5];
 u8         max_num_eqs[0x10];

 u8         reserved_at_480[0x1];
 u8         tls_tx[0x1];
 u8         tls_rx[0x1];
 u8         log_max_l2_table[0x5];
 u8         reserved_at_488[0x8];
 u8         log_uar_page_sz[0x10];

 u8         reserved_at_4a0[0x20];
 u8         device_frequency_mhz[0x20];
 u8         device_frequency_khz[0x20];

 u8         reserved_at_500[0x20];
 u8    num_of_uars_per_page[0x20];

 u8         flex_parser_protocols[0x20];

 u8         max_geneve_tlv_options[0x8];
 u8         reserved_at_568[0x3];
 u8         max_geneve_tlv_option_data_len[0x5];
 u8         reserved_at_570[0x1];
 u8         adv_rdma[0x1];
 u8         reserved_at_572[0x7];
 u8         adv_virtualization[0x1];
 u8         reserved_at_57a[0x6];

 u8    reserved_at_580[0xb];
 u8    log_max_dci_stream_channels[0x5];
 u8    reserved_at_590[0x3];
 u8    log_max_dci_errored_streams[0x5];
 u8    reserved_at_598[0x8];

 u8         reserved_at_5a0[0x10];
 u8         enhanced_cqe_compression[0x1];
 u8         reserved_at_5b1[0x1];
 u8         crossing_vhca_mkey[0x1];
 u8         log_max_dek[0x5];
 u8         reserved_at_5b8[0x4];
 u8         mini_cqe_resp_stride_index[0x1];
 u8         cqe_128_always[0x1];
 u8         cqe_compression_128[0x1];
 u8         cqe_compression[0x1];

 u8         cqe_compression_timeout[0x10];
 u8         cqe_compression_max_num[0x10];

 u8         reserved_at_5e0[0x8];
 u8         flex_parser_id_gtpu_dw_0[0x4];
 u8         reserved_at_5ec[0x4];
 u8         tag_matching[0x1];
 u8         rndv_offload_rc[0x1];
 u8         rndv_offload_dc[0x1];
 u8         log_tag_matching_list_sz[0x5];
 u8         reserved_at_5f8[0x3];
 u8         log_max_xrq[0x5];

 u8    affiliate_nic_vport_criteria[0x8];
 u8    native_port_num[0x8];
 u8    num_vhca_ports[0x8];
 u8         flex_parser_id_gtpu_teid[0x4];
 u8         reserved_at_61c[0x2];
 u8    sw_owner_id[0x1];
 u8         reserved_at_61f[0x1];

 u8         max_num_of_monitor_counters[0x10];
 u8         num_ppcnt_monitor_counters[0x10];

 u8         max_num_sf[0x10];
 u8         num_q_monitor_counters[0x10];

 u8         reserved_at_660[0x20];

 u8         sf[0x1];
 u8         sf_set_partition[0x1];
 u8         reserved_at_682[0x1];
 u8         log_max_sf[0x5];
 u8         apu[0x1];
 u8         reserved_at_689[0x4];
 u8         migration[0x1];
 u8         reserved_at_68e[0x2];
 u8         log_min_sf_size[0x8];
 u8         max_num_sf_partitions[0x8];

 u8         uctx_cap[0x20];

 u8         reserved_at_6c0[0x4];
 u8         flex_parser_id_geneve_tlv_option_0[0x4];
 u8         flex_parser_id_icmp_dw1[0x4];
 u8         flex_parser_id_icmp_dw0[0x4];
 u8         flex_parser_id_icmpv6_dw1[0x4];
 u8         flex_parser_id_icmpv6_dw0[0x4];
 u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
 u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];

 u8         max_num_match_definer[0x10];
 u8    sf_base_id[0x10];

 u8         flex_parser_id_gtpu_dw_2[0x4];
 u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
 u8    num_total_dynamic_vf_msix[0x18];
 u8    reserved_at_720[0x14];
 u8    dynamic_msix_table_size[0xc];
 u8    reserved_at_740[0xc];
 u8    min_dynamic_vf_msix_table_size[0x4];
 u8    reserved_at_750[0x2];
 u8    data_direct[0x1];
 u8    reserved_at_753[0x1];
 u8    max_dynamic_vf_msix_table_size[0xc];

 u8         reserved_at_760[0x3];
--> --------------------

--> maximum size reached

--> --------------------

Messung V0.5
C=100 H=100 G=100

¤ Dauer der Verarbeitung: 0.37 Sekunden  (vorverarbeitet)  ¤

*© Formatika GbR, Deutschland






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