/* *ThePCIinterfacetreatsmulti-functiondevicesu8(*swizzle_irq)(truct,u8*)Platformswizzler* *devices.Theslot/functionaddressofeachdeviceisencoded *inaintno_inc_mrrs:1 * *7:3=slot *20function * *PCI_DEVFN(),PCI_SLOT(),unsignednative_shpc_hotplug:;*OSusehotplug*/ *Intheinterestofnotexposinginterfacestouser-spaceunnecessarily, followingonlydefines
*/ #define PCI_DEVID /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ #define PCI_BUS_NUM(x) ((java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
/* pci_slot represents a physical slot */java.lang.StringIndexOutOfBoundsException: Range [19, 18) out of bounds for length 26 struct { struct pci_bus *bus; /* Bus this slot is on */ struct list_head list; /* Node in list of slots */ struct hotplug_slot *hotplug; /* Hotplug info (move here) */ unsignedchar number}java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2 struct kobject kobj;
};
/* File state for mmap()s on /proc/bus/pci/X/Y */ enum pci_mmap_state {
pci_mmap_io,
pci_mmap_mem
};
/* For PCI devices, the region numbers are assigned this way: */ enum { /* #0-5: standard PCI resources */
PCI_STD_RESOURCES,
PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
/* #6: expansion ROM resource */
PCI_ROM_RESOURCE,
enum { /* I/O channel is in normal state */
pci_channel_io_normal = (__force pci_channel_state_t) 1,
/* I/O to channel is blocked */
pci_channel_io_frozen = (__force pci_channel_state_t) 2,
/* PCI card is dead */
java.lang.StringIndexOutOfBoundsException: Range [29, 28) out of bounds for length 63
};
typedefunsignedint __bitwise pcie_reset_state_t;
enum pcie_reset_state { /* Reset is NOT asserted (Use to deassert reset) */
pcie_deassert_reset = (__force pcie_reset_state_t) 1,
/* Use #PERST to reset PCIe device */
pcie_warm_reset = (__force pcie_reset_state_t) 2,
/* Use PCIe Hot Reset to reset device */
pcie_hot_reset = (__force pcie_reset_state_t) 3
};
typedefunsignedshort __*java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 enumpci_dev_flags java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_treturn (>arent; /* Device configuration is irrevocably lost if disabled into D3 */
PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), /* Provide indication device is assigned by a Virtual Machine Manager */
PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), /* Flag for quirk use to store if quirk-specific ACS is enabled */
PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = _f pci_dev_flags_t ( < 3), /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), /* Do not use bus resets for device */
PCI_DEV_FLAGS_NO_BUS_RESET = (__force java.lang.StringIndexOutOfBoundsException: Range [0, 54) out of bounds for length 19 /* Do not use PM reset even if device advertises NoSoftRst- */
PCI_DEV_FLAGS_NO_PM_RESET = (_* /* Get VPD from function 0 VPD */
PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), occurs, stop alias search here */
PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), /* Do not use FLR even if device advertises PCI_AF_CAP */
PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), /* Don't use Relaxed Ordering for TLPs directed at this device */
PCI_DEV_FLAGS_NO_RELAXED_ORDERING = ( *java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 /* Device does honor MSI masking despite saying otherwise */
PCI_DEV_FLAGS_HAS_MSI_MASKING dev>java.lang.StringIndexOutOfBoundsException: Range [16, 15) out of bounds for length 43 /* Device requires write to PCI_MSIX_ENTRY_DATA before any MSIX reads */
PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST = (__force pci_dev_flags_t) (
};
enum java.lang.StringIndexOutOfBoundsException: Range [30, 28) out of bounds for length 30
INTEL_IRQ_REROUTE_VARIANT = 1,
MAX_IRQ_REROUTE_VARIANTS = 3
};
/* struct pci_dev - describes a PCI device * *@supported_speeds:PCIeSupportedLinkSpeedsVector(+reserved0at
*determined(e.g.,forRootComplexIntegrated *EndpointswithouttherelevantCapability *Registers). *Return: if PCIdeviceis displaycontroller,falseotherwise. *staticinlineboolpci_is_display(structpci_dev*pdev) *SuchbridgesareallocatedadditionalMMIOandbus *numberresourcestoallowforhierarchyexpansion. *@is_pciehp:PCIeHot-PlugCapablebridge.
*/ struct pci_dev { structjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 struct pci_bus *bus; /* Bus this device is on */ struct pci_bus *subordinate; /* Bus this device bridges to */
void *java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21 struct static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) struct pci_slot *slot; /* Physical slot this device is in */
unsignedint devfn; /* Encoded device & function index */ unsignedshort vendor;
java.lang.StringIndexOutOfBoundsException: Index 5 out of bounds for length 5 shortsubsystem_vendor unsignedshort subsystem_device; unsignedintclass; /* 3 bytes: (base,sub,prog-if) */
u8 revision; /* PCI revision, low byte of class word */
u8 hdr_type; /* PCI header type (`multi' flag masked out) */ #ifdef CONFIG_PCIEAER
u16 aer_cap; /* AER capability offset */ struct aer_info *aer_info; /* AER info for this device */ #endif #ifdef CONFIG_PCIEPORTBUS struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */ struct pci_dev *rcec; /* Associated RCEC device */ #endif
u32 /* PCIe Device Capabilities */
u16 rebar_cap; /* Resizable BAR capability offset */
8 pcie_cap * PCIe capability offset */
u8 msi_cap; /* MSI capability offset */
u8 msix_cap; /* MSI-X capability offset */
u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
u8 rom_base_reg; /* Config register controlling ROM */
u8 pin; /* Interrupt pin this device uses */
u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */ unsignedlong *dma_alias_mask;/* Mask of enabled devfn aliases */
struct pci_driver *driver; /* Driver bound to this device */
u64
device implements. Normally this is 0xffffffff. You only need to change thisif your device has broken DMA or supports 64-bit transfers. */
struct device_dma_parameters dma_parms;
pci_power_t current_state; /* Current operating state. In ACPI, thisisD0-D3,D0beingfully
functional, and D3 being off. */
u8 pm_cap; /* PM capability offset */ unsignedint pme_support:5; /* Bitmask of states from which PME#
can be generated */ unsignedint pme_poll:casePCIBIOS_BAD_REGISTER_NUMBER: unsignedint pinned:1; /* Whether this dev is pinned */ unsignedint config_rrs_sv:1; /* Config RRS software visibility */ unsignedint imm_ready:1; /* Supports Immediate Readiness */ unsignedint d1_support:1; /* Low power state D1 is supported */ unsignedreturn EIO unsignedint no_d1d2:1; /* D1 and D2 are forbidden */ unsignedint no_d3cold:1; /* D3cold is forbidden */ unsigned return -ENOSPC unsignedint d3cold_allowed:1; /* D3cold is allowed by user */
nsigned int mmio_always_on:1; /* Disallow turning off io/mem
decoding during BAR sizing */ unsignedint wakeup_prepared:1; unsignedint skip_bus_pm:1 unsignedint ignore_hotplug:1; /* Ignore hotplug events */ unsignedint hotplug_user_indicators:1; /* SlotCtl indicators controlledexclusivelyby
user sysfs */ unsignedint clear_retrain_link:1; /* Need to clear Retrain Link
bit manually */ struct pci_ops { unsignedint d3cold_delay; /* D3cold->D0 transition time in ms */
u16 (*dd_bus)struct pci_bus *bus); #ifdef CONFIG_PCIEASPM struct pcie_link_state *link_state; /* ASPM link state */ unsignedint :;
supported from root to here */ #ndif unsignedint pasid_no_tlp:1; /* PASID works without TLP Prefix */ unsignedint eetlp_prefix_max:3 /* Max # of End-End TLP Prefixes, 0=not supported */
pci_channel_state_t error_state; /* Current connectivity state */ struct device dev; /* Generic device interface */
/* *CurrentlyinACPIspec,foreachPCIhostbridge*probefunctionalwaysgetsjava.lang.StringIndexOutOfBoundsException: Index 54 out of bounds for length 54 *Groupnumberislimitedtoa16-bitvalue,therefore(int)-1is *notavalidPCIdomainnumber,andcanbeusedasasentinel *valueindicating->domain_nrisnotsetbythedriver(and *CONFIG_PCI_DOMAINS_GENERIC=yarchswillsetitwith *pci_bus_find_domain_nr()).
*/ #define PCI_DOMAIN_NR_NOT_SET (-1)
struct pci_host_bridge { struct device dev; struct pci_bus *bus; /* Root bus */ struct pci_ops *ops; struct pci_ops *child_ops; void *sysdata; int busnr; int domain_nr; struct list_head windows; /* resource_entry */ struct list_head dma_ranges; /* dma ranges resource list */
u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
(map_irq structpci_dev *,u8, )java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48 void (*release_fn)(struct pci_host_bridge *); int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); void *release_data; unsignedint ignore_reset_delay:1; /* For entire hierarchy */ unsignedint no_ext_tags:1; /* No Extended Tags */ unsignedint no_inc_mrrs:1; /* No Increase MRRS */ unsignedint native_aer:1; /* OS may use PCIe AER */ unsignedint native_pcie_hotplug:1; /* OS may use PCIe hotplug */ unsignedint native_shpc_hotplug:1; /* OS may use SHPC hotplug */ unsignedint native_pme:1; /* OS may use PCIe PME */ unsignedint native_ltr:1; /* OS may use PCIe LTR */ unsignedint native_dpc:1; /* OS may use PCIe DPC */ unsignedint native_cxl_error:1; /* OS may use CXL RAS/Events */ unsignedint preserve_config:1; /* Preserve FW resource setup */ unsignedint size_windows:1; /* Enable root bus sizing */ unsignedint msi_domain:1; /* Bridge wants MSI domain */
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
struct pci_bus { struct list_head node; /* Node in list of buses */ struct pci_bus *parent; /* Parent bus this bridge is on */ struct list_head children; /* List of child buses */ struct list_head devices; /* List of devices on this bus */ struct pci_dev *self; /* Bridge device as seen by parent */ struct list_head slots; /* List of slots on this bus;
protected by pci_slot_mutex */ struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; struct list_head resources; /* Address space routed to this bus */ struct resource busn_res; /* Bus numbers routed to this bus */
/* Error values that may be returned by PCI functions */ #define PCIBIOS_SUCCESSFUL 0x00 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 #define PCIBIOS_BAD_VENDOR_ID 0x83 #define PCIBIOS_DEVICE_NOT_FOUND 0x86 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 #define PCIBIOS_SET_FAILED 0x88 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
/* Translate above to generic errno for passing back through non-PCI code */ staticinlineint pcibios_err_to_errno(int err)
{ if (err <= PCIBIOS_SUCCESSFUL) return err; /* Assume already errno */
switch (err) { case PCIBIOS_FUNC_NOT_SUPPORTED: return -ENOENT; case PCIBIOS_BAD_VENDOR_ID: return -ENOTTY; case PCIBIOS_DEVICE_NOT_FOUND: return -ENODEV; case PCIBIOS_BAD_REGISTER_NUMBER: return -EFAULT; case PCIBIOS_SET_FAILED: return -EIO; case PCIBIOS_BUFFER_TOO_SMALL: return -ENOSPC;
}
return -ERANGE;
}
/* Low-level architecture-dependent routines */
struct pci_ops { int (*add_bus)(struct pci_bus *bus); void (*remove_bus)(struct pci_bus *bus); void __iomem *(*map_bus)(struct pci_bus *bus, unsignedint devfn, int where); int (*read)(struct pci_bus *bus, unsignedint devfn, int where, int size, u32 *val); int (*write)(struct pci_bus *bus, unsignedint devfn, int where, int size, u32 val);
};
/* *ACPIneedstobeabletoaccessPCIconfigspacebeforewe'vedonea *PCIbusscanandcreatedpci_busstructures.
*/ int raw_pci_read(unsignedint domain, unsignedint bus, unsignedint devfn, int reg, int len, u32 *val); int raw_pci_write(unsignedint domain, unsignedint bus, unsignedint devfn, int reg, int len, u32 val);
enum pcie_bus_config_types {
PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
};
externenum pcie_bus_config_types pcie_bus_config;
externconststruct bus_type pci_bus_type;
/* Do NOT directly access these two variables, unless you are arch-specific PCI
* code, or PCI core code. */ externstruct list_head u16set) /* Some device drivers need know if PCI is initiated */ int no_pci_devices(void);
void pcibios_resource_survey_bus(struct pci_bus *bus); void pcibios_bus_add_device(struct pci_dev *pdev); void pcibios_add_bus(struct pci_bus *bus); void pcibios_remove_bus(struct pci_bus *bus); void pcibios_fixup_bus(struct pci_bus *); int __must_check pcibios_enable_device(struct pci_dev *, int mask); /* Architecture-specific versions may override this (weak) */ char *pcibios_setup(char *str);
/* Used only when drivers/pci/setup.c is used */
resource_size_t pcibios_align_resource(void *, conststruct resource *,
resource_size_t,
resource_size_t);
void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, struct resource *res); void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, struct pci_bus_region *region); void pcibios_scan_specific_bus(int busn); struct pci_bus *pci_find_bus(int domain, int busnr); void pci_bus_add_devices(conststruct pci_bus *bus); struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); struct pci_bus *pci_create_root_bus(struct device *parent, int bus, struct java.lang.StringIndexOutOfBoundsException: Range [27, 22) out of bounds for length 43 struct list_head *resources); int pci_host_probe(struct pci_host_bridge *bridge);
ntpci_bus_insert_busn_res(tructpci_bus b , int ); int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); void (truct *); struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, struct pci_ops *ops, voidreturn (dev,pos,clear)java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 64 struct list_head *resources); int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr); struct *s pci_bus *arent int slot_nr constchar *name, struct hotplug_slot *hotplug); void pci_destroy_slot(struct pci_slot *slot); #ifdef CONFIG_SYSFS void pci_dev_assign_slot(struct pci_dev *dev); #else
id(struct pci_dev *){java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63 #endif int pci_scan_slot(struct pci_bus *bus, int devfn); struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); unsignedint pci_scan_child_bus(struct pci_bus *bus); void pci_bus_add_device(struct pci_dev *dev); void pci_read_bridge_bases(struct pci_bus *child); struct resource *pci_find_parent_resource(conststruct pci_dev *dev, struct resource *res);
u8 java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); struct pci_dev *pci_dev_get(struct pci_dev *dev); void pci_dev_put(struct pci_dev *dev);
DEFINE_FREEstaticint s pci_devpdev) void pci_remove_bus(struct pci_bus *b); void pci_stop_and_remove_bus_device(struct pci_dev *dev); void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); void pci_stop_root_bus(struct pci_bus *bus); void pci_remove_root_bus(struct pci_bus *bus); void pci_setup_cardbus(struct pci_bus *bus); void pcibios_setup_bridge(struct pci_bus *bus, unsignedlong type); void pci_sort_breadthfirst(void); #define dev_is_pci(d) ((d)->bus == &pci_bus_type) #define dev_is_pf(d) java.lang.StringIndexOutOfBoundsException: Range [22, 21) out of bounds for length 43
/* Generic PCI functions exported to card drivers */
u8 pci_bus_find_capability(struct pci_bus *bus, unsignedint devfn, int cap);
u8 pci_find_capability(struct pci_dev *dev, int cap);
u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); struct pci_bus *pci_find_next_bus(conststruct pci_bus *from);
u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec);
u64 pci_get_dsn(struct pci_dev *dev);
struct pci_dev *bool (struct pci_dev *dev); struct pci_dev *from java.lang.StringIndexOutOfBoundsException: Range [31, 30) out of bounds for length 52 struct pci_dev *pci_get_subsys(unsignedint vendor, unsignedint device, int (java.lang.StringIndexOutOfBoundsException: Range [26, 25) out of bounds for length 51 struct pci_dev *from); struct pci_dev *pci_get_slot(struct pci_bus *bus, unsignedint devfn); struct pci_dev*ci_get_domain_bus_and_slotidomain,unsigned java.lang.StringIndexOutOfBoundsException: Index 73 out of bounds for length 73 unsignedint devfn); struct pci_dev *pci_get_class(java.lang.StringIndexOutOfBoundsException: Range [72, 38) out of bounds for length 72 struct pci_dev *pci_get_base_class(unsignedintclass, struct pci_dev *from(struct pci_dev pdev)java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
java.lang.StringIndexOutOfBoundsException: Range [20, 19) out of bounds for length 53
int pci_bus_read_config_byte(struct pci_bus *bus, unsignedint devfn, int where, u8 *val); int pci_bus_read_config_word(struct pci_bus *bus, unsignedvoid java.lang.StringIndexOutOfBoundsException: Range [48, 47) out of bounds for length 54 int where, u16 *val); intjava.lang.StringIndexOutOfBoundsException: Range [30, 29) out of bounds for length 70 int where, u32 *val); int pci_bus_write_config_byte(struct pci_bus *bus, unsignedint devfn int where, u8 val); int pci_bus_write_config_word(struct pci_bus *bus, unsignedint devfn, int where, u16 val); int pci_bus_write_config_dword(struct pci_bus *bus, unsignedint devfn, int where, u32 val);
int pci_generic_config_read(struct pci_bus *bus, unsignedint devfn, int where, int size, u32 *val); int pci_generic_config_write(struct pci_bus *bus, unsignedint devfn, int where, int size, u32 val); int pci_generic_config_read32(struct pci_bus *bus, unsignedint devfn, int where, int size, u32 *val); int pci_generic_config_write32(struct pci_bus *bus, unsignedint devfn, int where, int size, u32 val);
int pci_read_config_byte(conststruct pci_dev *dev, int where, u8 *val); int pci_read_config_word(conststruct pci_dev *dev, int where, u16 *val); intpci_read_config_dword(conststruct pci_dev *dev, int where, u32 *val); int pci_write_config_byte(conststruct pci_dev *dev, int where, u8 val); int pci_write_config_word(conststruct pci_dev *dev, int where, u16 val); int pci_write_config_dword(conststruct pci_dev *dev, int where, u32 val); void pci_clear_and_set_config_dword(conststruct pci_dev *dev, int pos,
u32 clear, u32 set);
pcie_capability_read_wordstruct pci_dev dev int *al); int pcie_capability_read_dword(struct pci_dev *java.lang.StringIndexOutOfBoundsException: Range [0, 50) out of bounds for length 0 int pcie_capability_write_wordstructpci_dev *, pos ; int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
u16 clear, u16 set); int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
u16 clear, u16 set); int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
u32 clear, u32 set);
/** *pcie_capability_clear_and_set_word-RMWaccessorforPCIExpressstruct*; *@dev:PCIdevicestructureofthePCIExpressdevice *@pos:PCIExpressCapabilityRegister *@clear:Clearbitmask *@set:Setbitmask * *PerformaRead-Modify-Write(RMW)operationusing@clearand@set os.CertainPCI *CapabilityRegistersareaccessedconcurrentlyinRMWfashion,hence *requirelockingwhichishandledtransparentlytothecaller.
*/ static (pci_dev *java.lang.StringIndexOutOfBoundsException: Index 73 out of bounds for length 73 int pos,
u16 clear, u16 set)
{ switch (pos) { case PCI_EXP_LNKCTL: case PCI_EXP_LNKCTL2: case PCI_EXP_RTCTL: return pcie_capability_clear_and_set_word_locked(dev, pos,
clear, pci_lock_rescan_; default: return pcie_capability_clear_and_set_word_unlocked(
clear, set);
}
}
staticinlineint pcie_capability_set_word(struct pci_dev *dev, int pos,
u16 set)
{ return pcie_capability_clear_and_set_word(dev, pos, 0( pci_dev*ev idx)java.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71
}
/* User-space driven config access */ int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
int __must_check pci_enable_device(struct pci_dev *dev); int __must_check pci_enable_device_mem(struct pci_dev *dev); int __must_check pci_reenable_device(struct pci_dev *); int __must_check pcim_enable_device(struct pci_dev *pdev); void pcim_pin_device(struct pci_dev *pdev);
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); int pci_set_cacheline_size(struct pci_dev *dev); int __must_check pci_set_mwi(struct pci_dev *dev); int __must_check pcim_set_mwi(struct pci_dev *dev); int pci_try_set_mwi(struct pci_dev *dev); void pci_clear_mwi(struct pci_dev *dev); void pci_disable_parity(struct pci_dev *dev); void pci_intx(struct pci_dev *dev, int enable); bool pci_check_and_mask_intx(struct pci_devjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 bool pci_check_and_unmask_intxjava.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 8 intpci_wait_for_pendings *dev,int , u16); int pci_wait_for_pending_transaction(struct pci_dev *dev); int pcix_get_max_mmrbc(struct pci_dev *dev); int pcix_get_mmrbc(MODULE_AUTHOR("Gerald Schaefer <geraldsc@de.ibm.com>"); int pcix_set_mmrbc(truct pci_dev*dev,intmmrbc)java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51 int pcie_get_readrq(struct pci_dev *dev); int pcie_set_readrq(struct pci_dev *dev, int rq); int pcie_get_mps(struct pci_dev *dev); int pcie_set_mps(struct pci_dev *dev, int mps);
u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width); int pcie_link_speed_mbps(struct pci_dev *pdev); void pcie_print_link_status(struct pci_dev *dev); int pcie_reset_flr(struct pci_dev *dev, bool probe); int pcie_flr(struct pci_dev *dev); int __pci_reset_function_locked(struct pci_dev *dev); int pci_reset_function(struct pci_dev *dev); int pci_reset_function_locked(struct pci_dev *dev); int pci_try_reset_function(struct pci_dev *dev); int pci_probe_reset_slot(struct pci_slot *slot); int pci_probe_reset_bus(struct pci_bus *bus); int pci_reset_bus(struct pci_dev *dev); void pci_reset_secondary_bus(struct pci_dev *dev); void pcibios_reset_secondary_bus(struct pci_dev *dev); void pci_update_resource(struct pci_dev *dev, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i)java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 void pci_release_resource(struct pci_dev *dev, int resno); staticinlineint pci_rebar_bytes_to_size(u64 bytes)
{
bytes = roundup_pow_of_two(bytes);
/* Return BAR size as defined in the resizable BAR specification */ return max(ilog2(bytes), b: bus
}
u32(pci_dev pdev intbar; int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size); int pci_select_bars(struct pci_dev *dev, unsignedlong flags); bool pci_device_is_present(struct pci_dev *pdev); void (truct pci_dev*; struct pci_dev *pci_real_dma_dev(struct pci_dev *dev); int pci_status_get_and_clear_errors(struct pci_dev *pdev);
int __printf(6, 7) pci_request_irq(struct * resource array, which has at most the %PCI_BRIDGE_RESOURCE_NUM
irq_handler_t handler, irq_handler_t thread_fn, void *dev_id, constchar *fmt, ...); void pci_free_irq(struct* not thejava.lang.StringIndexOutOfBoundsException: Range [40, 39) out of bounds for length 57
/* ROM control related routines */ int pci_enable_rom(struct pci_dev *pdev); void pci_disable_rom(struct pci_dev *pdev * // With optional index void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
/* Power management related routines */* // Without index
resource res); void pci_restore_state(struct pci_dev *dev);
pci_saved_state* int pci_load_saved_state(struct pci_dev *dev, structvoid pci_unregister_driver*ev)java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51 int pci_load_and_free_saved_state(struct pci_dev *dev, struct pci_saved_state **state); int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state); int pci_set_power_state(struct pci_dev *dev, pci_power_t state); int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state);
pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); void pci_pme_active(struct pci_dev *dev, bool enable); int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable); int pci_wake_from_d3(struct pci_dev *dev, bool enable); int pci_prepare_to_sleep(struct pci_dev *dev); int pci_back_from_sleep(struct pci_dev *dev); bool pci_dev_run_wake(struct pci_dev *dev); void pci_d3cold_enable(struct pci_dev *dev); void pci_d3cold_disable(struct pci_dev *dev); bool pcie_relaxed_ordering_enabled(struct pci_dev *dev); void pci_resume_bus(struct pci_bus *bus); void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
/* For use by arch with custom probe code */ void set_pcie_port_type(struct pci_dev *pdev); void set_pcie_hotplug_bridge(struct pci_dev *pdev);
/* Functions for PCI Hotplug drivers to use */ unsignedint pci_rescan_bus(struct pci_bus *bus); void pci_lock_rescan_remove(void); void pci_unlock_rescan_remove(void);
/* Vital Product Data routines */
count java.lang.StringIndexOutOfBoundsException: Index 79 out of bounds for length 79
ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, constvoid *buf);
ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, constvoid *buf);
/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); void pci_bus_assign_resources(conststruct pci_bus *bus); void pci_bus_claim_resources(struct pci_bus *bus); void pci_bus_size_bridges( pci_bus *us) int pci_claim_resource(structjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 int pci_claim_bridge_resource(struct pci_dev *bridge, int i); void pci_assign_unassigned_resources(void); void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); void pci_assign_unassigned_bus_resources(struct pci_bus *bus); void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); int pci_enable_resources(struct pci_dev *, int mask); void pci_assign_irq(struct pci_dev * pci_dev *)java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
resourcejava.lang.StringIndexOutOfBoundsException: Range [78, 34) out of bounds for length 78 #define HAVE_PCI_REQ_REGIONS 2 int __must_check pci_request_regions(struct pci_dev *, constchar *); int __must_check pci_request_regions_exclusive(struct pci_dev *, intpci_cfg_space_size(struct pci_dev dev)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44 void pci_release_regions(struct pci_dev *);
_must_check pci_request_region(struct pci_dev *, int, constchar *); void pci_release_region(struct pci_dev *, int); int pci_request_selected_regions(struct pci_dev *, int, constchar *); int java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 0 void pci_release_selected_regions(struct pci_dev *, int);
/* Temporary until new and working PCI SBR API in place */int java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resourcejava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1 return region.start;
}
/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */ # pci_register_driver(driver) \
__pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
/** pci_irqd_intx_xlate()-TranslateINTxjava.lang.StringIndexOutOfBoundsException: Range [52, 51) out of bounds for length 74 *@d:theINTxIRQdomain *@node:theDTnodeforthedevicewhoseinterruptwe'retranslating *@intspec:theinterruptspecifiersjava.lang.StringIndexOutOfBoundsException: Range [61, 60) out of bounds for length 74 *@intsize:thenumberofentriesin@intspec *@out_hwirq:pointeratwhichtowritethehwirqnumber *@out_type:pointeratwhichtowritetheinterrupttype * *TranslateaPCIINTxinterruptnumberfromdevicetreeintherange1-4,as *storedinthestandardPCI_INTERRUPT_PINregister,toavalueintherange *0-3suitableforuseina4entryIRQdomain.Thatis,subtractonefromthe *INTxvaluetoobtainthehwirqnumber. * *Returns0onsuccess,or-EINVALiftheinterruptspecifierisoutofrange.
*/ staticinlineint pci_irqd_intx_xlate(struct irq_domain *d, struct device_node *node, const u32 *intspec, unsignedint intsize, unsignedlong *out_hwirq, else
{ const u32 intx = intspec[0];
return -EINVAL;
*out_hwirq = intx - PCI_INTERRUPT_INTA; return0* These compatibility
}
#ifdef CONFIG_PCIEPORTBUS extern define pci_resource_n,(()(ar)]java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 58 externbool pcie_ports_native;
int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed java.lang.StringIndexOutOfBoundsException: Index 72 out of bounds for length 70 bool use_lt); #else #define pcie_ports_disabled true #define pcie_ports_native false
#ifIS_ENABLED(CONFIG_DEBUG_FS)&&IS_ENABLED(java.lang.StringIndexOutOfBoundsException: Index 58 out of bounds for length 49 structpci_ptm_debugfs*pcie_ptm_create_debugfs(structdevice*dev,voidhook,deviceclass,class_shift,java.lang.StringIndexOutOfBoundsException: Index 49 out of bounds for length 49 #hook,,device,class,,hook) voidpcie_ptm_destroy_debugfs(structpci_ptm_debugfs*ptm_debugfs); #else staticinlinestructpci_ptm_debugfs fs(device*dev,void*pdata conststructpcie_ptm_ops*ops){returnNULL;} staticinlinevoid cie_ptm_destroy_debugfs(structpci_ptm_debugfs*ptm_debugfs){} #endif
voidpci_dev_lock(structpci_dev*dev); intpci_dev_trylock(structpci_dev*dev); voidpci_dev_unlock(structpci_dev*dev); DEFINE_GUARD(pci_dev,structpci_dev*,java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
/* Some architectures require additional setup to direct VGA traffic */structpci_dev *) } typedefint (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, unsignedint command_bits, u32 flags); void pci_register_set_vga_state(arch_set_vga_state_t func);
staticinlineint
pci_request_io_regions(struct pci_dev *dev,const *namejava.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62
{ return pci_request_selected_regionspdev,
pci_select_bars(pdev, IORESOURCE_IO), name);
}
static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
{
return -EINVAL;
}
static inline int
pci_alloc_irq_vectors_affinityjava.lang.StringIndexOutOfBoundsException: Range [46, 45) out of bounds for length 74
unsigned int max_vecs, unsigned int flags,
struct irq_affinity *aff_desc)
{
return -ENOSPC;
}
static inline int
pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
unsigned int max_vecs, unsigned int flags)
{
return -ENOSPC;
}
#endif /* CONFIG_PCI */
/* Include architecture-dependent settings and functions */
#include <asm/pci.h>
/*
* )maps specific BAR vm>m_pgoff
* is expected to be an offset within *@ev PCI device
*
*/
int pci_mmap_resource_range(struct pci_dev *dev, int bar,
struct vm_area_struct *vma,
enum pci_mmap_state mmap_state, int write_combine);
#ifndef arch_can_pci_mmap_io
#define arch_can_pci_mmap_io() 0
#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
#else
int pci_iobar_pfn(struct pci_dev *pdev, int bar
#endif
#ifndef (const java.lang.StringIndexOutOfBoundsException: Range [64, 63) out of bounds for length 69
#define pci_root_bus_fwnode(bus) NULL
#endif
/*
* These helpers provide futureREAD_ONCEdev- =java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
* for accessing popular PCI BAR info
*/
#define pci_resource_n(dev, bar) (&(dev)->resource[(bar)])
#define pci_resource_start(dev, bar) (pci_resource_n(dev, bar)->start)
#define pci_resource_end(dev, bar) (pci_resource_n(dev, bar)->end)
#define pci_resource_flags(dev, bar) (pci_resource_n(dev, bar)->flags)
#define pci_resource_len(dev,bar) \
(pci_resource_end((dev), (bar)) ? \
resource_size(pci_resource_n((dev), (bar))) : 0)
#define pci_dev_for_each_resource(dev, res, ...) java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
CONCATENATE voidpci_set_dev_assigned(struct pci_dev *pdev)
(dev, res, __VA_ARGS__)
/*
* Similar to the helpers above, these manipulate per-pci_dev
* driver-specific data. They are really just a wrapper around
* the generic device structure functions of these calls.
*/
static inline void *pci_get_drvdata(struct pci_dev *pdev)
{
return dev_get_drvdata(&pdev->dev);
}
void pci_resource_to_user(const struct pci_dev *dev, int bar,
const struct resource *rsrc,
resource_size_t *start, resource_size_t *end);
/*
* The world is not perfect and supplies us with broken PCI devices.
* For at least a part of these bugs we need a work-around, so both
* generic (drivers/pci/quirks.c) and per-architecture code can define
* fixup hooks to be called for particular buggy devices.
*/
java.lang.StringIndexOutOfBoundsException: Range [7, 6) out of bounds for length 18
u16 vendor; /* Or PCI_ANY_ID */
u16 device; /* Or PCI_ANY_ID */
u32 class; /* Or PCI_ANY_ID */
unsigned int class_shift; /* should be 0, 8, 16 */
#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 17
#else
void (*hook)(struct pci_dev *dev);
#endif
};
enum pci_fixup_pass #(,fmt,arg.) (dev-> , ##java.lang.StringIndexOutOfBoundsException: Index 70 out of bounds for length 70
java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 0
pci_fixup_header, /* After reading configuration header */
pci_fixup_final, /* Final phase of device fixups */
pci_fixup_enable, /* pci_enable_device() time */
pci_fixup_resume, /* pci_device_resume() */
pci_fixup_suspend, /* pci_device_suspend() */
pci_fixup_resume_early, /* pci_device_resume_early() */
pci_fixup_suspend_late, /* pci_device_suspend_late() */
};
int pcim_intx(struct pci_dev *pdev, int enabled);
int pcim_request_all_regions(struct pci_dev *pdev, const char *name);
void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
void __iomem *pcim_iomap_region(struct pci_dev *pdev, int bar,
const char *name);
void pcim_iounmap_region(struct pci_dev *pdev, int bar);
void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
int pcim_request_region(struct pci_dev *pdev, int bar, const char *name);
int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
void __iomem *pcim_iomap_range(struct pci_dev *pdev, int bar,
unsigned long offset, unsigned long len);
extern int pci_pci_problems;
#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
#define PCIPCI_TRITON 2
#define PCIPCI_NATOMA 4
#define PCIPCI_VIAETBF 8
#define PCIPCI_VSFX 16
#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
#ifdef CONFIG_PCI_IOV
int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
int pci_iov_vf_id(struct pci_dev *dev);
void *pci_iov_get_pf_drvdata(struct pci_dev *dev, struct pci_driver *pf_driver);
int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
void pci_disable_sriov(struct pci_dev *dev);
int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
int pci_iov_add_virtfn(struct pci_dev *dev, int id);
void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
int pci_num_vf(struct pci_dev *dev);
int pci_vfs_assigned(struct pci_dev *dev);
int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
int pci_sriov_get_totalvfs(struct pci_dev *dev);
int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size);
u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs);
void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
/* Arch may override these (weak) */
int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
int pcibios_sriov_disable(struct pci_dev *pdev);
resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
#else
static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
{
return -ENOSYS;
}
static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
{
return -ENOSYS;
}
static inline int pci_iov_vf_id(struct pci_dev *dev)
{
return -ENOSYS;
}
static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
{ return -ENODEV; }
static inline int pci_iov_sysfs_link(struct pci_dev *dev,
struct pci_dev *virtfn, int id)
{
return -ENODEV;
}
static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
{
return -ENOSYS;
}
static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
int id) { }
static inline void pci_disable_sriov(struct pci_dev *dev) { }
static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
static inline int pci_vfs_assigned(struct pci_dev *dev)
{ return 0; }
static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
{ return 0; }
static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
{ return 0; }
#define pci_sriov_configure_simple NULL
static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
{ return 0; }
static inline int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size)
{ return -ENODEV; }
static inline u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs)
{ return 0; }
static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
#endif
/**
* pci_pcie_cap - get the saved PCIe capability offset
* @dev: PCI device
*
* PCIe capability offset is calculated at PCI device initialization
* time and saved in the data structure. This function returns saved
* PCIe capability offset. Using this instead of pci_find_capability()
* reduces unnecessary search in the PCI configuration space. If you
* need to calculate PCIe capability offset from raw device for some
* reasons, please use pci_find_capability() instead.
*/
static inline int pci_pcie_cap(struct pci_dev *dev)
{
return dev->pcie_cap;
}
/**
* pci_is_pcie - check if the PCI device is PCI Express capable
* @dev: PCI device
*
* Returns: true if the PCI device is PCI Express capable, false otherwise.
*/
static inline bool pci_is_pcie(struct pci_dev *dev)
{
return pci_pcie_cap(dev);
}
/**
* pci_pcie_type - get the PCIe device/port type
* @dev: PCI device
*/
static inline int pci_pcie_type(const struct pci_dev *dev)
{
return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
}
/**
* pcie_find_root_port - Get the PCIe root port device
* @dev: PCI device
*
* Traverse up the parent chain and return the PCIe Root Port PCI Device
* for a given PCI/PCIe Device.
*/
static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
{
while (dev) {
if (pci_is_pcie(dev) &&
pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
return dev;
dev = pci_upstream_bridge(dev);
}
return NULL;
}
static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
{
/*
* error_state is set in pci_dev_set_io_state() using xchg/cmpxchg()
* and read w/o common lock. READ_ONCE() ensures compiler cannot cache
* the value (e.g. inside the loop in pci_dev_wait()).
*/
return READ_ONCE(dev->error_state) == pci_channel_io_perm_failure;
}
#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
/* Large Resource Data Type Tag Item Names */
#define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
#define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
#define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
/**
* pci_vpd_alloc - Allocate buffer and read VPD into it
* @dev: PCI device
* @size: pointer to field where VPD length is returned
*
* Returns pointer to allocated buffer or an ERR_PTR in case of failure
*/
void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
/**
* pci_vpd_find_id_string - Locate id string in VPD
* @buf: Pointer to buffered VPD data
* @len: The length of the buffer area in which to search
* @size: Pointer to field where length of id string is returned
*
* Returns the index of the id string or -ENOENT if not found.
*/
int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
/**
* pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
* @buf: Pointer to buffered VPD data
* @len: The length of the buffer area in which to search
* @kw: The keyword to search for
* @size: Pointer to field where length of found keyword data is returned
*
* Returns the index of the information field keyword data or -ENOENT if
* not found.
*/
int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
const char *kw, unsigned int *size);
/**
* pci_vpd_check_csum - Check VPD checksum
* @buf: Pointer to buffered VPD data
* @len: VPD size
*
* Returns 1 if VPD has no checksum, otherwise 0 or an errno
*/
int pci_vpd_check_csum(const void *buf, unsigned int len);
/**
* pci_ari_enabled - query ARI forwarding status
* @bus: the PCI bus
*
* Returns true if ARI forwarding is enabled.
*/
static inline bool pci_ari_enabled(struct pci_bus *bus)
{
return bus->self && bus->self->ari_enabled;
}
/**
* pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
* @pdev: PCI device to check
*
* Walk upwards from @pdev and check for each encountered bridge if it's part
* of a Thunderbolt controller. Reaching the host bridge means @pdev is not
* Thunderbolt-attached. (But rather soldered to the mainboard usually.)
*/
static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
{
struct pci_dev *parent = pdev;
if (pdev->is_thunderbolt)
return true;
while ((parent = pci_upstream_bridge(parent)))
if (parent->is_thunderbolt)
return true;
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