/* SPDX-License-Identifier: GPL-2.0-only */ /***************************************************************************** * * Copyright ( C ) 2008 Cedric Bregardis < cedric . bregardis @ free . fr > and * Jean - Christian Hassler < jhassler @ free . fr > * * This file is part of the Audiowerk2 ALSA driver * /* SAA7146 registers */ #define PCI_BT_A 0 x4C#define IICTFR 0 x8C#define IICSTA 0 x90#define BaseA1_in 0 x94#define ProtA1_in 0 x98#define PageA1_in 0 x9C#define BaseA1_out 0 xA0#define ProtA1_out 0 xA4#define PageA1_out 0 xA8#define BaseA2_in 0 xAC#define ProtA2_in 0 xB0#define PageA2_in 0 xB4#define BaseA2_out 0 xB8#define ProtA2_out 0 xBC#define PageA2_out 0 xC0#define IER 0 xDC#define GPIO_CTRL 0 xE0#define ACON1 0 xF4#define ACON2 0 xF8#define MC1 0 xFC#define MC2 0 x100#define ISR 0 x10C#define PSR 0 x110#define SSR 0 x114#define PCI_ADP1 0 x12C#define PCI_ADP2 0 x130#define PCI_ADP3 0 x134#define PCI_ADP4 0 x138#define LEVEL_REP 0 x140#define FB_BUFFER1 0 x144#define FB_BUFFER2 0 x148#define TSL1 0 x180#define TSL2 0 x1C0#define ME (1 UL << 11 )#define LIMIT (1 UL << 4 )#define PV (1 UL << 3 )/* PSR/ISR/IER */ #define PPEF (1 UL << 31 )#define PABO (1 UL << 30 )#define IIC_S (1 UL << 17 )#define IIC_E (1 UL << 16 )#define A2_in (1 UL << 15 )#define A2_out (1 UL << 14 )#define A1_in (1 UL << 13 )#define A1_out (1 UL << 12 )#define AFOU (1 UL << 11 )#define PIN3 (1 UL << 6 )#define PIN2 (1 UL << 5 )#define PIN1 (1 UL << 4 )#define PIN0 (1 UL << 3 )#define ECS (1 UL << 2 )#define EC3S (1 UL << 1 )#define EC0S (1 UL << 0 )/* SSR */ #define PRQ (1 UL << 31 )#define PMA (1 UL << 30 )#define IIC_EA (1 UL << 21 )#define IIC_EW (1 UL << 20 )#define IIC_ER (1 UL << 19 )#define IIC_EL (1 UL << 18 )#define IIC_EF (1 UL << 17 )#define AF2_in (1 UL << 10 )#define AF2_out (1 UL << 9 )#define AF1_in (1 UL << 8 )#define AF1_out (1 UL << 7 )#define EC5S (1 UL << 3 )#define EC4S (1 UL << 2 )#define EC2S (1 UL << 1 )#define EC1S (1 UL << 0 )/* PCI_BT_A */ #define BurstA1_in (1 UL << 26 )#define ThreshA1_in (1 UL << 24 )#define BurstA1_out (1 UL << 18 )#define ThreshA1_out (1 UL << 16 )#define BurstA2_in (1 UL << 10 )#define ThreshA2_in (1 UL << 8 )#define BurstA2_out (1 UL << 2 )#define ThreshA2_out (1 UL << 0 )/* MC1 */ #define MRST_N (1 UL << 15 )#define EAP (1 UL << 9 )#define EI2C (1 UL << 8 )#define TR_E_A2_OUT (1 UL << 3 )#define TR_E_A2_IN (1 UL << 2 )#define TR_E_A1_OUT (1 UL << 1 )#define TR_E_A1_IN (1 UL << 0 )/* MC2 */ #define UPLD_IIC (1 UL << 0 )/* ACON1 */ #define AUDIO_MODE (1 UL << 29 )#define MAXLEVEL (1 UL << 22 )#define A1_SWAP (1 UL << 21 )#define A2_SWAP (1 UL << 20 )#define WS0_CTRL (1 UL << 18 )#define WS0_SYNC (1 UL << 16 )#define WS1_CTRL (1 UL << 14 )#define WS1_SYNC (1 UL << 12 )#define WS2_CTRL (1 UL << 10 )#define WS2_SYNC (1 UL << 8 )#define WS3_CTRL (1 UL << 6 )#define WS3_SYNC (1 UL << 4 )#define WS4_CTRL (1 UL << 2 )#define WS4_SYNC (1 UL << 0 )/* ACON2 */ #define A1_CLKSRC (1 UL << 27 )#define A2_CLKSRC (1 UL << 22 )#define INVERT_BCLK1 (1 UL << 21 )#define INVERT_BCLK2 (1 UL << 20 )#define BCLK1_OEN (1 UL << 19 )#define BCLK2_OEN (1 UL << 18 )/* IICSTA */ #define IICCC (1 UL << 8 )#define ABORT (1 UL << 7 )#define SPERR (1 UL << 6 )#define APERR (1 UL << 5 )#define DTERR (1 UL << 4 )#define DRERR (1 UL << 3 )#define AL (1 UL << 2 )#define ERR (1 UL << 1 )#define BUSY (1 UL << 0 )/* IICTFR */ #define BYTE2 (1 UL << 24 )#define BYTE1 (1 UL << 16 )#define BYTE0 (1 UL << 8 )#define ATRR2 (1 UL << 6 )#define ATRR1 (1 UL << 4 )#define ATRR0 (1 UL << 2 )#define ERR (1 UL << 1 )#define BUSY (1 UL << 0 )#define START 3 #define CONT 2 #define STOP 1 #define NOP 0
Messung V0.5 in Prozent C=96 H=95 G=95
¤ Dauer der Verarbeitung: 0.4 Sekunden
¤ *© Formatika GbR, Deutschland
