// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2016, The Linux Foundation. All rights reserved. #include <linux/module.h>#include <linux/err.h>#include <linux/kernel.h>#include <linux/delay.h>#include <linux/regulator/consumer.h>#include <linux/types.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/regmap.h>#include <sound/soc.h>#include <sound/pcm.h>#include <sound/pcm_params.h>#include <sound/tlv.h>#include <sound/jack.h>#define CDC_D_REVISION1 (0xf000)#define CDC_D_PERPH_SUBTYPE (0xf005)#define CDC_D_INT_EN_SET (0xf015)#define CDC_D_INT_EN_CLR (0xf016)#define MBHC_SWITCH_INT BIT(7)#define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6)#define MBHC_BUTTON_PRESS_DET BIT(5)#define MBHC_BUTTON_RELEASE_DET BIT(4)#define CDC_D_CDC_RST_CTL (0xf046)#define RST_CTL_DIG_SW_RST_N_MASK BIT(7)#define RST_CTL_DIG_SW_RST_N_RESET 0#define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7)#define CDC_D_CDC_TOP_CLK_CTL (0xf048)#define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3))#define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2)#define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3)#define CDC_D_CDC_ANA_CLK_CTL (0xf049)#define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)#define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)#define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1)#define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4)#define ANA_CLK_CTL_SPKR_CLK_EN BIT(4)#define ANA_CLK_CTL_TXA_CLK25_EN BIT(5)#define CDC_D_CDC_DIG_CLK_CTL (0xf04A)#define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)#define DIG_CLK_CTL_RXD2_CLK_EN BIT(1)#define DIG_CLK_CTL_RXD3_CLK_EN BIT(2)#define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3)#define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3)#define DIG_CLK_CTL_TXD_CLK_EN BIT(4)#define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6)#define DIG_CLK_CTL_NCP_CLK_EN BIT(6)#define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7)#define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7)#define CDC_D_CDC_CONN_TX1_CTL (0xf050)#define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)#define CONN_TX1_SERIAL_TX1_ADC_1 0x0#define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1#define CONN_TX1_SERIAL_TX1_ZERO 0x2#define CDC_D_CDC_CONN_TX2_CTL (0xf051)#define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)#define CONN_TX2_SERIAL_TX2_ADC_2 0x0#define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1#define CONN_TX2_SERIAL_TX2_ZERO 0x2#define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)#define CDC_D_CDC_CONN_RX1_CTL (0xf053)#define CDC_D_CDC_CONN_RX2_CTL (0xf054)#define CDC_D_CDC_CONN_RX3_CTL (0xf055)#define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)#define CDC_D_SEC_ACCESS (0xf0D0)#define CDC_D_PERPH_RESET_CTL3 (0xf0DA)#define CDC_D_PERPH_RESET_CTL4 (0xf0DB)#define CDC_A_REVISION1 (0xf100)#define CDC_A_REVISION2 (0xf101)#define CDC_A_REVISION3 (0xf102)#define CDC_A_REVISION4 (0xf103)#define CDC_A_PERPH_TYPE (0xf104)#define CDC_A_PERPH_SUBTYPE (0xf105)#define CDC_A_INT_RT_STS (0xf110)#define CDC_A_INT_SET_TYPE (0xf111)#define CDC_A_INT_POLARITY_HIGH (0xf112)#define CDC_A_INT_POLARITY_LOW (0xf113)#define CDC_A_INT_LATCHED_CLR (0xf114)#define CDC_A_INT_EN_SET (0xf115)#define CDC_A_INT_EN_CLR (0xf116)#define CDC_A_INT_LATCHED_STS (0xf118)#define CDC_A_INT_PENDING_STS (0xf119)#define CDC_A_INT_MID_SEL (0xf11A)#define CDC_A_INT_PRIORITY (0xf11B)#define CDC_A_MICB_1_EN (0xf140)#define MICB_1_EN_MICB_ENABLE BIT(7)#define MICB_1_EN_BYP_CAP_MASK BIT(6)#define MICB_1_EN_NO_EXT_BYP_CAP BIT(6)#define MICB_1_EN_EXT_BYP_CAP 0#define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5)#define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5)#define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1)#define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)#define MICB_1_EN_PULL_UP_EN_MASK BIT(4)#define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)#define MICB_1_EN_TX3_GND_SEL_TX_GND 0#define CDC_A_MICB_1_VAL (0xf141)#define MICB_MIN_VAL 1600#define MICB_STEP_SIZE 50#define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3)#define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3)#define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)#define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)#define CDC_A_MICB_1_CTL (0xf142)#define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1)#define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1)#define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5)#define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5)#define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6)#define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6)#define CDC_A_MICB_1_INT_RBIAS (0xf143)#define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7)#define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7)#define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0#define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6)#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6)#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0#define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4)#define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4)#define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0#define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3)#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3)#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0#define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1)#define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1)#define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0#define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0#define CDC_A_MICB_2_EN (0xf144)#define CDC_A_MICB_2_EN_ENABLE BIT(7)#define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5)#define CDC_A_MICB_2_PULL_DOWN_EN BIT(5)#define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)#define CDC_A_MASTER_BIAS_CTL (0xf146)#define CDC_A_MBHC_DET_CTL_1 (0xf147)#define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7)#define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6)#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5)#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5)#define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5)#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4)#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3)#define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3)#define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2)#define CDC_A_MBHC_DET_CTL_2 (0xf150)#define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6))#define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5)#define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3)#define CDC_A_HPHL_PLUG_TYPE_NO BIT(4)#define CDC_A_GND_PLUG_TYPE_NO BIT(3)#define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)#define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)#define CDC_A_MBHC_FSM_CTL (0xf151)#define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7)#define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7)#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)#define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4)#define CDC_A_MBHC_DBNC_TIMER (0xf152)#define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3)#define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)#define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)#define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)#define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)#define CDC_A_MBHC_BTN3_CTL (0xf156)#define CDC_A_MBHC_BTN4_CTL (0xf157)#define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2)#define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2)#define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5)#define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5)#define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \#define CDC_A_MBHC_RESULT_1 (0xf158)#define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)#define CDC_A_TX_1_EN (0xf160)#define CDC_A_TX_2_EN (0xf161)#define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)#define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)#define CDC_A_TX_1_2_ATEST_CTL (0xf164)#define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)#define CDC_A_TX_3_EN (0xf167)#define CDC_A_NCP_EN (0xf180)#define CDC_A_NCP_CLK (0xf181)#define CDC_A_NCP_FBCTRL (0xf183)#define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5)#define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5)#define CDC_A_NCP_BIAS (0xf184)#define CDC_A_NCP_VCTRL (0xf185)#define CDC_A_NCP_TEST (0xf186)#define CDC_A_NCP_CLIM_ADDR (0xf187)#define CDC_A_RX_CLOCK_DIVIDER (0xf190)#define CDC_A_RX_COM_OCP_CTL (0xf191)#define CDC_A_RX_COM_OCP_COUNT (0xf192)#define CDC_A_RX_COM_BIAS_DAC (0xf193)#define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7)#define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7)#define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)#define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)#define CDC_A_RX_HPH_BIAS_PA (0xf194)#define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)#define CDC_A_RX_HPH_BIAS_CNP (0xf196)#define CDC_A_RX_HPH_CNP_EN (0xf197)#define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1)#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1)#define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)#define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1)#define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1)#define CDC_A_RX_EAR_CTL (0xf19E)#define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)#define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)#define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6)#define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6)#define RX_EAR_CTL_PA_SEL_MASK BIT(7)#define RX_EAR_CTL_PA_SEL BIT(7)#define CDC_A_SPKR_DAC_CTL (0xf1B0)#define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4)#define SPKR_DAC_CTL_DAC_RESET_NORMAL 0#define CDC_A_SPKR_DRV_CTL (0xf1B2)#define SPKR_DRV_CTL_DEF_MASK 0xEF#define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7)#define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7)#define SPKR_DRV_CAL_EN BIT(6)#define SPKR_DRV_SETTLE_EN BIT(5)#define SPKR_DRV_FW_EN BIT(3)#define SPKR_DRV_BOOST_SET BIT(2)#define SPKR_DRV_CMFB_SET BIT(1)#define SPKR_DRV_GAIN_SET BIT(0)#define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \#define CDC_A_SPKR_OCP_CTL (0xf1B4)#define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)#define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)#define SPKR_PWRSTG_CTL_DAC_EN BIT(0)#define SPKR_PWRSTG_CTL_MASK 0xE0#define SPKR_PWRSTG_CTL_BBM_MASK BIT(7)#define SPKR_PWRSTG_CTL_BBM_EN BIT(7)#define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6)#define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6)#define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5)#define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5)#define CDC_A_SPKR_DRV_DBG (0xf1B7)#define CDC_A_CURRENT_LIMIT (0xf1C0)#define CDC_A_BOOST_EN_CTL (0xf1C3)#define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)#define CDC_A_SEC_ACCESS (0xf1D0)#define CDC_A_PERPH_RESET_CTL3 (0xf1DA)#define CDC_A_PERPH_RESET_CTL4 (0xf1DB)#define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\#define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET;static const char * const supply_names[] = {"vdd-cdc-io" ,"vdd-cdc-tx-rx-cx" ,#define MBHC_MAX_BUTTONS (5)struct pm8916_wcd_analog_priv {bool mbhc_btn_enabled;/* special event to detect accessory type */ int mbhc_btn0_released;bool detect_accessory_type;struct clk *mclk;struct snd_soc_component *component;struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];struct snd_soc_jack *jack;bool hphl_jack_type_normally_open;bool gnd_jack_type_normally_open;/* Voltage threshold when internal current source of 100uA is used */ /* Voltage threshold when microphone bias is ON */ unsigned int micbias1_cap_mode;unsigned int micbias2_cap_mode;unsigned int micbias_mv;static const char *const adc2_mux_text[] = { "ZERO" , "INP2" , "INP3" };static const char *const rdac2_mux_text[] = { "RX1" , "RX2" };static const char *const hph_text[] = { "ZERO" , "Switch" , };static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT(static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S" , hph_enum);static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL" , hph_enum);static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR" , hph_enum);/* ADC2 MUX */ static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT(/* RDAC2 MUX */ static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE(static const struct snd_kcontrol_new spkr_switch[] = {"Switch" , CDC_A_SPKR_DAC_CTL, 7, 1, 0)static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM("RDAC2 MUX Mux" , rdac2_mux_enum);static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM("ADC2 MUX Mux" , adc2_enum);/* Analog Gain control 0 dB to +24 dB in 6 dB steps */ static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = {"ADC1 Volume" , CDC_A_TX_1_EN, 3, 8, 0, analog_gain),"ADC2 Volume" , CDC_A_TX_2_EN, 3, 8, 0, analog_gain),"ADC3 Volume" , CDC_A_TX_3_EN, 3, 8, 0, analog_gain),static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component)struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);if (wcd->micbias_mv) {/* * Special headset needs MICBIAS as 2.7V so wait for * 50 msec for the MICBIAS to reach 2.7 volts. if (wcd->micbias_mv >= 2700)static int pm8916_wcd_analog_enable_micbias(struct snd_soc_component *component,int event, unsigned int cap_mode)switch (event) {case SND_SOC_DAPM_POST_PMU:break ;return 0;static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);switch (event) {case SND_SOC_DAPM_PRE_PMU:break ;return 0;static int pm8916_wcd_analog_enable_micbias1(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);return pm8916_wcd_analog_enable_micbias(component, event,static int pm8916_wcd_analog_enable_micbias2(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);return pm8916_wcd_analog_enable_micbias(component, event,static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv,bool micbias2_enabled)struct snd_soc_component *component = priv->component;int *vrefs, i;if (!micbias2_enabled) { /* use internal 100uA Current source */ /* Enable internal 2.2k Internal Rbias Resistor */ /* Remove pull down on MIC BIAS2 */ /* enable 100uA internal current source */ if (micbias2_enabled)else /* program vref ranges for all the buttons */ for (i = 0; i < MBHC_MAX_BUTTONS; i++) {/* split mv in to coarse parts of 100mv & fine parts of 12mv */ return 0;static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd)struct snd_soc_component *component = wcd->component;bool micbias_enabled = false ;if (wcd->hphl_jack_type_normally_open)if (wcd->gnd_jack_type_normally_open)/* enable MBHC clock */ if (snd_soc_component_read(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE)true ;if (wcd->mbhc_btn_enabled));false ;true ;static int pm8916_wcd_analog_enable_micbias_int2(struct struct snd_kcontrolint event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);switch (event) {case SND_SOC_DAPM_PRE_PMU:break ;case SND_SOC_DAPM_POST_PMU:true );break ;case SND_SOC_DAPM_POST_PMD:false );break ;return pm8916_wcd_analog_enable_micbias_int(w, kcontrol, event);static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);if (w->reg == CDC_A_TX_1_EN)else switch (event) {case SND_SOC_DAPM_PRE_PMU:if (w->reg == CDC_A_TX_2_EN)/* * Add delay of 10 ms to give sufficient time for the voltage * to shoot up and settle so that the txfe init does not * happen when the input voltage is changing too much. switch (w->reg) {case CDC_A_TX_1_EN:break ;case CDC_A_TX_2_EN:case CDC_A_TX_3_EN:break ;break ;case SND_SOC_DAPM_POST_PMU:/* * Add delay of 12 ms before deasserting the init * to reduce the tx pop break ;case SND_SOC_DAPM_POST_PMD:switch (w->reg) {case CDC_A_TX_1_EN:break ;case CDC_A_TX_2_EN:case CDC_A_TX_3_EN:break ;break ;return 0;static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);switch (event) {case SND_SOC_DAPM_PRE_PMU:break ;case SND_SOC_DAPM_POST_PMU:break ;case SND_SOC_DAPM_POST_PMD:break ;return 0;static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol,int event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);switch (event) {case SND_SOC_DAPM_PRE_PMU:break ;case SND_SOC_DAPM_POST_PMU:break ;case SND_SOC_DAPM_POST_PMD:/* Delay to reduce ear turn off pop */ break ;return 0;static const struct reg_default wcd_reg_defaults_2_0[] = {static int pm8916_wcd_analog_probe(struct snd_soc_component *component)struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);int err, reg;if (err != 0) {"failed to enable regulators (%d)\n" , err);return err;"PMIC REV: %d\t CODEC Version: %d\n" ,for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++)return 0;static void pm8916_wcd_analog_remove(struct snd_soc_component *component)struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev);static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = {"PDM_RX1" , NULL, "PDM Playback" },"PDM_RX2" , NULL, "PDM Playback" },"PDM_RX3" , NULL, "PDM Playback" },"PDM Capture" , NULL, "PDM_TX" },/* ADC Connections */ "PDM_TX" , NULL, "ADC2" },"PDM_TX" , NULL, "ADC3" },"ADC2" , NULL, "ADC2 MUX" },"ADC3" , NULL, "ADC2 MUX" },"ADC2 MUX" , "INP2" , "ADC2_INP2" },"ADC2 MUX" , "INP3" , "ADC2_INP3" },"PDM_TX" , NULL, "ADC1" },"ADC1" , NULL, "AMIC1" },"ADC2_INP2" , NULL, "AMIC2" },"ADC2_INP3" , NULL, "AMIC3" },/* RDAC Connections */ "HPHR DAC" , NULL, "RDAC2 MUX" },"RDAC2 MUX" , "RX1" , "PDM_RX1" },"RDAC2 MUX" , "RX2" , "PDM_RX2" },"HPHL DAC" , NULL, "PDM_RX1" },"PDM_RX1" , NULL, "RXD1_CLK" },"PDM_RX2" , NULL, "RXD2_CLK" },"PDM_RX3" , NULL, "RXD3_CLK" },"PDM_RX1" , NULL, "RXD_PDM_CLK" },"PDM_RX2" , NULL, "RXD_PDM_CLK" },"PDM_RX3" , NULL, "RXD_PDM_CLK" },"ADC1" , NULL, "TXD_CLK" },"ADC2" , NULL, "TXD_CLK" },"ADC3" , NULL, "TXD_CLK" },"ADC1" , NULL, "TXA_CLK25" },"ADC2" , NULL, "TXA_CLK25" },"ADC3" , NULL, "TXA_CLK25" },"PDM_RX1" , NULL, "A_MCLK2" },"PDM_RX2" , NULL, "A_MCLK2" },"PDM_RX3" , NULL, "A_MCLK2" },"PDM_TX" , NULL, "A_MCLK2" },"A_MCLK2" , NULL, "A_MCLK" },/* Earpiece (RX MIX1) */ "EAR" , NULL, "EAR_S" },"EAR_S" , "Switch" , "EAR PA" },"EAR PA" , NULL, "RX_BIAS" },"EAR PA" , NULL, "HPHL DAC" },"EAR PA" , NULL, "HPHR DAC" },"EAR PA" , NULL, "EAR CP" },/* Headset (RX MIX1 and RX MIX2) */ "HPH_L" , NULL, "HPHL PA" },"HPH_R" , NULL, "HPHR PA" },"HPHL DAC" , NULL, "EAR_HPHL_CLK" },"HPHR DAC" , NULL, "EAR_HPHR_CLK" },"CP" , NULL, "NCP_CLK" },"HPHL PA" , NULL, "HPHL" },"HPHR PA" , NULL, "HPHR" },"HPHL PA" , NULL, "CP" },"HPHL PA" , NULL, "RX_BIAS" },"HPHR PA" , NULL, "CP" },"HPHR PA" , NULL, "RX_BIAS" },"HPHL" , "Switch" , "HPHL DAC" },"HPHR" , "Switch" , "HPHR DAC" },"RX_BIAS" , NULL, "DAC_REF" },"SPK_OUT" , NULL, "SPK PA" },"SPK PA" , NULL, "RX_BIAS" },"SPK PA" , NULL, "SPKR_CLK" },"SPK PA" , NULL, "SPK DAC" },"SPK DAC" , "Switch" , "PDM_RX3" },"MIC_BIAS1" , NULL, "INT_LDO_H" },"MIC_BIAS2" , NULL, "INT_LDO_H" },"MIC_BIAS1" , NULL, "vdd-micbias" },"MIC_BIAS2" , NULL, "vdd-micbias" },"MIC BIAS External1" , NULL, "MIC_BIAS1" },"MIC BIAS Internal1" , NULL, "MIC_BIAS1" },"MIC BIAS External2" , NULL, "MIC_BIAS2" },"MIC BIAS Internal2" , NULL, "MIC_BIAS2" },"MIC BIAS Internal3" , NULL, "MIC_BIAS1" },static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = {"PDM_RX1" , NULL, 0, SND_SOC_NOPM, 0, 0),"PDM_RX2" , NULL, 0, SND_SOC_NOPM, 0, 0),"PDM_RX3" , NULL, 0, SND_SOC_NOPM, 0, 0),"PDM_TX" , NULL, 0, SND_SOC_NOPM, 0, 0),"AMIC1" ),"AMIC3" ),"AMIC2" ),"EAR" ),"HPH_L" ),"HPH_R" ),/* RX stuff */ "INT_LDO_H" , SND_SOC_NOPM, 1, 0, NULL, 0),"EAR PA" , SND_SOC_NOPM,"EAR_S" , SND_SOC_NOPM, 0, 0, &ear_mux),"EAR CP" , CDC_A_NCP_EN, 4, 0, NULL, 0),"HPHL PA" , CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),"HPHL" , SND_SOC_NOPM, 0, 0, &hphl_mux),"HPHL DAC" , CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,"HPHR PA" , CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),"HPHR" , SND_SOC_NOPM, 0, 0, &hphr_mux),"HPHR DAC" , CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,"SPK DAC" , SND_SOC_NOPM, 0, 0,/* Speaker */ "SPK_OUT" ),"SPK PA" , CDC_A_SPKR_DRV_CTL,"vdd-micbias" , 0, 0),"CP" , CDC_A_NCP_EN, 0, 0, NULL, 0),"DAC_REF" , CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),"RX_BIAS" , CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),/* TX */ "MIC_BIAS1" , CDC_A_MICB_1_EN, 7, 0,"MIC_BIAS2" , CDC_A_MICB_2_EN, 7, 0,"MIC BIAS External1" , SND_SOC_NOPM, 0, 0, NULL, 0),"MIC BIAS External2" , SND_SOC_NOPM, 0, 0, NULL, 0),"MIC BIAS Internal1" , CDC_A_MICB_1_INT_RBIAS, 7, 0,"MIC BIAS Internal2" , CDC_A_MICB_1_INT_RBIAS, 4, 0,"MIC BIAS Internal3" , CDC_A_MICB_1_INT_RBIAS, 1, 0,"ADC1" , NULL, CDC_A_TX_1_EN, 7, 0,"ADC2_INP2" , NULL, CDC_A_TX_2_EN, 7, 0,"ADC2_INP3" , NULL, CDC_A_TX_3_EN, 7, 0,"ADC2" , SND_SOC_NOPM, 0, 0, NULL, 0),"ADC3" , SND_SOC_NOPM, 0, 0, NULL, 0),"ADC2 MUX" , SND_SOC_NOPM, 0, 0, &tx_adc2_mux),"RDAC2 MUX" , SND_SOC_NOPM, 0, 0, &rdac2_mux),/* Analog path clocks */ "EAR_HPHR_CLK" , CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,"EAR_HPHL_CLK" , CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,"SPKR_CLK" , CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),"TXA_CLK25" , CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),/* Digital path clocks */ "RXD1_CLK" , CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),"RXD2_CLK" , CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),"RXD3_CLK" , CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),"TXD_CLK" , CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),"NCP_CLK" , CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),"RXD_PDM_CLK" , CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,/* System Clock source */ "A_MCLK" , CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),/* TX ADC and RX DAC Clock source. */ "A_MCLK2" , CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component,struct snd_soc_jack *jack,void *data)struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component);return 0;static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)struct pm8916_wcd_analog_priv *priv = arg;if (priv->detect_accessory_type) {struct snd_soc_component *component = priv->component;/* check if its BTN0 thats released */ if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK))true ;else {return IRQ_HANDLED;static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg)struct pm8916_wcd_analog_priv *priv = arg;struct snd_soc_component *component = priv->component;switch (btn_result) {case 0xf:break ;case 0x7:break ;case 0x3:break ;case 0x1:break ;case 0x0:/* handle BTN_0 specially for type detection */ if (!priv->detect_accessory_type)break ;default :"Unexpected button press result (%x)" , btn_result);break ;return IRQ_HANDLED;static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg)struct pm8916_wcd_analog_priv *priv = arg;struct snd_soc_component *component = priv->component;bool ins = false ;if (snd_soc_component_read(component, CDC_A_MBHC_DET_CTL_1) &true ;/* Set the detection type appropriately */ if (ins) { /* hs insertion */ bool micbias_enabled = false ;if (snd_soc_component_read(component, CDC_A_MICB_2_EN) &true ;/* * if only a btn0 press event is receive just before * insert event then its a 3 pole headphone else if * both press and release event received then its * a headset. if (priv->mbhc_btn0_released)else false ;else { /* removal */ true ;false ;return IRQ_HANDLED;static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = {"pm8916_wcd_analog_pdm_rx" ,"PDM Playback" ,"pm8916_wcd_analog_pdm_tx" ,"PDM Capture" ,static const struct snd_soc_component_driver pm8916_wcd_analog = {static int pm8916_wcd_analog_parse_dt(struct device *dev,struct pm8916_wcd_analog_priv *priv)int rval;if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap" ))else if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap" ))else "qcom,micbias-lvl" ,if (of_property_read_bool(dev->of_node,"qcom,hphl-jack-type-normally-open" ))true ;else false ;if (of_property_read_bool(dev->of_node,"qcom,gnd-jack-type-normally-open" ))true ;else false ;true ;"qcom,mbhc-vthreshold-low" ,if (rval < 0) {false ;else {"qcom,mbhc-vthreshold-high" ,if (rval < 0)false ;if (!priv->mbhc_btn_enabled)"DT property missing, MBHC btn detection disabled\n" );return 0;static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev)struct pm8916_wcd_analog_priv *priv;struct device *dev = &pdev->dev;int ret, i, irq;sizeof (*priv), GFP_KERNEL);if (!priv)return -ENOMEM;if (ret < 0)return ret;for (i = 0; i < ARRAY_SIZE(supply_names); i++)if (ret) {"Failed to get regulator supplies %d\n" , ret);return ret;"mbhc_switch_int" );if (irq < 0)return irq;"mbhc switch irq" , priv);if (ret) {"cannot request mbhc switch irq\n" );return ret;if (priv->mbhc_btn_enabled) {"mbhc_but_press_det" );if (irq < 0)return irq;"mbhc btn press irq" , priv);if (ret) {"cannot request mbhc button press irq\n" );return ret;"mbhc_but_rel_det" );if (irq < 0)return irq;"mbhc btn release irq" , priv);if (ret) {"cannot request mbhc button release irq\n" );return ret;return devm_snd_soc_register_component(dev, &pm8916_wcd_analog,static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = {"qcom,pm8916-wcd-analog-codec" , },static struct platform_driver pm8916_wcd_analog_spmi_driver = {"qcom,pm8916-wcd-spmi-codec" ,"Srinivas Kandagatla " );"PMIC PM8916 WCD Analog Codec driver" );"GPL v2" );
Messung V0.5 C=95 H=95 G=94
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