// SPDX-License-Identifier: GPL-2.0-only /* ALSA SoC TLV320AIC3X codec driver * * Author : Vladimir Barinov , < vbarinov @ embeddedalley . com > * Copyright : ( C ) 2007 MontaVista Software , Inc . , < source @ mvista . com > * * Based on sound / soc / codecs / wm8753 . c by Liam Girdwood * * Notes : * The AIC3X is a driver for a low power stereo audio * codecs aic31 , aic32 , aic33 , aic3007 . * * It supports full aic33 codec functionality . * The compatibility with aic32 , aic31 and aic3007 is as follows : * aic32 / aic3007 | aic31 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * MONO_LOUT - > N / A | MONO_LOUT - > N / A * | IN1L - > LINE1L * | IN1R - > LINE1R * | IN2L - > LINE2L * | IN2R - > LINE2R * | MIC3L / R - > N / A * truncated internal functionality in * accordance with documentation * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * Hence the machine layer should disable unsupported inputs / outputs by * snd_soc_dapm_disable_pin ( codec , " MONO_LOUT " ) , etc . #include <linux/module.h>#include <linux/moduleparam.h>#include <linux/init.h>#include <linux/delay.h>#include <linux/err.h>#include <linux/pm.h>#include <linux/i2c.h>#include <linux/gpio/consumer.h>#include <linux/regulator/consumer.h>#include <linux/of.h>#include <linux/slab.h>#include <sound/core.h>#include <sound/pcm.h>#include <sound/pcm_params.h>#include <sound/soc.h>#include <sound/initval.h>#include <sound/tlv.h>#include "tlv320aic3x.h" #define AIC3X_NUM_SUPPLIES 4 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {"IOVDD" , /* I/O Voltage */ "DVDD" , /* Digital Core Voltage */ "AVDD" , /* Analog DAC Voltage */ "DRVDD" , /* ADC Analog and Output Driver Voltage */ struct aic3x_priv;struct aic3x_disable_nb {struct notifier_block nb;struct aic3x_priv *aic3x;struct aic3x_setup_data {unsigned int gpio_func[2 ];/* codec private data */ struct aic3x_priv {struct snd_soc_component *component;struct regmap *regmap;struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];struct aic3x_setup_data *setup;unsigned int sysclk;unsigned int dai_fmt;unsigned int tdm_delay;unsigned int slot_width;int master;struct gpio_desc *gpio_reset;bool shared_reset;int power;/* Selects the micbias voltage */ enum aic3x_micbias_voltage micbias_vg;/* Output Common-Mode Voltage */ static const struct reg_default aic3x_reg[] = {0 , 0 x00 }, { 1 , 0 x00 }, { 2 , 0 x00 }, { 3 , 0 x10 },4 , 0 x04 }, { 5 , 0 x00 }, { 6 , 0 x00 }, { 7 , 0 x00 },8 , 0 x00 }, { 9 , 0 x00 }, { 10 , 0 x00 }, { 11 , 0 x01 },12 , 0 x00 }, { 13 , 0 x00 }, { 14 , 0 x00 }, { 15 , 0 x80 },16 , 0 x80 }, { 17 , 0 xff }, { 18 , 0 xff }, { 19 , 0 x78 },20 , 0 x78 }, { 21 , 0 x78 }, { 22 , 0 x78 }, { 23 , 0 x78 },24 , 0 x78 }, { 25 , 0 x00 }, { 26 , 0 x00 }, { 27 , 0 xfe },28 , 0 x00 }, { 29 , 0 x00 }, { 30 , 0 xfe }, { 31 , 0 x00 },32 , 0 x18 }, { 33 , 0 x18 }, { 34 , 0 x00 }, { 35 , 0 x00 },36 , 0 x00 }, { 37 , 0 x00 }, { 38 , 0 x00 }, { 39 , 0 x00 },40 , 0 x00 }, { 41 , 0 x00 }, { 42 , 0 x00 }, { 43 , 0 x80 },44 , 0 x80 }, { 45 , 0 x00 }, { 46 , 0 x00 }, { 47 , 0 x00 },48 , 0 x00 }, { 49 , 0 x00 }, { 50 , 0 x00 }, { 51 , 0 x04 },52 , 0 x00 }, { 53 , 0 x00 }, { 54 , 0 x00 }, { 55 , 0 x00 },56 , 0 x00 }, { 57 , 0 x00 }, { 58 , 0 x04 }, { 59 , 0 x00 },60 , 0 x00 }, { 61 , 0 x00 }, { 62 , 0 x00 }, { 63 , 0 x00 },64 , 0 x00 }, { 65 , 0 x04 }, { 66 , 0 x00 }, { 67 , 0 x00 },68 , 0 x00 }, { 69 , 0 x00 }, { 70 , 0 x00 }, { 71 , 0 x00 },72 , 0 x04 }, { 73 , 0 x00 }, { 74 , 0 x00 }, { 75 , 0 x00 },76 , 0 x00 }, { 77 , 0 x00 }, { 78 , 0 x00 }, { 79 , 0 x00 },80 , 0 x00 }, { 81 , 0 x00 }, { 82 , 0 x00 }, { 83 , 0 x00 },84 , 0 x00 }, { 85 , 0 x00 }, { 86 , 0 x00 }, { 87 , 0 x00 },88 , 0 x00 }, { 89 , 0 x00 }, { 90 , 0 x00 }, { 91 , 0 x00 },92 , 0 x00 }, { 93 , 0 x00 }, { 94 , 0 x00 }, { 95 , 0 x00 },96 , 0 x00 }, { 97 , 0 x00 }, { 98 , 0 x00 }, { 99 , 0 x00 },100 , 0 x00 }, { 101 , 0 x00 }, { 102 , 0 x02 }, { 103 , 0 x00 },104 , 0 x00 }, { 105 , 0 x00 }, { 106 , 0 x00 }, { 107 , 0 x00 },108 , 0 x00 }, { 109 , 0 x00 },static const struct reg_sequence aic3007_class_d[] = {/* Class-D speaker driver init; datasheet p. 46 */ 0 x0D },0 xD, 0 x0D },0 x8, 0 x5C },0 x8, 0 x5D },0 x8, 0 x5C },0 x00 },static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)switch (reg) {case AIC3X_RESET:return true ;default :return false ;const struct regmap_config aic3x_regmap = {#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \/* * All input lines are connected when ! 0 xf and disconnected with 0 xf bit field , * so we have to use specific dapm_put call for input mixer static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol)struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);struct soc_mixer_control *mc =struct soc_mixer_control *)kcontrol->private_value;unsigned int reg = mc->reg;unsigned int shift = mc->shift;int max = mc->max;unsigned int mask = (1 << fls(max)) - 1 ;unsigned int invert = mc->invert;unsigned short val;struct snd_soc_dapm_update update = {};int connect, change;0 ] & mask);0 xf;if (val)if (invert)if (change) {return change;/* * mic bias power on / off share the same register bits with * output voltage of mic bias . when power on mic bias , we * need reclaim it to voltage value . * 0 x0 = Powered off * 0 x1 = MICBIAS output is powered to 2 . 0 V , * 0 x2 = MICBIAS output is powered to 2 . 5 V * 0 x3 = MICBIAS output is connected to AVDD static int mic_bias_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol, int event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);switch (event) {case SND_SOC_DAPM_POST_PMU:/* change mic bias voltage to user defined */ break ;case SND_SOC_DAPM_PRE_PMD:0 );break ;return 0 ;static const char * const aic3x_left_dac_mux[] = {"DAC_L1" , "DAC_L3" , "DAC_L2" };static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6 ,static const char * const aic3x_right_dac_mux[] = {"DAC_R1" , "DAC_R3" , "DAC_R2" };static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4 ,static const char * const aic3x_left_hpcom_mux[] = {"differential of HPLOUT" , "constant VCM" , "single-ended" };static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4 ,static const char * const aic3x_right_hpcom_mux[] = {"differential of HPROUT" , "constant VCM" , "single-ended" ,"differential of HPLCOM" , "external feedback" };static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3 ,static const char * const aic3x_linein_mode_mux[] = {"single-ended" , "differential" };static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7 ,static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7 ,static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7 ,static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7 ,static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7 ,static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7 ,static const char * const aic3x_adc_hpf[] = {"Disabled" , "0.0045xFs" , "0.0125xFs" , "0.025xFs" };static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6 , 4 ,static const char * const aic3x_agc_level[] = {"-5.5dB" , "-8dB" , "-10dB" , "-12dB" ,"-14dB" , "-17dB" , "-20dB" , "-24dB" };static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4 ,static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4 ,static const char * const aic3x_agc_attack[] = {"8ms" , "11ms" , "16ms" , "20ms" };static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2 ,static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2 ,static const char * const aic3x_agc_decay[] = {"100ms" , "200ms" , "400ms" , "500ms" };static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0 ,static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0 ,static const char * const aic3x_poweron_time[] = {"0us" , "10us" , "100us" , "1ms" , "10ms" , "50ms" ,"100ms" , "200ms" , "400ms" , "800ms" , "2s" , "4s" };static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4 ,static const char * const aic3x_rampup_step[] = { "0ms" , "1ms" , "2ms" , "4ms" };static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2 ,/* * DAC digital volumes . From - 63 . 5 to 0 dB in 0 . 5 dB steps static DECLARE_TLV_DB_SCALE(dac_tlv, -6350 , 50 , 0 );/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ static DECLARE_TLV_DB_SCALE(adc_tlv, 0 , 50 , 0 );/* * Output stage volumes . From - 78 . 3 to 0 dB . Muted below - 78 . 3 dB . * Step size is approximately 0 . 5 dB over most of the scale but increasing * near the very low levels . * Define dB scale so that it is mostly correct for range about - 55 to 0 dB * but having increasing dB difference below that ( and where it doesn ' t count * so much ) . This setting shows - 50 dB ( actual is - 50 . 3 dB ) for register * value 100 and - 58 . 5 dB ( actual is - 78 . 3 dB ) for register value 117 . static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900 , 50 , 1 );/* Output volumes. From 0 to 9 dB in 1 dB steps */ static const DECLARE_TLV_DB_SCALE(out_tlv, 0 , 100 , 0 );static const struct snd_kcontrol_new aic3x_snd_controls[] = {/* Output */ "PCM Playback Volume" ,0 , 0 x7f, 1 , dac_tlv),/* * Output controls that map to output mixer switches . Note these are * only for swapped L - to - R and R - to - L routes . See below stereo controls * for direct L - to - L and R - to - R routes . "Left Line Mixer PGAR Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Left Line Mixer DACR1 Playback Volume" ,0 , 118 , 1 , output_stage_tlv),"Right Line Mixer PGAL Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Right Line Mixer DACL1 Playback Volume" ,0 , 118 , 1 , output_stage_tlv),"Left HP Mixer PGAR Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Left HP Mixer DACR1 Playback Volume" ,0 , 118 , 1 , output_stage_tlv),"Right HP Mixer PGAL Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Right HP Mixer DACL1 Playback Volume" ,0 , 118 , 1 , output_stage_tlv),"Left HPCOM Mixer PGAR Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Left HPCOM Mixer DACR1 Playback Volume" ,0 , 118 , 1 , output_stage_tlv),"Right HPCOM Mixer PGAL Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Right HPCOM Mixer DACL1 Playback Volume" ,0 , 118 , 1 , output_stage_tlv),/* Stereo output controls for direct L-to-L and R-to-R routes */ "Line PGA Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Line DAC Playback Volume" ,0 , 118 , 1 , output_stage_tlv),"HP PGA Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"HP DAC Playback Volume" ,0 , 118 , 1 , output_stage_tlv),"HPCOM PGA Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"HPCOM DAC Playback Volume" ,0 , 118 , 1 , output_stage_tlv),/* Output pin controls */ "Line Playback Volume" , LLOPM_CTRL, RLOPM_CTRL, 4 ,9 , 0 , out_tlv),"Line Playback Switch" , LLOPM_CTRL, RLOPM_CTRL, 3 ,0 x01, 0 ),"HP Playback Volume" , HPLOUT_CTRL, HPROUT_CTRL, 4 ,9 , 0 , out_tlv),"HP Playback Switch" , HPLOUT_CTRL, HPROUT_CTRL, 3 ,0 x01, 0 ),"HPCOM Playback Volume" , HPLCOM_CTRL, HPRCOM_CTRL,4 , 9 , 0 , out_tlv),"HPCOM Playback Switch" , HPLCOM_CTRL, HPRCOM_CTRL, 3 ,0 x01, 0 ),/* * Note : enable Automatic input Gain Controller with care . It can * adjust PGA to max value when ADC is on and will never go back . "AGC Switch" , LAGC_CTRL_A, RAGC_CTRL_A, 7 , 0 x01, 0 ),"Left AGC Target level" , aic3x_lagc_level_enum),"Right AGC Target level" , aic3x_ragc_level_enum),"Left AGC Attack time" , aic3x_lagc_attack_enum),"Right AGC Attack time" , aic3x_ragc_attack_enum),"Left AGC Decay time" , aic3x_lagc_decay_enum),"Right AGC Decay time" , aic3x_ragc_decay_enum),/* De-emphasis */ "De-emphasis Switch" , AIC3X_CODEC_DFILT_CTRL, 2 , 0 , 0 x01, 0 ),/* Input */ "PGA Capture Volume" , LADC_VOL, RADC_VOL,0 , 119 , 0 , adc_tlv),"PGA Capture Switch" , LADC_VOL, RADC_VOL, 7 , 0 x01, 1 ),"ADC HPF Cut-off" , aic3x_adc_hpf_enum),/* Pop reduction */ "Output Driver Power-On time" , aic3x_poweron_time_enum),"Output Driver Ramp-up step" , aic3x_rampup_step_enum),/* For other than tlv320aic3104 */ static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {/* * Output controls that map to output mixer switches . Note these are * only for swapped L - to - R and R - to - L routes . See below stereo controls * for direct L - to - L and R - to - R routes . "Left Line Mixer Line2R Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Right Line Mixer Line2L Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Left HP Mixer Line2R Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Right HP Mixer Line2L Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Left HPCOM Mixer Line2R Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Right HPCOM Mixer Line2L Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),/* Stereo output controls for direct L-to-L and R-to-R routes */ "Line Line2 Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"HP Line2 Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"HPCOM Line2 Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),static const struct snd_kcontrol_new aic3x_mono_controls[] = {"Mono Line2 Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Mono PGA Bypass Volume" ,0 , 118 , 1 , output_stage_tlv),"Mono DAC Playback Volume" ,0 , 118 , 1 , output_stage_tlv),"Mono Playback Switch" , MONOLOPM_CTRL, 3 , 0 x01, 0 ),"Mono Playback Volume" , MONOLOPM_CTRL, 4 , 9 , 0 ,/* * Class - D amplifier gain . From 0 to 18 dB in 6 dB steps static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0 , 600 , 0 );static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl ="Class-D Playback Volume" , CLASSD_CTRL, 6 , 4 , 3 , 0 , classd_amp_tlv);/* Left DAC Mux */ static const struct snd_kcontrol_new aic3x_left_dac_mux_controls ="Route" , aic3x_left_dac_enum);/* Right DAC Mux */ static const struct snd_kcontrol_new aic3x_right_dac_mux_controls ="Route" , aic3x_right_dac_enum);/* Left HPCOM Mux */ static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls ="Route" , aic3x_left_hpcom_enum);/* Right HPCOM Mux */ static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls ="Route" , aic3x_right_hpcom_enum);/* Left Line Mixer */ static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {"PGAL Bypass Switch" , PGAL_2_LLOPM_VOL, 7 , 1 , 0 ),"DACL1 Switch" , DACL1_2_LLOPM_VOL, 7 , 1 , 0 ),"PGAR Bypass Switch" , PGAR_2_LLOPM_VOL, 7 , 1 , 0 ),"DACR1 Switch" , DACR1_2_LLOPM_VOL, 7 , 1 , 0 ),/* Not on tlv320aic3104 */ "Line2L Bypass Switch" , LINE2L_2_LLOPM_VOL, 7 , 1 , 0 ),"Line2R Bypass Switch" , LINE2R_2_LLOPM_VOL, 7 , 1 , 0 ),/* Right Line Mixer */ static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {"PGAL Bypass Switch" , PGAL_2_RLOPM_VOL, 7 , 1 , 0 ),"DACL1 Switch" , DACL1_2_RLOPM_VOL, 7 , 1 , 0 ),"PGAR Bypass Switch" , PGAR_2_RLOPM_VOL, 7 , 1 , 0 ),"DACR1 Switch" , DACR1_2_RLOPM_VOL, 7 , 1 , 0 ),/* Not on tlv320aic3104 */ "Line2L Bypass Switch" , LINE2L_2_RLOPM_VOL, 7 , 1 , 0 ),"Line2R Bypass Switch" , LINE2R_2_RLOPM_VOL, 7 , 1 , 0 ),/* Mono Mixer */ static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {"Line2L Bypass Switch" , LINE2L_2_MONOLOPM_VOL, 7 , 1 , 0 ),"PGAL Bypass Switch" , PGAL_2_MONOLOPM_VOL, 7 , 1 , 0 ),"DACL1 Switch" , DACL1_2_MONOLOPM_VOL, 7 , 1 , 0 ),"Line2R Bypass Switch" , LINE2R_2_MONOLOPM_VOL, 7 , 1 , 0 ),"PGAR Bypass Switch" , PGAR_2_MONOLOPM_VOL, 7 , 1 , 0 ),"DACR1 Switch" , DACR1_2_MONOLOPM_VOL, 7 , 1 , 0 ),/* Left HP Mixer */ static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {"PGAL Bypass Switch" , PGAL_2_HPLOUT_VOL, 7 , 1 , 0 ),"DACL1 Switch" , DACL1_2_HPLOUT_VOL, 7 , 1 , 0 ),"PGAR Bypass Switch" , PGAR_2_HPLOUT_VOL, 7 , 1 , 0 ),"DACR1 Switch" , DACR1_2_HPLOUT_VOL, 7 , 1 , 0 ),/* Not on tlv320aic3104 */ "Line2L Bypass Switch" , LINE2L_2_HPLOUT_VOL, 7 , 1 , 0 ),"Line2R Bypass Switch" , LINE2R_2_HPLOUT_VOL, 7 , 1 , 0 ),/* Right HP Mixer */ static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {"PGAL Bypass Switch" , PGAL_2_HPROUT_VOL, 7 , 1 , 0 ),"DACL1 Switch" , DACL1_2_HPROUT_VOL, 7 , 1 , 0 ),"PGAR Bypass Switch" , PGAR_2_HPROUT_VOL, 7 , 1 , 0 ),"DACR1 Switch" , DACR1_2_HPROUT_VOL, 7 , 1 , 0 ),/* Not on tlv320aic3104 */ "Line2L Bypass Switch" , LINE2L_2_HPROUT_VOL, 7 , 1 , 0 ),"Line2R Bypass Switch" , LINE2R_2_HPROUT_VOL, 7 , 1 , 0 ),/* Left HPCOM Mixer */ static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {"PGAL Bypass Switch" , PGAL_2_HPLCOM_VOL, 7 , 1 , 0 ),"DACL1 Switch" , DACL1_2_HPLCOM_VOL, 7 , 1 , 0 ),"PGAR Bypass Switch" , PGAR_2_HPLCOM_VOL, 7 , 1 , 0 ),"DACR1 Switch" , DACR1_2_HPLCOM_VOL, 7 , 1 , 0 ),/* Not on tlv320aic3104 */ "Line2L Bypass Switch" , LINE2L_2_HPLCOM_VOL, 7 , 1 , 0 ),"Line2R Bypass Switch" , LINE2R_2_HPLCOM_VOL, 7 , 1 , 0 ),/* Right HPCOM Mixer */ static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {"PGAL Bypass Switch" , PGAL_2_HPRCOM_VOL, 7 , 1 , 0 ),"DACL1 Switch" , DACL1_2_HPRCOM_VOL, 7 , 1 , 0 ),"PGAR Bypass Switch" , PGAR_2_HPRCOM_VOL, 7 , 1 , 0 ),"DACR1 Switch" , DACR1_2_HPRCOM_VOL, 7 , 1 , 0 ),/* Not on tlv320aic3104 */ "Line2L Bypass Switch" , LINE2L_2_HPRCOM_VOL, 7 , 1 , 0 ),"Line2R Bypass Switch" , LINE2R_2_HPRCOM_VOL, 7 , 1 , 0 ),/* Left PGA Mixer */ static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {"Line1L Switch" , LINE1L_2_LADC_CTRL, 3 , 1 , 1 ),"Line1R Switch" , LINE1R_2_LADC_CTRL, 3 , 1 , 1 ),"Line2L Switch" , LINE2L_2_LADC_CTRL, 3 , 1 , 1 ),"Mic3L Switch" , MIC3LR_2_LADC_CTRL, 4 , 1 , 1 ),"Mic3R Switch" , MIC3LR_2_LADC_CTRL, 0 , 1 , 1 ),/* Right PGA Mixer */ static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {"Line1R Switch" , LINE1R_2_RADC_CTRL, 3 , 1 , 1 ),"Line1L Switch" , LINE1L_2_RADC_CTRL, 3 , 1 , 1 ),"Line2R Switch" , LINE2R_2_RADC_CTRL, 3 , 1 , 1 ),"Mic3L Switch" , MIC3LR_2_RADC_CTRL, 4 , 1 , 1 ),"Mic3R Switch" , MIC3LR_2_RADC_CTRL, 0 , 1 , 1 ),/* Left PGA Mixer for tlv320aic3104 */ static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {"Line1L Switch" , LINE1L_2_LADC_CTRL, 3 , 1 , 1 ),"Line1R Switch" , LINE1R_2_LADC_CTRL, 3 , 1 , 1 ),"Mic2L Switch" , MIC3LR_2_LADC_CTRL, 4 , 1 , 1 ),"Mic2R Switch" , MIC3LR_2_LADC_CTRL, 0 , 1 , 1 ),/* Right PGA Mixer for tlv320aic3104 */ static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {"Line1R Switch" , LINE1R_2_RADC_CTRL, 3 , 1 , 1 ),"Line1L Switch" , LINE1L_2_RADC_CTRL, 3 , 1 , 1 ),"Mic2L Switch" , MIC3LR_2_RADC_CTRL, 4 , 1 , 1 ),"Mic2R Switch" , MIC3LR_2_RADC_CTRL, 0 , 1 , 1 ),/* Left Line1 Mux */ static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls ="Route" , aic3x_line1l_2_l_enum);static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls ="Route" , aic3x_line1l_2_r_enum);/* Right Line1 Mux */ static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls ="Route" , aic3x_line1r_2_r_enum);static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls ="Route" , aic3x_line1r_2_l_enum);/* Left Line2 Mux */ static const struct snd_kcontrol_new aic3x_left_line2_mux_controls ="Route" , aic3x_line2l_2_ldac_enum);/* Right Line2 Mux */ static const struct snd_kcontrol_new aic3x_right_line2_mux_controls ="Route" , aic3x_line2r_2_rdac_enum);static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {/* Left DAC to Left Outputs */ "Left DAC" , "Left Playback" , DAC_PWR, 7 , 0 ),"Left DAC Mux" , SND_SOC_NOPM, 0 , 0 ,"Left HPCOM Mux" , SND_SOC_NOPM, 0 , 0 ,"Left Line Out" , LLOPM_CTRL, 0 , 0 , NULL, 0 ),"Left HP Out" , HPLOUT_CTRL, 0 , 0 , NULL, 0 ),"Left HP Com" , HPLCOM_CTRL, 0 , 0 , NULL, 0 ),/* Right DAC to Right Outputs */ "Right DAC" , "Right Playback" , DAC_PWR, 6 , 0 ),"Right DAC Mux" , SND_SOC_NOPM, 0 , 0 ,"Right HPCOM Mux" , SND_SOC_NOPM, 0 , 0 ,"Right Line Out" , RLOPM_CTRL, 0 , 0 , NULL, 0 ),"Right HP Out" , HPROUT_CTRL, 0 , 0 , NULL, 0 ),"Right HP Com" , HPRCOM_CTRL, 0 , 0 , NULL, 0 ),/* Inputs to Left ADC */ "Left ADC" , "Left Capture" , LINE1L_2_LADC_CTRL, 2 , 0 ),"Left Line1L Mux" , SND_SOC_NOPM, 0 , 0 ,"Left Line1R Mux" , SND_SOC_NOPM, 0 , 0 ,/* Inputs to Right ADC */ "Right ADC" , "Right Capture" ,2 , 0 ),"Right Line1L Mux" , SND_SOC_NOPM, 0 , 0 ,"Right Line1R Mux" , SND_SOC_NOPM, 0 , 0 ,/* Mic Bias */ "Mic Bias" , MICBIAS_CTRL, 6 , 0 ,"LLOUT" ),"RLOUT" ),"HPLOUT" ),"HPROUT" ),"HPLCOM" ),"HPRCOM" ),"LINE1L" ),"LINE1R" ),/* * Virtual output pin to detection block inside codec . This can be * used to keep codec bias on if gpio or detection features are needed . * Force pin on or construct a path with an input jack and mic bias * widgets . "Detection" ),/* For other than tlv320aic3104 */ static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {/* Inputs to Left ADC */ "Left PGA Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"Left Line2L Mux" , SND_SOC_NOPM, 0 , 0 ,/* Inputs to Right ADC */ "Right PGA Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"Right Line2R Mux" , SND_SOC_NOPM, 0 , 0 ,/* * Not a real mic bias widget but similar function . This is for dynamic * control of GPIO1 digital mic modulator clock output function when * using digital mic . "GPIO1 dmic modclk" ,4 , 0 xf,/* * Also similar function like mic bias . Selects digital mic with * configurable oversampling rate instead of ADC converter . "DMic Rate 128" ,0 , 3 , 1 , 0 ),"DMic Rate 64" ,0 , 3 , 2 , 0 ),"DMic Rate 32" ,0 , 3 , 3 , 0 ),/* Output mixers */ "Left Line Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"Right Line Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"Left HP Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"Right HP Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"Left HPCOM Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"Right HPCOM Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"MIC3L" ),"MIC3R" ),"LINE2L" ),"LINE2R" ),/* For tlv320aic3104 */ static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {/* Inputs to Left ADC */ "Left PGA Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],/* Inputs to Right ADC */ "Right PGA Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],/* Output mixers */ "Left Line Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],2 ),"Right Line Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],2 ),"Left HP Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],2 ),"Right HP Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],2 ),"Left HPCOM Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],2 ),"Right HPCOM Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],2 ),"MIC2L" ),"MIC2R" ),static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {/* Mono Output */ "Mono Out" , MONOLOPM_CTRL, 0 , 0 , NULL, 0 ),"Mono Mixer" , SND_SOC_NOPM, 0 , 0 ,0 ],"MONO_LOUT" ),static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {/* Class-D outputs */ "Left Class-D Out" , CLASSD_CTRL, 3 , 0 , NULL, 0 ),"Right Class-D Out" , CLASSD_CTRL, 2 , 0 , NULL, 0 ),"SPOP" ),"SPOM" ),static const struct snd_soc_dapm_route intercon[] = {/* Left Input */ "Left Line1L Mux" , "single-ended" , "LINE1L" },"Left Line1L Mux" , "differential" , "LINE1L" },"Left Line1R Mux" , "single-ended" , "LINE1R" },"Left Line1R Mux" , "differential" , "LINE1R" },"Left PGA Mixer" , "Line1L Switch" , "Left Line1L Mux" },"Left PGA Mixer" , "Line1R Switch" , "Left Line1R Mux" },"Left ADC" , NULL, "Left PGA Mixer" },/* Right Input */ "Right Line1R Mux" , "single-ended" , "LINE1R" },"Right Line1R Mux" , "differential" , "LINE1R" },"Right Line1L Mux" , "single-ended" , "LINE1L" },"Right Line1L Mux" , "differential" , "LINE1L" },"Right PGA Mixer" , "Line1L Switch" , "Right Line1L Mux" },"Right PGA Mixer" , "Line1R Switch" , "Right Line1R Mux" },"Right ADC" , NULL, "Right PGA Mixer" },/* Left DAC Output */ "Left DAC Mux" , "DAC_L1" , "Left DAC" },"Left DAC Mux" , "DAC_L2" , "Left DAC" },"Left DAC Mux" , "DAC_L3" , "Left DAC" },/* Right DAC Output */ "Right DAC Mux" , "DAC_R1" , "Right DAC" },"Right DAC Mux" , "DAC_R2" , "Right DAC" },"Right DAC Mux" , "DAC_R3" , "Right DAC" },/* Left Line Output */ "Left Line Mixer" , "PGAL Bypass Switch" , "Left PGA Mixer" },"Left Line Mixer" , "DACL1 Switch" , "Left DAC Mux" },"Left Line Mixer" , "PGAR Bypass Switch" , "Right PGA Mixer" },"Left Line Mixer" , "DACR1 Switch" , "Right DAC Mux" },"Left Line Out" , NULL, "Left Line Mixer" },"Left Line Out" , NULL, "Left DAC Mux" },"LLOUT" , NULL, "Left Line Out" },/* Right Line Output */ "Right Line Mixer" , "PGAL Bypass Switch" , "Left PGA Mixer" },"Right Line Mixer" , "DACL1 Switch" , "Left DAC Mux" },"Right Line Mixer" , "PGAR Bypass Switch" , "Right PGA Mixer" },"Right Line Mixer" , "DACR1 Switch" , "Right DAC Mux" },"Right Line Out" , NULL, "Right Line Mixer" },"Right Line Out" , NULL, "Right DAC Mux" },"RLOUT" , NULL, "Right Line Out" },/* Left HP Output */ "Left HP Mixer" , "PGAL Bypass Switch" , "Left PGA Mixer" },"Left HP Mixer" , "DACL1 Switch" , "Left DAC Mux" },"Left HP Mixer" , "PGAR Bypass Switch" , "Right PGA Mixer" },"Left HP Mixer" , "DACR1 Switch" , "Right DAC Mux" },"Left HP Out" , NULL, "Left HP Mixer" },"Left HP Out" , NULL, "Left DAC Mux" },"HPLOUT" , NULL, "Left HP Out" },/* Right HP Output */ "Right HP Mixer" , "PGAL Bypass Switch" , "Left PGA Mixer" },"Right HP Mixer" , "DACL1 Switch" , "Left DAC Mux" },"Right HP Mixer" , "PGAR Bypass Switch" , "Right PGA Mixer" },"Right HP Mixer" , "DACR1 Switch" , "Right DAC Mux" },"Right HP Out" , NULL, "Right HP Mixer" },"Right HP Out" , NULL, "Right DAC Mux" },"HPROUT" , NULL, "Right HP Out" },/* Left HPCOM Output */ "Left HPCOM Mixer" , "PGAL Bypass Switch" , "Left PGA Mixer" },"Left HPCOM Mixer" , "DACL1 Switch" , "Left DAC Mux" },"Left HPCOM Mixer" , "PGAR Bypass Switch" , "Right PGA Mixer" },"Left HPCOM Mixer" , "DACR1 Switch" , "Right DAC Mux" },"Left HPCOM Mux" , "differential of HPLOUT" , "Left HP Mixer" },"Left HPCOM Mux" , "constant VCM" , "Left HPCOM Mixer" },"Left HPCOM Mux" , "single-ended" , "Left HPCOM Mixer" },"Left HP Com" , NULL, "Left HPCOM Mux" },"HPLCOM" , NULL, "Left HP Com" },/* Right HPCOM Output */ "Right HPCOM Mixer" , "PGAL Bypass Switch" , "Left PGA Mixer" },"Right HPCOM Mixer" , "DACL1 Switch" , "Left DAC Mux" },"Right HPCOM Mixer" , "PGAR Bypass Switch" , "Right PGA Mixer" },"Right HPCOM Mixer" , "DACR1 Switch" , "Right DAC Mux" },"Right HPCOM Mux" , "differential of HPROUT" , "Right HP Mixer" },"Right HPCOM Mux" , "constant VCM" , "Right HPCOM Mixer" },"Right HPCOM Mux" , "single-ended" , "Right HPCOM Mixer" },"Right HPCOM Mux" , "differential of HPLCOM" , "Left HPCOM Mixer" },"Right HPCOM Mux" , "external feedback" , "Right HPCOM Mixer" },"Right HP Com" , NULL, "Right HPCOM Mux" },"HPRCOM" , NULL, "Right HP Com" },/* For other than tlv320aic3104 */ static const struct snd_soc_dapm_route intercon_extra[] = {/* Left Input */ "Left Line2L Mux" , "single-ended" , "LINE2L" },"Left Line2L Mux" , "differential" , "LINE2L" },"Left PGA Mixer" , "Line2L Switch" , "Left Line2L Mux" },"Left PGA Mixer" , "Mic3L Switch" , "MIC3L" },"Left PGA Mixer" , "Mic3R Switch" , "MIC3R" },"Left ADC" , NULL, "GPIO1 dmic modclk" },/* Right Input */ "Right Line2R Mux" , "single-ended" , "LINE2R" },"Right Line2R Mux" , "differential" , "LINE2R" },"Right PGA Mixer" , "Line2R Switch" , "Right Line2R Mux" },"Right PGA Mixer" , "Mic3L Switch" , "MIC3L" },"Right PGA Mixer" , "Mic3R Switch" , "MIC3R" },"Right ADC" , NULL, "GPIO1 dmic modclk" },/* * Logical path between digital mic enable and GPIO1 modulator clock * output function "GPIO1 dmic modclk" , NULL, "DMic Rate 128" },"GPIO1 dmic modclk" , NULL, "DMic Rate 64" },"GPIO1 dmic modclk" , NULL, "DMic Rate 32" },/* Left Line Output */ "Left Line Mixer" , "Line2L Bypass Switch" , "Left Line2L Mux" },"Left Line Mixer" , "Line2R Bypass Switch" , "Right Line2R Mux" },/* Right Line Output */ "Right Line Mixer" , "Line2L Bypass Switch" , "Left Line2L Mux" },"Right Line Mixer" , "Line2R Bypass Switch" , "Right Line2R Mux" },/* Left HP Output */ "Left HP Mixer" , "Line2L Bypass Switch" , "Left Line2L Mux" },"Left HP Mixer" , "Line2R Bypass Switch" , "Right Line2R Mux" },/* Right HP Output */ "Right HP Mixer" , "Line2L Bypass Switch" , "Left Line2L Mux" },"Right HP Mixer" , "Line2R Bypass Switch" , "Right Line2R Mux" },/* Left HPCOM Output */ "Left HPCOM Mixer" , "Line2L Bypass Switch" , "Left Line2L Mux" },"Left HPCOM Mixer" , "Line2R Bypass Switch" , "Right Line2R Mux" },/* Right HPCOM Output */ "Right HPCOM Mixer" , "Line2L Bypass Switch" , "Left Line2L Mux" },"Right HPCOM Mixer" , "Line2R Bypass Switch" , "Right Line2R Mux" },/* For tlv320aic3104 */ static const struct snd_soc_dapm_route intercon_extra_3104[] = {/* Left Input */ "Left PGA Mixer" , "Mic2L Switch" , "MIC2L" },"Left PGA Mixer" , "Mic2R Switch" , "MIC2R" },/* Right Input */ "Right PGA Mixer" , "Mic2L Switch" , "MIC2L" },"Right PGA Mixer" , "Mic2R Switch" , "MIC2R" },static const struct snd_soc_dapm_route intercon_mono[] = {/* Mono Output */ "Mono Mixer" , "Line2L Bypass Switch" , "Left Line2L Mux" },"Mono Mixer" , "PGAL Bypass Switch" , "Left PGA Mixer" },"Mono Mixer" , "DACL1 Switch" , "Left DAC Mux" },"Mono Mixer" , "Line2R Bypass Switch" , "Right Line2R Mux" },"Mono Mixer" , "PGAR Bypass Switch" , "Right PGA Mixer" },"Mono Mixer" , "DACR1 Switch" , "Right DAC Mux" },"Mono Out" , NULL, "Mono Mixer" },"MONO_LOUT" , NULL, "Mono Out" },static const struct snd_soc_dapm_route intercon_3007[] = {/* Class-D outputs */ "Left Class-D Out" , NULL, "Left Line Out" },"Right Class-D Out" , NULL, "Left Line Out" },"SPOP" , NULL, "Left Class-D Out" },"SPOM" , NULL, "Right Class-D Out" },static int aic3x_add_widgets(struct snd_soc_component *component)struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);switch (aic3x->model) {case AIC3X_MODEL_3X:case AIC3X_MODEL_33:case AIC3X_MODEL_3106:break ;case AIC3X_MODEL_3007:break ;case AIC3X_MODEL_3104:break ;return 0 ;static int aic3x_hw_params(struct snd_pcm_substream *substream,struct snd_pcm_hw_params *params,struct snd_soc_dai *dai)struct snd_soc_component *component = dai->component;struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);int codec_clk = 0 , bypass_pll = 0 , fsref, last_clk = 0 ;1 , pll_r = 1 , pll_j = 1 ;1 ;int clk;int width = aic3x->slot_width;if (!width)/* select data word length */ 0 x3 << 4 ));switch (width) {case 16 :break ;case 20 :0 x01 << 4 );break ;case 24 :0 x02 << 4 );break ;case 32 :0 x03 << 4 );break ;/* Fsref can be 44100 or 48000 */ 11025 == 0 ) ? 44100 : 48000 ;/* Try to find a value for Q which allows us to bypass the PLL and for (pll_q = 2 ; pll_q < 18 ; pll_q++)if (aic3x->sysclk / (128 * pll_q) == fsref) {1 ;break ;if (bypass_pll) {0 xf;/* disable PLL if it is bypassed */ 0 );else {/* enable PLL when it is used */ /* Route Left DAC to left channel input and 44100 ) ? FSREF_44100 : FSREF_48000;if (params_rate(params) >= 64000 )/* codec sample rate select */ 20 ) / params_rate(params);if (params_rate(params) < 64000 )2 ;5 ;2 ;4 );if (bypass_pll)return 0 ;/* Use PLL, compute appropriate setup for j, d, r and p, the closest * one wins the game . Try with d = = 0 first , next with d ! = 0 . * Constraints for j are according to the datasheet . * The sysclk is divided by 1000 to prevent integer overflows . 2048 * fsref) / (aic3x->sysclk / 1000 );for (r = 1 ; r <= 16 ; r++)for (p = 1 ; p <= 8 ; p++) {for (j = 4 ; j <= 55 ; j++) {/* This is actually 1000*((j+(d/10000))*r)/p * The term had to be converted to get * rid of the division by 10000 ; d = 0 here int tmp_clk = (1000 * j * r) / p;/* Check whether this values get closer than * the best ones we had before if (abs(codec_clk - tmp_clk) <0 ;/* Early exit for exact matches */ if (tmp_clk == codec_clk)goto found;/* try with d != 0 */ for (p = 1 ; p <= 8 ; p++) {1000 ;if (j < 4 || j > 11 )continue ;/* do not use codec_clk here since we'd loose precision */ 2048 * p * fsref) - j * aic3x->sysclk)100 / (aic3x->sysclk/100 );10000 * j + d) / (10 * p);/* check whether this values get closer than the best if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {1 ; pll_p = p;/* Early exit for exact matches */ if (clk == codec_clk)goto found;if (last_clk == 0 ) {"%s(): unable to setup PLL\n" , __func__);return -EINVAL;6 ) << PLLD_MSB_SHIFT);0 x3F) << PLLD_LSB_SHIFT);return 0 ;static int aic3x_prepare(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)struct snd_soc_component *component = dai->component;struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);int delay = 0 ;int width = aic3x->slot_width;if (!width)/* TDM slot selection only valid in DSP_A/_B mode */ if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)1 );else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)/* Configure data delay */ return 0 ;static int aic3x_mute(struct snd_soc_dai *dai, int mute, int direction)struct snd_soc_component *component = dai->component;if (mute) {else {return 0 ;static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,int clk_id, unsigned int freq, int dir)struct snd_soc_component *component = codec_dai->component;struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);/* set clock on MCLK or GPIO2 or BCLK */ return 0 ;static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,unsigned int fmt)struct snd_soc_component *component = codec_dai->component;struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);0 x3f;0 x3f;switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {case SND_SOC_DAIFMT_CBP_CFP:1 ;break ;case SND_SOC_DAIFMT_CBC_CFC:0 ;break ;case SND_SOC_DAIFMT_CBP_CFC:1 ;break ;case SND_SOC_DAIFMT_CBC_CFP:1 ;break ;default :return -EINVAL;/* * match both interface format and signal polarities since they * are fixed switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):break ;case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):0 x01 << 6 );break ;case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):0 x02 << 6 );break ;case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):0 x03 << 6 );break ;default :return -EINVAL;/* set iface */ return 0 ;static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,unsigned int tx_mask, unsigned int rx_mask,int slots, int slot_width)struct snd_soc_component *component = codec_dai->component;struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);unsigned int lsb;if (tx_mask != rx_mask) {"tx and rx masks must be symmetric\n" );return -EINVAL;if (unlikely(!tx_mask)) {"tx and rx masks need to be non 0\n" );return -EINVAL;/* TDM based on DSP mode requires slots to be adjacent */ if ((lsb + 1 ) != __fls(tx_mask)) {"Invalid mask, slots must be adjacent\n" );return -EINVAL;switch (slot_width) {case 16 :case 20 :case 24 :case 32 :break ;default :"Unsupported slot width %d\n" , slot_width);return -EINVAL;/* DOUT in high-impedance on inactive bit clocks */ return 0 ;static int aic3x_regulator_event(struct notifier_block *nb,unsigned long event, void *data)struct aic3x_disable_nb *disable_nb =struct aic3x_disable_nb, nb);struct aic3x_priv *aic3x = disable_nb->aic3x;if (event & REGULATOR_EVENT_DISABLE) {/* * Put codec to reset and require cache sync as at least one * of the supplies was disabled if (aic3x->gpio_reset)1 );return 0 ;static int aic3x_set_power(struct snd_soc_component *component, int power)struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);unsigned int pll_c, pll_d;int ret;if (power) {if (ret)goto out;1 ;if (aic3x->gpio_reset) {1 );0 );if (aic3x->model == AIC3X_MODEL_3007)/* Sync reg_cache with the hardware */ false );/* Rewrite paired PLL D registers in case cached sync skipped * writing one of them and thus caused other one also not * being written if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||/* * Delay is needed to reduce pop - noise after syncing back the * registers 50 );else {/* * Do soft reset to this codec instance in order to clear * possible VDD leakage currents in case the supply regulators * remain on 0 ;/* HW writes are needless when bias is off */ true );return ret;static int aic3x_set_bias_level(struct snd_soc_component *component,enum snd_soc_bias_level level)struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);switch (level) {case SND_SOC_BIAS_ON:break ;case SND_SOC_BIAS_PREPARE:if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY &&/* enable pll */ break ;case SND_SOC_BIAS_STANDBY:if (!aic3x->power)1 );if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE &&/* disable pll */ 0 );break ;case SND_SOC_BIAS_OFF:if (aic3x->power)0 );break ;return 0 ;#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \static const struct snd_soc_dai_ops aic3x_dai_ops = {1 ,static struct snd_soc_dai_driver aic3x_dai = {"tlv320aic3x-hifi" ,"Playback" ,2 ,2 ,"Capture" ,2 ,2 ,1 ,static void aic3x_mono_init(struct snd_soc_component *component)/* DAC to Mono Line Out default volume and route to Output mixer */ /* unmute all outputs */ /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ /* Line2 to Mono Out default volume, disconnect from Output Mixer */ /* * initialise the AIC3X driver * register the mixer and dsp interfaces with the kernel static int aic3x_init(struct snd_soc_component *component)struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);/* DAC default volume and mute */ /* DAC to HP default volume and route to Output mixer */ /* DAC to Line Out default volume and route to Output mixer */ /* unmute all outputs */ /* ADC default volume and unmute */ /* By default route Line1 to ADC PGA mixer */ 0 x0);0 x0);/* PGA to HP Bypass default volume, disconnect from Output Mixer */ /* PGA to Line Out default volume, disconnect from Output Mixer */ /* On tlv320aic3104, these registers are reserved and must not be written */ if (aic3x->model != AIC3X_MODEL_3104) {/* Line2 to HP Bypass default volume, disconnect from Output Mixer */ /* Line2 Line Out default volume, disconnect from Output Mixer */ switch (aic3x->model) {case AIC3X_MODEL_3X:case AIC3X_MODEL_33:case AIC3X_MODEL_3106:break ;case AIC3X_MODEL_3007:0 );break ;/* Output common-mode voltage = 1.5 V */ return 0 ;static int aic3x_component_probe(struct snd_soc_component *component)struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);int ret, i;for (i = 0 ; i < ARRAY_SIZE(aic3x->supplies); i++) {if (ret) {"Failed to request regulator notifier: %d\n" ,return ret;if (aic3x->setup) {if (aic3x->model != AIC3X_MODEL_3104) {/* setup GPIO functions */ 0 ] & 0 xf) << 4 );1 ] & 0 xf) << 4 );else {"GPIO functionality is not supported on tlv320aic3104\n" );switch (aic3x->model) {case AIC3X_MODEL_3X:case AIC3X_MODEL_33:case AIC3X_MODEL_3106:break ;case AIC3X_MODEL_3007:1 );break ;case AIC3X_MODEL_3104:break ;/* set mic bias voltage */ switch (aic3x->micbias_vg) {case AIC3X_MICBIAS_2_0V:case AIC3X_MICBIAS_2_5V:case AIC3X_MICBIAS_AVDDV:break ;case AIC3X_MICBIAS_OFF:/* * noting to do . target won ' t enter here . This is just to avoid * compile time warning " warning : enumeration value * ' AIC3X_MICBIAS_OFF ' not handled in switch " break ;return 0 ;static const struct snd_soc_component_driver soc_component_dev_aic3x = {1 ,1 ,static void aic3x_configure_ocmv(struct device *dev, struct aic3x_priv *aic3x)struct device_node *np = dev->of_node;int dvdd, avdd;if (np && !of_property_read_u32(np, "ai3x-ocmv" , &value)) {/* OCMV setting is forced by DT */ if (value <= 3 ) {return ;1 ].consumer);2 ].consumer);if (avdd > 3600000 || dvdd > 1950000 ) {"Too high supply voltage(s) AVDD: %d, DVDD: %d\n" ,else if (avdd == 3600000 && dvdd == 1950000 ) {else if (avdd > 3300000 && dvdd > 1800000 ) {else if (avdd > 3000000 && dvdd > 1650000 ) {else if (avdd >= 2700000 && dvdd >= 1525000 ) {else {"Invalid supply voltage(s) AVDD: %d, DVDD: %d\n" ,int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data)struct aic3x_priv *aic3x;struct aic3x_setup_data *ai3x_setup;struct device_node *np = dev->of_node;int ret, i;sizeof (struct aic3x_priv), GFP_KERNEL);if (!aic3x)return -ENOMEM;if (IS_ERR(aic3x->regmap)) {return ret;true );if (np) {sizeof (*ai3x_setup), GFP_KERNEL);if (!ai3x_setup)return -ENOMEM;if (of_property_read_u32_array(np, "ai3x-gpio-func" ,2 ) >= 0 ) {if (!of_property_read_u32(np, "ai3x-micbias-vg" , &value)) {switch (value) {case 1 :break ;case 2 :break ;case 3 :break ;default :"Unsuitable MicBias voltage " "found in DT\n" );else {"reset" ,if (ret) {if (ret != -EBUSY)return ret;/* * Apparently there are setups where the codec is sharing * its reset line . Try to get it non - exclusively , although * the utility of this is unclear : how do we make sure that * resetting one chip will not disturb the others that share * the same line ? "reset" ,if (ret)return ret;true ;"tlv320aic3x reset" );for (i = 0 ; i < ARRAY_SIZE(aic3x->supplies); i++)if (ret)return dev_err_probe(dev, ret, "Failed to request supplies\n" );1 );if (ret)return ret;return 0 ;void aic3x_remove(struct device *dev)struct aic3x_priv *aic3x = dev_get_drvdata(dev);/* Leave the codec in reset state */ if (aic3x->gpio_reset && !aic3x->shared_reset)1 );"ASoC TLV320AIC3X codec driver" );"Vladimir Barinov" );"GPL" );
Messung V0.5 in Prozent C=93 H=95 G=93
¤ Dauer der Verarbeitung: 0.27 Sekunden
(vorverarbeitet am 2026-10-12)
¤ *© Formatika GbR, Deutschland
