// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2023, Linaro Ltd. #include <linux/bitfield.h>#include <linux/cleanup.h>#include <linux/device.h>#include <linux/gpio/consumer.h>#include <linux/hwmon.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/mutex.h>#include <linux/pm_runtime.h>#include <linux/regmap.h>#include <linux/regulator/consumer.h>#include <linux/reset.h>#include <linux/slab.h>#include <linux/soundwire/sdw.h>#include <linux/soundwire/sdw_registers.h>#include <linux/soundwire/sdw_type.h>#include <sound/pcm.h>#include <sound/pcm_params.h>#include <sound/soc-dapm.h>#include <sound/soc.h>#include <sound/tlv.h>#define WSA884X_BASE 0x3000#define WSA884X_ANA_BG_TSADC_BASE (WSA884X_BASE + 0x0001)#define WSA884X_BG_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x00)#define WSA884X_ADC_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x01)#define WSA884X_BOP1_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x02)#define WSA884X_BOP2_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x03)#define WSA884X_BOP2_PROG_BOP2_VTH_MASK 0xf0#define WSA884X_BOP2_PROG_BOP2_VTH_SHIFT 4#define WSA884X_BOP2_PROG_BOP2_HYST_MASK 0x0f#define WSA884X_BOP2_PROG_BOP2_HYST_SHIFT 0#define WSA884X_UVLO_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x04)#define WSA884X_UVLO_PROG1 (WSA884X_ANA_BG_TSADC_BASE + 0x05)#define WSA884X_SPARE_CTRL_0 (WSA884X_ANA_BG_TSADC_BASE + 0x06)#define WSA884X_SPARE_CTRL_1 (WSA884X_ANA_BG_TSADC_BASE + 0x07)#define WSA884X_SPARE_CTRL_2 (WSA884X_ANA_BG_TSADC_BASE + 0x08)#define WSA884X_SPARE_CTRL_3 (WSA884X_ANA_BG_TSADC_BASE + 0x09)#define WSA884X_REF_CTRL (WSA884X_ANA_BG_TSADC_BASE + 0x0a)#define WSA884X_REF_CTRL_BG_RDY_SEL_MASK 0x03#define WSA884X_REF_CTRL_BG_RDY_SEL_SHIFT 0#define WSA884X_BG_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0b)#define WSA884X_BG_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x0c)#define WSA884X_ADC_PROG (WSA884X_ANA_BG_TSADC_BASE + 0x0d)#define WSA884X_ADC_IREF_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0e)#define WSA884X_ADC_ISENS_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x0f)#define WSA884X_ADC_CLK_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x10)#define WSA884X_ADC_TEST_CTL (WSA884X_ANA_BG_TSADC_BASE + 0x11)#define WSA884X_ADC_BIAS (WSA884X_ANA_BG_TSADC_BASE + 0x12)#define WSA884X_VBAT_SNS (WSA884X_ANA_BG_TSADC_BASE + 0x13)#define WSA884X_DOUT_MSB (WSA884X_ANA_BG_TSADC_BASE + 0x14)#define WSA884X_DOUT_LSB (WSA884X_ANA_BG_TSADC_BASE + 0x15)#define WSA884X_BOP_ATEST_SEL (WSA884X_ANA_BG_TSADC_BASE + 0x16)#define WSA884X_MISC0 (WSA884X_ANA_BG_TSADC_BASE + 0x17)#define WSA884X_MISC1 (WSA884X_ANA_BG_TSADC_BASE + 0x18)#define WSA884X_MISC2 (WSA884X_ANA_BG_TSADC_BASE + 0x19)#define WSA884X_MISC3 (WSA884X_ANA_BG_TSADC_BASE + 0x1a)#define WSA884X_SPARE_TSBG_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1b)#define WSA884X_SPARE_TUNE_0 (WSA884X_ANA_BG_TSADC_BASE + 0x1c)#define WSA884X_SPARE_TUNE_1 (WSA884X_ANA_BG_TSADC_BASE + 0x1d)#define WSA884X_ANA_IVSENSE_BASE (WSA884X_BASE + 0x0020)#define WSA884X_VSENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x00)#define WSA884X_VSENSE1_GAIN_VSENSE_FE_MASK 0xe0#define WSA884X_VSENSE1_GAIN_VSENSE_FE_SHIFT 5#define WSA884X_ISENSE2 (WSA884X_ANA_IVSENSE_BASE + 0x01)#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_MASK 0xe0#define WSA884X_ISENSE2_ISENSE_GAIN_CTL_SHIFT 5#define WSA884X_SPARE_CTL_1 (WSA884X_ANA_IVSENSE_BASE + 0x02)#define WSA884X_SPARE_CTL_2 (WSA884X_ANA_IVSENSE_BASE + 0x03)#define WSA884X_SPARE_CTL_3 (WSA884X_ANA_IVSENSE_BASE + 0x04)#define WSA884X_SPARE_CTL_4 (WSA884X_ANA_IVSENSE_BASE + 0x05)#define WSA884X_EN (WSA884X_ANA_IVSENSE_BASE + 0x06)#define WSA884X_OVERRIDE1 (WSA884X_ANA_IVSENSE_BASE + 0x07)#define WSA884X_OVERRIDE2 (WSA884X_ANA_IVSENSE_BASE + 0x08)#define WSA884X_ISENSE1 (WSA884X_ANA_IVSENSE_BASE + 0x09)#define WSA884X_ISENSE_CAL (WSA884X_ANA_IVSENSE_BASE + 0x0a)#define WSA884X_MISC (WSA884X_ANA_IVSENSE_BASE + 0x0b)#define WSA884X_ADC_0 (WSA884X_ANA_IVSENSE_BASE + 0x0c)#define WSA884X_ADC_1 (WSA884X_ANA_IVSENSE_BASE + 0x0d)#define WSA884X_ADC_2 (WSA884X_ANA_IVSENSE_BASE + 0x0e)#define WSA884X_ADC_3 (WSA884X_ANA_IVSENSE_BASE + 0x0f)#define WSA884X_ADC_4 (WSA884X_ANA_IVSENSE_BASE + 0x10)#define WSA884X_ADC_5 (WSA884X_ANA_IVSENSE_BASE + 0x11)#define WSA884X_ADC_6 (WSA884X_ANA_IVSENSE_BASE + 0x12)#define WSA884X_ADC_7 (WSA884X_ANA_IVSENSE_BASE + 0x13)#define WSA884X_STATUS (WSA884X_ANA_IVSENSE_BASE + 0x14)#define WSA884X_IVSENSE_SPARE_TUNE_1 (WSA884X_ANA_IVSENSE_BASE + 0x15)#define WSA884X_SPARE_TUNE_2 (WSA884X_ANA_IVSENSE_BASE + 0x16)#define WSA884X_SPARE_TUNE_3 (WSA884X_ANA_IVSENSE_BASE + 0x17)#define WSA884X_SPARE_TUNE_4 (WSA884X_ANA_IVSENSE_BASE + 0x18)#define WSA884X_ANA_SPK_TOP_BASE (WSA884X_BASE + 0x0040)#define WSA884X_TOP_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x00)#define WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK 0x01#define WSA884X_CLIP_DET_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x01)#define WSA884X_CLIP_DET_CTRL2 (WSA884X_ANA_SPK_TOP_BASE + 0x02)#define WSA884X_DAC_CTRL1 (WSA884X_ANA_SPK_TOP_BASE + 0x03)#define WSA884X_DAC_VCM_CTRL_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x04)#define WSA884X_DAC_VCM_CTRL_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x05)#define WSA884X_DAC_VCM_CTRL_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x06)#define WSA884X_DAC_VCM_CTRL_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x07)#define WSA884X_DAC_VCM_CTRL_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x08)#define WSA884X_DAC_VCM_CTRL_REG6 (WSA884X_ANA_SPK_TOP_BASE + 0x09)#define WSA884X_PWM_CLK_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0a)#define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_MASK 0x80#define WSA884X_PWM_CLK_CTL_VCMO_INT1_IDLE_MODE_OVRT_SHIFT 7#define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_MASK 0x40#define WSA884X_PWM_CLK_CTL_REG_MCLK_DIV_RATIO_SHIFT 6#define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_MASK 0x30#define WSA884X_PWM_CLK_CTL_PWM_DEGLITCH_CLK_DELAY_CTRL_SHIFT 4#define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_MASK 0x08#define WSA884X_PWM_CLK_CTL_PWM_CLK_FREQ_SEL_SHIFT 3#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_MASK 0x06#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_RATIO_SHIFT 1#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_MASK 0x01#define WSA884X_PWM_CLK_CTL_PWM_CLK_DIV_BYPASS_SHIFT 0#define WSA884X_DRV_LF_LDO_SEL (WSA884X_ANA_SPK_TOP_BASE + 0x0b)#define WSA884X_OCP_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0c)#define WSA884X_PDRV_HS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0d)#define WSA884X_PDRV_LS_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x0e)#define WSA884X_SPK_TOP_SPARE_CTL_1 (WSA884X_ANA_SPK_TOP_BASE + 0x0f)#define WSA884X_SPK_TOP_SPARE_CTL_2 (WSA884X_ANA_SPK_TOP_BASE + 0x10)#define WSA884X_SPK_TOP_SPARE_CTL_3 (WSA884X_ANA_SPK_TOP_BASE + 0x11)#define WSA884X_SPK_TOP_SPARE_CTL_4 (WSA884X_ANA_SPK_TOP_BASE + 0x12)#define WSA884X_SPARE_CTL_5 (WSA884X_ANA_SPK_TOP_BASE + 0x13)#define WSA884X_DAC_EN_DEBUG_REG (WSA884X_ANA_SPK_TOP_BASE + 0x14)#define WSA884X_DAC_OPAMP_BIAS1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x15)#define WSA884X_DAC_OPAMP_BIAS2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x16)#define WSA884X_DAC_TUNE1 (WSA884X_ANA_SPK_TOP_BASE + 0x17)#define WSA884X_DAC_VOLTAGE_CTRL_REG (WSA884X_ANA_SPK_TOP_BASE + 0x18)#define WSA884X_ATEST1_REG (WSA884X_ANA_SPK_TOP_BASE + 0x19)#define WSA884X_ATEST2_REG (WSA884X_ANA_SPK_TOP_BASE + 0x1a)#define WSA884X_TOP_BIAS_REG1 (WSA884X_ANA_SPK_TOP_BASE + 0x1b)#define WSA884X_TOP_BIAS_REG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1c)#define WSA884X_TOP_BIAS_REG3 (WSA884X_ANA_SPK_TOP_BASE + 0x1d)#define WSA884X_TOP_BIAS_REG4 (WSA884X_ANA_SPK_TOP_BASE + 0x1e)#define WSA884X_PWRSTG_DBG2 (WSA884X_ANA_SPK_TOP_BASE + 0x1f)#define WSA884X_DRV_LF_BLK_EN (WSA884X_ANA_SPK_TOP_BASE + 0x20)#define WSA884X_DRV_LF_EN (WSA884X_ANA_SPK_TOP_BASE + 0x21)#define WSA884X_DRV_LF_MASK_DCC_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x22)#define WSA884X_DRV_LF_MISC_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x23)#define WSA884X_DRV_LF_REG_GAIN (WSA884X_ANA_SPK_TOP_BASE + 0x24)#define WSA884X_DRV_OS_CAL_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x25)#define WSA884X_DRV_OS_CAL_CTL1 (WSA884X_ANA_SPK_TOP_BASE + 0x26)#define WSA884X_PWRSTG_DBG (WSA884X_ANA_SPK_TOP_BASE + 0x27)#define WSA884X_BBM_CTL (WSA884X_ANA_SPK_TOP_BASE + 0x28)#define WSA884X_TOP_MISC1 (WSA884X_ANA_SPK_TOP_BASE + 0x29)#define WSA884X_DAC_VCM_CTRL_REG7 (WSA884X_ANA_SPK_TOP_BASE + 0x2a)#define WSA884X_TOP_BIAS_REG5 (WSA884X_ANA_SPK_TOP_BASE + 0x2b)#define WSA884X_DRV_LF_MISC_CTL2 (WSA884X_ANA_SPK_TOP_BASE + 0x2c)#define WSA884X_SPK_TOP_SPARE_TUNE_2 (WSA884X_ANA_SPK_TOP_BASE + 0x2d)#define WSA884X_SPK_TOP_SPARE_TUNE_3 (WSA884X_ANA_SPK_TOP_BASE + 0x2e)#define WSA884X_SPK_TOP_SPARE_TUNE_4 (WSA884X_ANA_SPK_TOP_BASE + 0x2f)#define WSA884X_SPARE_TUNE_5 (WSA884X_ANA_SPK_TOP_BASE + 0x30)#define WSA884X_SPARE_TUNE_6 (WSA884X_ANA_SPK_TOP_BASE + 0x31)#define WSA884X_SPARE_TUNE_7 (WSA884X_ANA_SPK_TOP_BASE + 0x32)#define WSA884X_SPARE_TUNE_8 (WSA884X_ANA_SPK_TOP_BASE + 0x33)#define WSA884X_SPARE_TUNE_9 (WSA884X_ANA_SPK_TOP_BASE + 0x34)#define WSA884X_SPARE_TUNE_10 (WSA884X_ANA_SPK_TOP_BASE + 0x35)#define WSA884X_PA_STATUS0 (WSA884X_ANA_SPK_TOP_BASE + 0x36)#define WSA884X_PA_STATUS1 (WSA884X_ANA_SPK_TOP_BASE + 0x37)#define WSA884X_PA_STATUS2 (WSA884X_ANA_SPK_TOP_BASE + 0x38)#define WSA884X_PA_STATUS3 (WSA884X_ANA_SPK_TOP_BASE + 0x39)#define WSA884X_PA_STATUS4 (WSA884X_ANA_SPK_TOP_BASE + 0x3a)#define WSA884X_PA_STATUS5 (WSA884X_ANA_SPK_TOP_BASE + 0x3b)#define WSA884X_SPARE_RO_1 (WSA884X_ANA_SPK_TOP_BASE + 0x3c)#define WSA884X_SPARE_RO_2 (WSA884X_ANA_SPK_TOP_BASE + 0x3d)#define WSA884X_SPARE_RO_3 (WSA884X_ANA_SPK_TOP_BASE + 0x3e)#define WSA884X_ANA_BOOST_BASE (WSA884X_BASE + 0x0090)#define WSA884X_STB_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x00)#define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_MASK 0xf8#define WSA884X_STB_CTRL1_SLOPE_COMP_CURRENT_SHIFT 3#define WSA884X_STB_CTRL1_VOUT_FS_MASK 0x07#define WSA884X_STB_CTRL1_VOUT_FS_SHIFT 0#define WSA884X_CURRENT_LIMIT (WSA884X_ANA_BOOST_BASE + 0x01)#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_MASK 0x80#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_OVRD_EN_SHIFT 7#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_MASK 0x7c#define WSA884X_CURRENT_LIMIT_CURRENT_LIMIT_SHIFT 2#define WSA884X_CURRENT_LIMIT_CLK_PHASE_SHIFT 0#define WSA884X_BYP_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x02)#define WSA884X_SPARE_CTL_0 (WSA884X_ANA_BOOST_BASE + 0x03)#define WSA884X_BOOST_SPARE_CTL_1 (WSA884X_ANA_BOOST_BASE + 0x04)#define WSA884X_SPARE_RO_0 (WSA884X_ANA_BOOST_BASE + 0x05)#define WSA884X_BOOST_SPARE_RO_1 (WSA884X_ANA_BOOST_BASE + 0x06)#define WSA884X_IBIAS1 (WSA884X_ANA_BOOST_BASE + 0x07)#define WSA884X_IBIAS2 (WSA884X_ANA_BOOST_BASE + 0x08)#define WSA884X_IBIAS3 (WSA884X_ANA_BOOST_BASE + 0x09)#define WSA884X_EN_CTRL (WSA884X_ANA_BOOST_BASE + 0x0a)#define WSA884X_STB_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0b)#define WSA884X_STB_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0c)#define WSA884X_STB_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x0d)#define WSA884X_BYP_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x0e)#define WSA884X_BYP_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x0f)#define WSA884X_ZX_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x10)#define WSA884X_ZX_CTRL1_ZX_DET_EN_MASK 0x80#define WSA884X_ZX_CTRL1_ZX_DET_EN_SHIFT 7#define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_MASK 0x40#define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_SHIFT 6#define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_MASK 0x20#define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_SHIFT 5#define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK 0x18#define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_SHIFT 3#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_MASK 0x04#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_SHIFT 2#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_MASK 0x02#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_SHIFT 1#define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_MASK 0x01#define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_SHIFT 0#define WSA884X_ZX_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x11)#define WSA884X_BLEEDER_CTRL (WSA884X_ANA_BOOST_BASE + 0x12)#define WSA884X_BOOST_MISC (WSA884X_ANA_BOOST_BASE + 0x13)#define WSA884X_PWRSTAGE_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x14)#define WSA884X_PWRSTAGE_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x15)#define WSA884X_PWRSTAGE_CTRL3 (WSA884X_ANA_BOOST_BASE + 0x16)#define WSA884X_PWRSTAGE_CTRL4 (WSA884X_ANA_BOOST_BASE + 0x17)#define WSA884X_MAXD_REG1 (WSA884X_ANA_BOOST_BASE + 0x18)#define WSA884X_MAXD_REG2 (WSA884X_ANA_BOOST_BASE + 0x19)#define WSA884X_ILIM_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1a)#define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_MASK 0x80#define WSA884X_ILIM_CTRL1_EN_AUTO_MAXD_SEL_SHIFT 0x07#define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_MASK 0x40#define WSA884X_ILIM_CTRL1_EN_ILIM_SW_CLH_SHIFT 0x06#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_MASK 0x38#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_CLH_SHIFT 0x03#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_MASK 0x07#define WSA884X_ILIM_CTRL1_ILIM_OFFSET_PB_SHIFT 0x00#define WSA884X_ILIM_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1b)#define WSA884X_TEST_CTRL1 (WSA884X_ANA_BOOST_BASE + 0x1c)#define WSA884X_TEST_CTRL2 (WSA884X_ANA_BOOST_BASE + 0x1d)#define WSA884X_SPARE1 (WSA884X_ANA_BOOST_BASE + 0x1e)#define WSA884X_BOOT_CAP_CHECK (WSA884X_ANA_BOOST_BASE + 0x1f)#define WSA884X_ANA_PON_LDOL_BASE (WSA884X_BASE + 0x00b0)#define WSA884X_PON_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x00)#define WSA884X_PWRSAV_CTL (WSA884X_ANA_PON_LDOL_BASE + 0x01)#define WSA884X_PON_LDOL_SPARE_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x02)#define WSA884X_PON_LDOL_SPARE_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x03)#define WSA884X_PON_LDOL_SPARE_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x04)#define WSA884X_PON_LDOL_SPARE_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x05)#define WSA884X_PON_CLT_1 (WSA884X_ANA_PON_LDOL_BASE + 0x06)#define WSA884X_PON_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x07)#define WSA884X_PON_CTL_3 (WSA884X_ANA_PON_LDOL_BASE + 0x08)#define WSA884X_CKWD_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x09)#define WSA884X_CKWD_CTL_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0a)#define WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK 0x20#define WSA884X_CKWD_CTL_1_VPP_SW_CTL_SHIFT 5#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK 0x1f#define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT 0#define WSA884X_CKWD_CTL_2 (WSA884X_ANA_PON_LDOL_BASE + 0x0b)#define WSA884X_CKSK_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0c)#define WSA884X_PADSW_CTL_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0d)#define WSA884X_TEST_0 (WSA884X_ANA_PON_LDOL_BASE + 0x0e)#define WSA884X_TEST_1 (WSA884X_ANA_PON_LDOL_BASE + 0x0f)#define WSA884X_STATUS_0 (WSA884X_ANA_PON_LDOL_BASE + 0x10)#define WSA884X_STATUS_1 (WSA884X_ANA_PON_LDOL_BASE + 0x11)#define WSA884X_PON_LDOL_SPARE_TUNE_0 (WSA884X_ANA_PON_LDOL_BASE + 0x12)#define WSA884X_PON_LDOL_SPARE_TUNE_1 (WSA884X_ANA_PON_LDOL_BASE + 0x13)#define WSA884X_PON_LDOL_SPARE_TUNE_2 (WSA884X_ANA_PON_LDOL_BASE + 0x14)#define WSA884X_PON_LDOL_SPARE_TUNE_3 (WSA884X_ANA_PON_LDOL_BASE + 0x15)#define WSA884X_PON_LDOL_SPARE_TUNE_4 (WSA884X_ANA_PON_LDOL_BASE + 0x16)#define WSA884X_DIG_CTRL0_BASE (WSA884X_BASE + 0x0400)#define WSA884X_DIG_CTRL0_PAGE (WSA884X_DIG_CTRL0_BASE + 0x00)#define WSA884X_CHIP_ID0 (WSA884X_DIG_CTRL0_BASE + 0x01)#define WSA884X_CHIP_ID1 (WSA884X_DIG_CTRL0_BASE + 0x02)#define WSA884X_CHIP_ID2 (WSA884X_DIG_CTRL0_BASE + 0x03)#define WSA884X_CHIP_ID3 (WSA884X_DIG_CTRL0_BASE + 0x04)#define WSA884X_BUS_ID (WSA884X_DIG_CTRL0_BASE + 0x05)#define WSA884X_CDC_RST_CTL (WSA884X_DIG_CTRL0_BASE + 0x10)#define WSA884X_SWR_RESET_EN (WSA884X_DIG_CTRL0_BASE + 0x14)#define WSA884X_TOP_CLK_CFG (WSA884X_DIG_CTRL0_BASE + 0x18)#define WSA884X_SWR_CLK_RATE (WSA884X_DIG_CTRL0_BASE + 0x19)#define WSA884X_CDC_PATH_MODE (WSA884X_DIG_CTRL0_BASE + 0x1a)#define WSA884X_CDC_PATH_MODE_RXD_MODE_MASK 0x02#define WSA884X_CDC_PATH_MODE_RXD_MODE_SHIFT 0#define WSA884X_CDC_PATH_MODE_TXD_MODE_MASK 0x01#define WSA884X_CDC_PATH_MODE_TXD_MODE_SHIFT 0#define WSA884X_CDC_CLK_CTL (WSA884X_DIG_CTRL0_BASE + 0x1c)#define WSA884X_PA_FSM_EN (WSA884X_DIG_CTRL0_BASE + 0x30)#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_MASK 0x01#define WSA884X_PA_FSM_EN_GLOBAL_PA_EN_SHIFT 0#define WSA884X_PA_FSM_CTL0 (WSA884X_DIG_CTRL0_BASE + 0x31)#define WSA884X_PA_FSM_CTL1 (WSA884X_DIG_CTRL0_BASE + 0x32)#define WSA884X_PA_FSM_CTL1_NOISE_GATE_BLOCK_MASK 0x38#define WSA884X_PA_FSM_TIMER0 (WSA884X_DIG_CTRL0_BASE + 0x33)#define WSA884X_PA_FSM_TIMER1 (WSA884X_DIG_CTRL0_BASE + 0x34)#define WSA884X_PA_FSM_STA0 (WSA884X_DIG_CTRL0_BASE + 0x35)#define WSA884X_PA_FSM_STA1 (WSA884X_DIG_CTRL0_BASE + 0x36)#define WSA884X_PA_FSM_ERR_CTL (WSA884X_DIG_CTRL0_BASE + 0x37)#define WSA884X_PA_FSM_ERR_COND0 (WSA884X_DIG_CTRL0_BASE + 0x38)#define WSA884X_PA_FSM_ERR_COND1 (WSA884X_DIG_CTRL0_BASE + 0x39)#define WSA884X_PA_FSM_MSK0 (WSA884X_DIG_CTRL0_BASE + 0x3a)#define WSA884X_PA_FSM_MSK1 (WSA884X_DIG_CTRL0_BASE + 0x3b)#define WSA884X_PA_FSM_BYP_CTL (WSA884X_DIG_CTRL0_BASE + 0x3c)#define WSA884X_PA_FSM_BYP0 (WSA884X_DIG_CTRL0_BASE + 0x3d)#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_MASK 0x01#define WSA884X_PA_FSM_BYP0_DC_CAL_EN_SHIFT 0#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_MASK 0x02#define WSA884X_PA_FSM_BYP0_CLK_WD_EN_SHIFT 1#define WSA884X_PA_FSM_BYP0_BG_EN_MASK 0x04#define WSA884X_PA_FSM_BYP0_BG_EN_SHIFT 2#define WSA884X_PA_FSM_BYP0_BOOST_EN_MASK 0x08#define WSA884X_PA_FSM_BYP0_BOOST_EN_SHIFT 3#define WSA884X_PA_FSM_BYP0_PA_EN_MASK 0x10#define WSA884X_PA_FSM_BYP0_PA_EN_SHIFT 4#define WSA884X_PA_FSM_BYP0_D_UNMUTE_MASK 0x20#define WSA884X_PA_FSM_BYP0_D_UNMUTE_SHIFT 5#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_MASK 0x40#define WSA884X_PA_FSM_BYP0_SPKR_PROT_EN_SHIFT 6#define WSA884X_PA_FSM_BYP0_TSADC_EN_MASK 0x80#define WSA884X_PA_FSM_BYP0_TSADC_EN_SHIFT 7#define WSA884X_PA_FSM_BYP1 (WSA884X_DIG_CTRL0_BASE + 0x3e)#define WSA884X_TADC_VALUE_CTL (WSA884X_DIG_CTRL0_BASE + 0x50)#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_MASK 0x01#define WSA884X_TADC_VALUE_CTL_TEMP_VALUE_RD_EN_SHIFT 0#define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_MASK 0x02#define WSA884X_TADC_VALUE_CTL_VBAT_VALUE_RD_EN_SHIFT 1#define WSA884X_TEMP_DETECT_CTL (WSA884X_DIG_CTRL0_BASE + 0x51)#define WSA884X_TEMP_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x52)#define WSA884X_TEMP_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x53)#define WSA884X_TEMP_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x54)#define WSA884X_TEMP_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x55)#define WSA884X_TEMP_CONFIG0 (WSA884X_DIG_CTRL0_BASE + 0x56)#define WSA884X_TEMP_CONFIG1 (WSA884X_DIG_CTRL0_BASE + 0x57)#define WSA884X_VBAT_THRM_FLT_CTL (WSA884X_DIG_CTRL0_BASE + 0x58)#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_MASK 0xe0#define WSA884X_VBAT_THRM_FLT_CTL_THRM_COEF_SEL_SHIFT 5#define WSA884X_VBAT_THRM_FLT_CTL_THRM_FLT_EN_SHIFT 4#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_MASK 0x0e#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_COEF_SEL_SHIFT 1#define WSA884X_VBAT_THRM_FLT_CTL_VBAT_FLT_EN_SHIFT 0#define WSA884X_VBAT_CAL_CTL (WSA884X_DIG_CTRL0_BASE + 0x59)#define WSA884X_VBAT_CAL_CTL_RESERVE_MASK 0x0e#define WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK 0x01#define WSA884X_VBAT_DIN_MSB (WSA884X_DIG_CTRL0_BASE + 0x5a)#define WSA884X_VBAT_DIN_LSB (WSA884X_DIG_CTRL0_BASE + 0x5b)#define WSA884X_VBAT_DOUT_MSB (WSA884X_DIG_CTRL0_BASE + 0x5c)#define WSA884X_VBAT_DOUT_LSB (WSA884X_DIG_CTRL0_BASE + 0x5d)#define WSA884X_VBAT_CAL_MSB (WSA884X_DIG_CTRL0_BASE + 0x5e)#define WSA884X_VBAT_CAL_LSB (WSA884X_DIG_CTRL0_BASE + 0x5f)#define WSA884X_UVLO_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x60)#define WSA884X_BOP_DEGLITCH_CTL (WSA884X_DIG_CTRL0_BASE + 0x61)#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_MASK 0x1e#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_SETTING_SHIFT 1#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_MASK 0x1#define WSA884X_BOP_DEGLITCH_CTL_BOP_DEGLITCH_EN_SHIFT 0#define WSA884X_VBAT_ZONE_DETC_CTL (WSA884X_DIG_CTRL0_BASE + 0x64)#define WSA884X_CPS_CTL (WSA884X_DIG_CTRL0_BASE + 0x68)#define WSA884X_CDC_RX_CTL (WSA884X_DIG_CTRL0_BASE + 0x70)#define WSA884X_CDC_SPK_DSM_A1_0 (WSA884X_DIG_CTRL0_BASE + 0x71)#define WSA884X_CDC_SPK_DSM_A1_1 (WSA884X_DIG_CTRL0_BASE + 0x72)#define WSA884X_CDC_SPK_DSM_A2_0 (WSA884X_DIG_CTRL0_BASE + 0x73)#define WSA884X_CDC_SPK_DSM_A2_1 (WSA884X_DIG_CTRL0_BASE + 0x74)#define WSA884X_CDC_SPK_DSM_A3_0 (WSA884X_DIG_CTRL0_BASE + 0x75)#define WSA884X_CDC_SPK_DSM_A3_1 (WSA884X_DIG_CTRL0_BASE + 0x76)#define WSA884X_CDC_SPK_DSM_A4_0 (WSA884X_DIG_CTRL0_BASE + 0x77)#define WSA884X_CDC_SPK_DSM_A4_1 (WSA884X_DIG_CTRL0_BASE + 0x78)#define WSA884X_CDC_SPK_DSM_A5_0 (WSA884X_DIG_CTRL0_BASE + 0x79)#define WSA884X_CDC_SPK_DSM_A5_1 (WSA884X_DIG_CTRL0_BASE + 0x7a)#define WSA884X_CDC_SPK_DSM_A6_0 (WSA884X_DIG_CTRL0_BASE + 0x7b)#define WSA884X_CDC_SPK_DSM_A7_0 (WSA884X_DIG_CTRL0_BASE + 0x7c)#define WSA884X_CDC_SPK_DSM_C_0 (WSA884X_DIG_CTRL0_BASE + 0x7d)#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_MASK 0xf0#define WSA884X_CDC_SPK_DSM_C_0_COEF_C3_SHIFT 4#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_MASK 0x0f#define WSA884X_CDC_SPK_DSM_C_0_COEF_C2_SHIFT 0#define WSA884X_CDC_SPK_DSM_C_1 (WSA884X_DIG_CTRL0_BASE + 0x7e)#define WSA884X_CDC_SPK_DSM_C_2 (WSA884X_DIG_CTRL0_BASE + 0x7f)#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_MASK 0xf0#define WSA884X_CDC_SPK_DSM_C_2_COEF_C7_SHIFT 4#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_MASK 0x0f#define WSA884X_CDC_SPK_DSM_C_2_COEF_C6_SHIFT 0#define WSA884X_CDC_SPK_DSM_C_3 (WSA884X_DIG_CTRL0_BASE + 0x80)#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_MASK 0x3f#define WSA884X_CDC_SPK_DSM_C_3_COEF_C7_SHIFT 0#define WSA884X_CDC_SPK_DSM_R1 (WSA884X_DIG_CTRL0_BASE + 0x81)#define WSA884X_CDC_SPK_DSM_R2 (WSA884X_DIG_CTRL0_BASE + 0x82)#define WSA884X_CDC_SPK_DSM_R3 (WSA884X_DIG_CTRL0_BASE + 0x83)#define WSA884X_CDC_SPK_DSM_R4 (WSA884X_DIG_CTRL0_BASE + 0x84)#define WSA884X_CDC_SPK_DSM_R5 (WSA884X_DIG_CTRL0_BASE + 0x85)#define WSA884X_CDC_SPK_DSM_R6 (WSA884X_DIG_CTRL0_BASE + 0x86)#define WSA884X_CDC_SPK_DSM_R7 (WSA884X_DIG_CTRL0_BASE + 0x87)#define WSA884X_CDC_SPK_GAIN_PDM_0 (WSA884X_DIG_CTRL0_BASE + 0x88)#define WSA884X_CDC_SPK_GAIN_PDM_1 (WSA884X_DIG_CTRL0_BASE + 0x89)#define WSA884X_CDC_SPK_GAIN_PDM_2 (WSA884X_DIG_CTRL0_BASE + 0x8a)#define WSA884X_PDM_WD_CTL (WSA884X_DIG_CTRL0_BASE + 0x8b)#define WSA884X_PDM_WD_CTL_HOLD_OFF_MASK 0x04#define WSA884X_PDM_WD_CTL_HOLD_OFF_SHIFT 2#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_MASK 0x02#define WSA884X_PDM_WD_CTL_TIME_OUT_SEL_SHIFT 1#define WSA884X_PDM_WD_CTL_PDM_WD_EN_MASK 0x01#define WSA884X_PDM_WD_CTL_PDM_WD_EN_SHIFT 0#define WSA884X_DEM_BYPASS_DATA0 (WSA884X_DIG_CTRL0_BASE + 0x90)#define WSA884X_DEM_BYPASS_DATA1 (WSA884X_DIG_CTRL0_BASE + 0x91)#define WSA884X_DEM_BYPASS_DATA2 (WSA884X_DIG_CTRL0_BASE + 0x92)#define WSA884X_DEM_BYPASS_DATA3 (WSA884X_DIG_CTRL0_BASE + 0x93)#define WSA884X_DRE_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xb0)#define WSA884X_DRE_CTL_0_PROG_DELAY_MASK 0xf0#define WSA884X_DRE_CTL_0_PROG_DELAY_SHIFT 4#define WSA884X_DRE_CTL_0_OFFSET_MASK 0x07#define WSA884X_DRE_CTL_0_OFFSET_SHIFT 0#define WSA884X_DRE_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xb1)#define WSA884X_DRE_CTL_1_CSR_GAIN_MASK 0x3e#define WSA884X_DRE_CTL_1_CSR_GAIN_SHIFT 1#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_MASK 0x01#define WSA884X_DRE_CTL_1_CSR_GAIN_EN_SHIFT 0#define WSA884X_DRE_IDLE_DET_CTL (WSA884X_DIG_CTRL0_BASE + 0xb2)#define WSA884X_GAIN_RAMPING_CTL (WSA884X_DIG_CTRL0_BASE + 0xb8)#define WSA884X_GAIN_RAMPING_MIN (WSA884X_DIG_CTRL0_BASE + 0xb9)#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_MASK 0x1f#define WSA884X_GAIN_RAMPING_MIN_MIN_GAIN_SHIFT 0#define WSA884X_TAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc0)#define WSA884X_TAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc1)#define WSA884X_TAGC_FORCE_VAL (WSA884X_DIG_CTRL0_BASE + 0xc2)#define WSA884X_VAGC_CTL (WSA884X_DIG_CTRL0_BASE + 0xc8)#define WSA884X_VAGC_TIME (WSA884X_DIG_CTRL0_BASE + 0xc9)#define WSA884X_VAGC_ATTN_LVL_1 (WSA884X_DIG_CTRL0_BASE + 0xca)#define WSA884X_VAGC_ATTN_LVL_2 (WSA884X_DIG_CTRL0_BASE + 0xcb)#define WSA884X_VAGC_ATTN_LVL_3 (WSA884X_DIG_CTRL0_BASE + 0xcc)#define WSA884X_CLSH_CTL_0 (WSA884X_DIG_CTRL0_BASE + 0xd0)#define WSA884X_CLSH_CTL_0_CSR_GAIN_EN_SHIFT 7#define WSA884X_CLSH_CTL_0_DLY_CODE_MASK 0x70#define WSA884X_CLSH_CTL_0_DLY_CODE_SHIFT 4#define WSA884X_CLSH_CTL_0_DLY_RST_SHIFT 3#define WSA884X_CLSH_CTL_0_DLY_EN_SHIFT 2#define WSA884X_CLSH_CTL_0_INPUT_EN_SHIFT 1#define WSA884X_CLSH_CTL_0_CLSH_EN_SHIFT 0#define WSA884X_CLSH_CTL_1 (WSA884X_DIG_CTRL0_BASE + 0xd1)#define WSA884X_CLSH_V_HD_PA (WSA884X_DIG_CTRL0_BASE + 0xd2)#define WSA884X_CLSH_V_PA_MIN (WSA884X_DIG_CTRL0_BASE + 0xd3)#define WSA884X_CLSH_OVRD_VAL (WSA884X_DIG_CTRL0_BASE + 0xd4)#define WSA884X_CLSH_HARD_MAX (WSA884X_DIG_CTRL0_BASE + 0xd5)#define WSA884X_CLSH_SOFT_MAX (WSA884X_DIG_CTRL0_BASE + 0xd6)#define WSA884X_CLSH_SIG_DP (WSA884X_DIG_CTRL0_BASE + 0xd7)#define WSA884X_PBR_DELAY_CTL (WSA884X_DIG_CTRL0_BASE + 0xd8)#define WSA884X_CLSH_SRL_MAX_PBR (WSA884X_DIG_CTRL0_BASE + 0xe0)#define WSA884X_PBR_MAX_VOLTAGE 20#define WSA884X_PBR_MAX_CODE 255#define WSA884X_VTH_TO_REG(vth) \#define WSA884X_CLSH_VTH1 (WSA884X_DIG_CTRL0_BASE + 0xe1)#define WSA884X_CLSH_VTH2 (WSA884X_DIG_CTRL0_BASE + 0xe2)#define WSA884X_CLSH_VTH3 (WSA884X_DIG_CTRL0_BASE + 0xe3)#define WSA884X_CLSH_VTH4 (WSA884X_DIG_CTRL0_BASE + 0xe4)#define WSA884X_CLSH_VTH5 (WSA884X_DIG_CTRL0_BASE + 0xe5)#define WSA884X_CLSH_VTH6 (WSA884X_DIG_CTRL0_BASE + 0xe6)#define WSA884X_CLSH_VTH7 (WSA884X_DIG_CTRL0_BASE + 0xe7)#define WSA884X_CLSH_VTH8 (WSA884X_DIG_CTRL0_BASE + 0xe8)#define WSA884X_CLSH_VTH9 (WSA884X_DIG_CTRL0_BASE + 0xe9)#define WSA884X_CLSH_VTH10 (WSA884X_DIG_CTRL0_BASE + 0xea)#define WSA884X_CLSH_VTH11 (WSA884X_DIG_CTRL0_BASE + 0xeb)#define WSA884X_CLSH_VTH12 (WSA884X_DIG_CTRL0_BASE + 0xec)#define WSA884X_CLSH_VTH13 (WSA884X_DIG_CTRL0_BASE + 0xed)#define WSA884X_CLSH_VTH14 (WSA884X_DIG_CTRL0_BASE + 0xee)#define WSA884X_CLSH_VTH15 (WSA884X_DIG_CTRL0_BASE + 0xef)#define WSA884X_DIG_CTRL1_BASE (WSA884X_BASE + 0x0500)#define WSA884X_DIG_CTRL1_PAGE (WSA884X_DIG_CTRL1_BASE + 0x00)#define WSA884X_VPHX_SYS_EN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x01)#define WSA884X_ANA_WO_CTL_0 (WSA884X_DIG_CTRL1_BASE + 0x04)#define WSA884X_ANA_WO_CTL_0_MODE_SHIFT 0#define WSA884X_ANA_WO_CTL_0_VPHX_SYS_EN_MASK 0xc0#define WSA884X_ANA_WO_CTL_0_PA_AUX_DISABLE 0x0#define WSA884X_ANA_WO_CTL_0_PA_AUX_18_DB 0xa#define WSA884X_ANA_WO_CTL_0_PA_AUX_0_DB 0x7#define WSA884X_ANA_WO_CTL_0_PA_AUX_GAIN_MASK 0x3c#define WSA884X_ANA_WO_CTL_0_PA_MIN_GAIN_BYP_MASK 0x02#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MODE_SPEAKER 0x1#define WSA884X_ANA_WO_CTL_0_DAC_CM_CLAMP_EN_MASK 0x01#define WSA884X_ANA_WO_CTL_1 (WSA884X_DIG_CTRL1_BASE + 0x05)#define WSA884X_PIN_CTL (WSA884X_DIG_CTRL1_BASE + 0x10)#define WSA884X_PIN_CTL_OE (WSA884X_DIG_CTRL1_BASE + 0x11)#define WSA884X_PIN_WDATA_IOPAD (WSA884X_DIG_CTRL1_BASE + 0x12)#define WSA884X_PIN_STATUS (WSA884X_DIG_CTRL1_BASE + 0x13)#define WSA884X_I2C_SLAVE_CTL (WSA884X_DIG_CTRL1_BASE + 0x14)#define WSA884X_SPMI_PAD_CTL0 (WSA884X_DIG_CTRL1_BASE + 0x15)#define WSA884X_SPMI_PAD_CTL1 (WSA884X_DIG_CTRL1_BASE + 0x16)#define WSA884X_SPMI_PAD_CTL2 (WSA884X_DIG_CTRL1_BASE + 0x17)#define WSA884X_MEM_CTL (WSA884X_DIG_CTRL1_BASE + 0x18)#define WSA884X_SWR_HM_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x19)#define WSA884X_SWR_HM_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x1a)#define WSA884X_OTP_CTRL0 (WSA884X_DIG_CTRL1_BASE + 0x30)#define WSA884X_OTP_CTRL1 (WSA884X_DIG_CTRL1_BASE + 0x31)#define WSA884X_OTP_CTRL2 (WSA884X_DIG_CTRL1_BASE + 0x32)#define WSA884X_OTP_STAT (WSA884X_DIG_CTRL1_BASE + 0x33)#define WSA884X_OTP_PRG_TCSP0 (WSA884X_DIG_CTRL1_BASE + 0x34)#define WSA884X_OTP_PRG_TCSP1 (WSA884X_DIG_CTRL1_BASE + 0x35)#define WSA884X_OTP_PRG_TPPS (WSA884X_DIG_CTRL1_BASE + 0x36)#define WSA884X_OTP_PRG_TVPS (WSA884X_DIG_CTRL1_BASE + 0x37)#define WSA884X_OTP_PRG_TVPH (WSA884X_DIG_CTRL1_BASE + 0x38)#define WSA884X_OTP_PRG_TPPR0 (WSA884X_DIG_CTRL1_BASE + 0x39)#define WSA884X_OTP_PRG_TPPR1 (WSA884X_DIG_CTRL1_BASE + 0x3a)#define WSA884X_OTP_PRG_TPPH (WSA884X_DIG_CTRL1_BASE + 0x3b)#define WSA884X_OTP_PRG_END (WSA884X_DIG_CTRL1_BASE + 0x3c)#define WSA884X_WAVG_PLAY (WSA884X_DIG_CTRL1_BASE + 0x40)#define WSA884X_WAVG_CTL (WSA884X_DIG_CTRL1_BASE + 0x41)#define WSA884X_WAVG_LRA_PER_0 (WSA884X_DIG_CTRL1_BASE + 0x43)#define WSA884X_WAVG_LRA_PER_1 (WSA884X_DIG_CTRL1_BASE + 0x44)#define WSA884X_WAVG_DELTA_THETA_0 (WSA884X_DIG_CTRL1_BASE + 0x45)#define WSA884X_WAVG_DELTA_THETA_1 (WSA884X_DIG_CTRL1_BASE + 0x46)#define WSA884X_WAVG_DIRECT_AMP_0 (WSA884X_DIG_CTRL1_BASE + 0x47)#define WSA884X_WAVG_DIRECT_AMP_1 (WSA884X_DIG_CTRL1_BASE + 0x48)#define WSA884X_WAVG_PTRN_AMP0_0 (WSA884X_DIG_CTRL1_BASE + 0x49)#define WSA884X_WAVG_PTRN_AMP0_1 (WSA884X_DIG_CTRL1_BASE + 0x4a)#define WSA884X_WAVG_PTRN_AMP1_0 (WSA884X_DIG_CTRL1_BASE + 0x4b)#define WSA884X_WAVG_PTRN_AMP1_1 (WSA884X_DIG_CTRL1_BASE + 0x4c)#define WSA884X_WAVG_PTRN_AMP2_0 (WSA884X_DIG_CTRL1_BASE + 0x4d)#define WSA884X_WAVG_PTRN_AMP2_1 (WSA884X_DIG_CTRL1_BASE + 0x4e)#define WSA884X_WAVG_PTRN_AMP3_0 (WSA884X_DIG_CTRL1_BASE + 0x4f)#define WSA884X_WAVG_PTRN_AMP3_1 (WSA884X_DIG_CTRL1_BASE + 0x50)#define WSA884X_WAVG_PTRN_AMP4_0 (WSA884X_DIG_CTRL1_BASE + 0x51)#define WSA884X_WAVG_PTRN_AMP4_1 (WSA884X_DIG_CTRL1_BASE + 0x52)#define WSA884X_WAVG_PTRN_AMP5_0 (WSA884X_DIG_CTRL1_BASE + 0x53)#define WSA884X_WAVG_PTRN_AMP5_1 (WSA884X_DIG_CTRL1_BASE + 0x54)#define WSA884X_WAVG_PTRN_AMP6_0 (WSA884X_DIG_CTRL1_BASE + 0x55)#define WSA884X_WAVG_PTRN_AMP6_1 (WSA884X_DIG_CTRL1_BASE + 0x56)#define WSA884X_WAVG_PTRN_AMP7_0 (WSA884X_DIG_CTRL1_BASE + 0x57)#define WSA884X_WAVG_PTRN_AMP7_1 (WSA884X_DIG_CTRL1_BASE + 0x58)#define WSA884X_WAVG_PER_0_1 (WSA884X_DIG_CTRL1_BASE + 0x59)#define WSA884X_WAVG_PER_2_3 (WSA884X_DIG_CTRL1_BASE + 0x5a)#define WSA884X_WAVG_PER_4_5 (WSA884X_DIG_CTRL1_BASE + 0x5b)#define WSA884X_WAVG_PER_6_7 (WSA884X_DIG_CTRL1_BASE + 0x5c)#define WSA884X_WAVG_STA (WSA884X_DIG_CTRL1_BASE + 0x5d)#define WSA884X_INTR_MODE (WSA884X_DIG_CTRL1_BASE + 0x80)#define WSA884X_INTR_MASK0 (WSA884X_DIG_CTRL1_BASE + 0x81)#define WSA884X_INTR_MASK1 (WSA884X_DIG_CTRL1_BASE + 0x82)#define WSA884X_INTR_STATUS0 (WSA884X_DIG_CTRL1_BASE + 0x83)#define WSA884X_INTR_STATUS1 (WSA884X_DIG_CTRL1_BASE + 0x84)#define WSA884X_INTR_CLEAR0 (WSA884X_DIG_CTRL1_BASE + 0x85)#define WSA884X_INTR_CLEAR1 (WSA884X_DIG_CTRL1_BASE + 0x86)#define WSA884X_INTR_LEVEL0 (WSA884X_DIG_CTRL1_BASE + 0x87)#define WSA884X_INTR_LEVEL1 (WSA884X_DIG_CTRL1_BASE + 0x88)#define WSA884X_INTR_SET0 (WSA884X_DIG_CTRL1_BASE + 0x89)#define WSA884X_INTR_SET1 (WSA884X_DIG_CTRL1_BASE + 0x8a)#define WSA884X_INTR_TEST0 (WSA884X_DIG_CTRL1_BASE + 0x8b)#define WSA884X_INTR_TEST1 (WSA884X_DIG_CTRL1_BASE + 0x8c)#define WSA884X_PDM_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc0)#define WSA884X_ATE_TEST_MODE (WSA884X_DIG_CTRL1_BASE + 0xc1)#define WSA884X_PA_FSM_DBG (WSA884X_DIG_CTRL1_BASE + 0xc2)#define WSA884X_DIG_DEBUG_MODE (WSA884X_DIG_CTRL1_BASE + 0xc3)#define WSA884X_DIG_DEBUG_SEL (WSA884X_DIG_CTRL1_BASE + 0xc4)#define WSA884X_DIG_DEBUG_EN (WSA884X_DIG_CTRL1_BASE + 0xc5)#define WSA884X_TADC_DETECT_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xc9)#define WSA884X_TADC_DEBUG_MSB (WSA884X_DIG_CTRL1_BASE + 0xca)#define WSA884X_TADC_DEBUG_LSB (WSA884X_DIG_CTRL1_BASE + 0xcb)#define WSA884X_SAMPLE_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcc)#define WSA884X_SWR_EDGE_SEL (WSA884X_DIG_CTRL1_BASE + 0xcd)#define WSA884X_TEST_MODE_CTL (WSA884X_DIG_CTRL1_BASE + 0xce)#define WSA884X_IOPAD_CTL (WSA884X_DIG_CTRL1_BASE + 0xcf)#define WSA884X_ANA_CSR_DBG_ADD (WSA884X_DIG_CTRL1_BASE + 0xd0)#define WSA884X_ANA_CSR_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd1)#define WSA884X_CLK_DBG_CTL (WSA884X_DIG_CTRL1_BASE + 0xd2)#define WSA884X_SPARE_R (WSA884X_DIG_CTRL1_BASE + 0xf0)#define WSA884X_SPARE_0 (WSA884X_DIG_CTRL1_BASE + 0xf1)#define WSA884X_SPARE_1 (WSA884X_DIG_CTRL1_BASE + 0xf2)#define WSA884X_SPARE_2 (WSA884X_DIG_CTRL1_BASE + 0xf3)#define WSA884X_SCODE (WSA884X_DIG_CTRL1_BASE + 0xff)#define WSA884X_DIG_TRIM_BASE (WSA884X_BASE + 0x0800)#define WSA884X_DIG_TRIM_PAGE (WSA884X_DIG_TRIM_BASE + 0x00)#define WSA884X_OTP_REG_0 (WSA884X_DIG_TRIM_BASE + 0x80)#define WSA884X_OTP_ID_WSA8840 0x0#define WSA884X_OTP_ID_WSA8845 0x5#define WSA884X_OTP_ID_WSA8845H 0xc#define WSA884X_OTP_REG_0_ID_MASK 0x0f#define WSA884X_OTP_REG_1 (WSA884X_DIG_TRIM_BASE + 0x81)#define WSA884X_OTP_REG_2 (WSA884X_DIG_TRIM_BASE + 0x82)#define WSA884X_OTP_REG_3 (WSA884X_DIG_TRIM_BASE + 0x83)#define WSA884X_OTP_REG_4 (WSA884X_DIG_TRIM_BASE + 0x84)#define WSA884X_OTP_REG_5 (WSA884X_DIG_TRIM_BASE + 0x85)#define WSA884X_OTP_REG_6 (WSA884X_DIG_TRIM_BASE + 0x86)#define WSA884X_OTP_REG_7 (WSA884X_DIG_TRIM_BASE + 0x87)#define WSA884X_OTP_REG_8 (WSA884X_DIG_TRIM_BASE + 0x88)#define WSA884X_OTP_REG_9 (WSA884X_DIG_TRIM_BASE + 0x89)#define WSA884X_OTP_REG_10 (WSA884X_DIG_TRIM_BASE + 0x8a)#define WSA884X_OTP_REG_11 (WSA884X_DIG_TRIM_BASE + 0x8b)#define WSA884X_OTP_REG_12 (WSA884X_DIG_TRIM_BASE + 0x8c)#define WSA884X_OTP_REG_13 (WSA884X_DIG_TRIM_BASE + 0x8d)#define WSA884X_OTP_REG_14 (WSA884X_DIG_TRIM_BASE + 0x8e)#define WSA884X_OTP_REG_15 (WSA884X_DIG_TRIM_BASE + 0x8f)#define WSA884X_OTP_REG_16 (WSA884X_DIG_TRIM_BASE + 0x90)#define WSA884X_OTP_REG_17 (WSA884X_DIG_TRIM_BASE + 0x91)#define WSA884X_OTP_REG_18 (WSA884X_DIG_TRIM_BASE + 0x92)#define WSA884X_OTP_REG_19 (WSA884X_DIG_TRIM_BASE + 0x93)#define WSA884X_OTP_REG_20 (WSA884X_DIG_TRIM_BASE + 0x94)#define WSA884X_OTP_REG_21 (WSA884X_DIG_TRIM_BASE + 0x95)#define WSA884X_OTP_REG_22 (WSA884X_DIG_TRIM_BASE + 0x96)#define WSA884X_OTP_REG_23 (WSA884X_DIG_TRIM_BASE + 0x97)#define WSA884X_OTP_REG_24 (WSA884X_DIG_TRIM_BASE + 0x98)#define WSA884X_OTP_REG_25 (WSA884X_DIG_TRIM_BASE + 0x99)#define WSA884X_OTP_REG_26 (WSA884X_DIG_TRIM_BASE + 0x9a)#define WSA884X_OTP_REG_27 (WSA884X_DIG_TRIM_BASE + 0x9b)#define WSA884X_OTP_REG_28 (WSA884X_DIG_TRIM_BASE + 0x9c)#define WSA884X_OTP_REG_29 (WSA884X_DIG_TRIM_BASE + 0x9d)#define WSA884X_OTP_REG_30 (WSA884X_DIG_TRIM_BASE + 0x9e)#define WSA884X_OTP_REG_31 (WSA884X_DIG_TRIM_BASE + 0x9f)#define WSA884X_OTP_REG_32 (WSA884X_DIG_TRIM_BASE + 0xa0)#define WSA884X_OTP_REG_33 (WSA884X_DIG_TRIM_BASE + 0xa1)#define WSA884X_OTP_REG_34 (WSA884X_DIG_TRIM_BASE + 0xa2)#define WSA884X_OTP_REG_35 (WSA884X_DIG_TRIM_BASE + 0xa3)#define WSA884X_OTP_REG_36 (WSA884X_DIG_TRIM_BASE + 0xa4)#define WSA884X_OTP_REG_37 (WSA884X_DIG_TRIM_BASE + 0xa5)#define WSA884X_OTP_REG_38 (WSA884X_DIG_TRIM_BASE + 0xa6)#define WSA884X_OTP_REG_38_RESERVER_MASK 0xf0#define WSA884X_OTP_REG_38_RESERVER_SHIFT 4#define WSA884X_OTP_REG_38_BST_CFG_SEL_MASK 0x08#define WSA884X_OTP_REG_38_BST_CFG_SEL_SHIFT 3#define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_MASK 0x07#define WSA884X_OTP_REG_38_BOOST_ILIM_TUNE_SHIFT 0#define WSA884X_OTP_REG_39 (WSA884X_DIG_TRIM_BASE + 0xa7)#define WSA884X_OTP_REG_40 (WSA884X_DIG_TRIM_BASE + 0xa8)#define WSA884X_OTP_REG_40_SPARE_TYPE2_MASK 0xc0#define WSA884X_OTP_REG_40_SPARE_TYPE2_SHIFT 6#define WSA884X_OTP_REG_40_ISENSE_RESCAL_MASK 0x3c#define WSA884X_OTP_REG_40_ISENSE_RESCAL_SHIFT 2#define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_MASK 0x2#define WSA884X_OTP_REG_40_ATE_BOOST_RDSON_TEST_SHIFT 1#define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_MASK 0x1#define WSA884X_OTP_REG_40_ATE_CLASSD_RDSON_TEST_SHIFT 0#define WSA884X_OTP_REG_41 (WSA884X_DIG_TRIM_BASE + 0xa9)#define WSA884X_OTP_REG_63 (WSA884X_DIG_TRIM_BASE + 0xbf)#define WSA884X_DIG_EMEM_BASE (WSA884X_BASE + 0x08C0)#define WSA884X_EMEM_0 (WSA884X_DIG_EMEM_BASE + 0x00)#define WSA884X_EMEM_1 (WSA884X_DIG_EMEM_BASE + 0x01)#define WSA884X_EMEM_2 (WSA884X_DIG_EMEM_BASE + 0x02)#define WSA884X_EMEM_3 (WSA884X_DIG_EMEM_BASE + 0x03)#define WSA884X_EMEM_4 (WSA884X_DIG_EMEM_BASE + 0x04)#define WSA884X_EMEM_5 (WSA884X_DIG_EMEM_BASE + 0x05)#define WSA884X_EMEM_6 (WSA884X_DIG_EMEM_BASE + 0x06)#define WSA884X_EMEM_7 (WSA884X_DIG_EMEM_BASE + 0x07)#define WSA884X_EMEM_8 (WSA884X_DIG_EMEM_BASE + 0x08)#define WSA884X_EMEM_9 (WSA884X_DIG_EMEM_BASE + 0x09)#define WSA884X_EMEM_10 (WSA884X_DIG_EMEM_BASE + 0x0a)#define WSA884X_EMEM_11 (WSA884X_DIG_EMEM_BASE + 0x0b)#define WSA884X_EMEM_12 (WSA884X_DIG_EMEM_BASE + 0x0c)#define WSA884X_EMEM_13 (WSA884X_DIG_EMEM_BASE + 0x0d)#define WSA884X_EMEM_14 (WSA884X_DIG_EMEM_BASE + 0x0e)#define WSA884X_EMEM_15 (WSA884X_DIG_EMEM_BASE + 0x0f)#define WSA884X_EMEM_16 (WSA884X_DIG_EMEM_BASE + 0x10)#define WSA884X_EMEM_17 (WSA884X_DIG_EMEM_BASE + 0x11)#define WSA884X_EMEM_18 (WSA884X_DIG_EMEM_BASE + 0x12)#define WSA884X_EMEM_19 (WSA884X_DIG_EMEM_BASE + 0x13)#define WSA884X_EMEM_20 (WSA884X_DIG_EMEM_BASE + 0x14)#define WSA884X_EMEM_21 (WSA884X_DIG_EMEM_BASE + 0x15)#define WSA884X_EMEM_22 (WSA884X_DIG_EMEM_BASE + 0x16)#define WSA884X_EMEM_23 (WSA884X_DIG_EMEM_BASE + 0x17)#define WSA884X_EMEM_24 (WSA884X_DIG_EMEM_BASE + 0x18)#define WSA884X_EMEM_25 (WSA884X_DIG_EMEM_BASE + 0x19)#define WSA884X_EMEM_26 (WSA884X_DIG_EMEM_BASE + 0x1a)#define WSA884X_EMEM_27 (WSA884X_DIG_EMEM_BASE + 0x1b)#define WSA884X_EMEM_28 (WSA884X_DIG_EMEM_BASE + 0x1c)#define WSA884X_EMEM_29 (WSA884X_DIG_EMEM_BASE + 0x1d)#define WSA884X_EMEM_30 (WSA884X_DIG_EMEM_BASE + 0x1e)#define WSA884X_EMEM_31 (WSA884X_DIG_EMEM_BASE + 0x1f)#define WSA884X_EMEM_32 (WSA884X_DIG_EMEM_BASE + 0x20)#define WSA884X_EMEM_33 (WSA884X_DIG_EMEM_BASE + 0x21)#define WSA884X_EMEM_34 (WSA884X_DIG_EMEM_BASE + 0x22)#define WSA884X_EMEM_35 (WSA884X_DIG_EMEM_BASE + 0x23)#define WSA884X_EMEM_36 (WSA884X_DIG_EMEM_BASE + 0x24)#define WSA884X_EMEM_37 (WSA884X_DIG_EMEM_BASE + 0x25)#define WSA884X_EMEM_38 (WSA884X_DIG_EMEM_BASE + 0x26)#define WSA884X_EMEM_39 (WSA884X_DIG_EMEM_BASE + 0x27)#define WSA884X_EMEM_40 (WSA884X_DIG_EMEM_BASE + 0x28)#define WSA884X_EMEM_41 (WSA884X_DIG_EMEM_BASE + 0x29)#define WSA884X_EMEM_42 (WSA884X_DIG_EMEM_BASE + 0x2a)#define WSA884X_EMEM_43 (WSA884X_DIG_EMEM_BASE + 0x2b)#define WSA884X_EMEM_44 (WSA884X_DIG_EMEM_BASE + 0x2c)#define WSA884X_EMEM_45 (WSA884X_DIG_EMEM_BASE + 0x2d)#define WSA884X_EMEM_46 (WSA884X_DIG_EMEM_BASE + 0x2e)#define WSA884X_EMEM_47 (WSA884X_DIG_EMEM_BASE + 0x2f)#define WSA884X_EMEM_48 (WSA884X_DIG_EMEM_BASE + 0x30)#define WSA884X_EMEM_49 (WSA884X_DIG_EMEM_BASE + 0x31)#define WSA884X_EMEM_50 (WSA884X_DIG_EMEM_BASE + 0x32)#define WSA884X_EMEM_51 (WSA884X_DIG_EMEM_BASE + 0x33)#define WSA884X_EMEM_52 (WSA884X_DIG_EMEM_BASE + 0x34)#define WSA884X_EMEM_53 (WSA884X_DIG_EMEM_BASE + 0x35)#define WSA884X_EMEM_54 (WSA884X_DIG_EMEM_BASE + 0x36)#define WSA884X_EMEM_55 (WSA884X_DIG_EMEM_BASE + 0x37)#define WSA884X_EMEM_56 (WSA884X_DIG_EMEM_BASE + 0x38)#define WSA884X_EMEM_57 (WSA884X_DIG_EMEM_BASE + 0x39)#define WSA884X_EMEM_58 (WSA884X_DIG_EMEM_BASE + 0x3a)#define WSA884X_EMEM_59 (WSA884X_DIG_EMEM_BASE + 0x3b)#define WSA884X_EMEM_60 (WSA884X_DIG_EMEM_BASE + 0x3c)#define WSA884X_EMEM_61 (WSA884X_DIG_EMEM_BASE + 0x3d)#define WSA884X_EMEM_62 (WSA884X_DIG_EMEM_BASE + 0x3e)#define WSA884X_EMEM_63 (WSA884X_DIG_EMEM_BASE + 0x3f)#define WSA884X_NUM_REGISTERS (WSA884X_EMEM_63 + 1)#define WSA884X_MAX_REGISTER (WSA884X_NUM_REGISTERS - 1)#define WSA884X_SUPPLIES_NUM 2#define WSA884X_MAX_SWR_PORTS 6#define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\/* Fractional Rates */ #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\#define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\/* Two-point trimming for temperature calibration */ #define WSA884X_T1_TEMP -10L#define WSA884X_T2_TEMP 150L/* * Device will report senseless data in many cases, so discard any measurements * outside of valid range. #define WSA884X_LOW_TEMP_THRESHOLD 5#define WSA884X_HIGH_TEMP_THRESHOLD 45struct wsa884x_priv {struct regmap *regmap;struct device *dev;struct regulator_bulk_data supplies[WSA884X_SUPPLIES_NUM];struct sdw_slave *slave;struct sdw_stream_config sconfig;struct sdw_stream_runtime *sruntime;struct sdw_port_config port_config[WSA884X_MAX_SWR_PORTS];struct gpio_desc *sd_n;struct reset_control *sd_reset;bool port_prepared[WSA884X_MAX_SWR_PORTS];bool port_enable[WSA884X_MAX_SWR_PORTS];int active_ports;int dev_mode;bool hw_init;/* * Protects temperature reading code (related to speaker protection) and * fields: temperature and pa_on. struct mutex sp_lock;unsigned int temperature;bool pa_on;enum {enum wsa884x_gain {enum wsa884x_isense {enum wsa884x_vsense {enum wsa884x_port_ids {static const char * const wsa884x_supply_name[] = {"vdd-io" ,"vdd-1p8" ,static const char * const wsa884x_dev_mode_text[] = {"Speaker" , "Receiver" enum wsa884x_mode {static const struct soc_enum wsa884x_dev_mode_enum =static struct sdw_dpn_prop wsa884x_sink_dpn_prop[WSA884X_MAX_SWR_PORTS] = {true ,true ,true ,true ,true ,true ,true ,true ,true ,true ,true ,true ,static const struct sdw_port_config wsa884x_pconfig[WSA884X_MAX_SWR_PORTS] = {static const struct reg_default wsa884x_defaults[] = {static bool wsa884x_readonly_register(struct device *dev, unsigned int reg)switch (reg) {case WSA884X_DOUT_MSB:case WSA884X_DOUT_LSB:case WSA884X_STATUS:case WSA884X_SPK_TOP_SPARE_TUNE_2:case WSA884X_SPK_TOP_SPARE_TUNE_3:case WSA884X_SPK_TOP_SPARE_TUNE_4:case WSA884X_SPARE_TUNE_5:case WSA884X_SPARE_TUNE_6:case WSA884X_SPARE_TUNE_7:case WSA884X_SPARE_TUNE_8:case WSA884X_SPARE_TUNE_9:case WSA884X_SPARE_TUNE_10:case WSA884X_PA_STATUS0:case WSA884X_PA_STATUS1:case WSA884X_PA_STATUS2:case WSA884X_PA_STATUS3:case WSA884X_PA_STATUS4:case WSA884X_PA_STATUS5:case WSA884X_SPARE_RO_1:case WSA884X_SPARE_RO_2:case WSA884X_SPARE_RO_3:case WSA884X_SPARE_RO_0:case WSA884X_BOOST_SPARE_RO_1:case WSA884X_STATUS_0:case WSA884X_STATUS_1:case WSA884X_CHIP_ID0:case WSA884X_CHIP_ID1:case WSA884X_CHIP_ID2:case WSA884X_CHIP_ID3:case WSA884X_BUS_ID:case WSA884X_PA_FSM_STA0:case WSA884X_PA_FSM_STA1:case WSA884X_PA_FSM_ERR_COND0:case WSA884X_PA_FSM_ERR_COND1:case WSA884X_TEMP_DIN_MSB:case WSA884X_TEMP_DIN_LSB:case WSA884X_TEMP_DOUT_MSB:case WSA884X_TEMP_DOUT_LSB:case WSA884X_VBAT_DIN_MSB:case WSA884X_VBAT_DIN_LSB:case WSA884X_VBAT_DOUT_MSB:case WSA884X_VBAT_DOUT_LSB:case WSA884X_VBAT_CAL_MSB:case WSA884X_VBAT_CAL_LSB:case WSA884X_VPHX_SYS_EN_STATUS:case WSA884X_PIN_STATUS:case WSA884X_SWR_HM_TEST1:case WSA884X_OTP_CTRL1:case WSA884X_OTP_STAT:case WSA884X_WAVG_STA:case WSA884X_INTR_STATUS0:case WSA884X_INTR_STATUS1:case WSA884X_ATE_TEST_MODE:case WSA884X_SPARE_R:return true ;return false ;static bool wsa884x_writeable_register(struct device *dev, unsigned int reg)return !wsa884x_readonly_register(dev, reg);static bool wsa884x_volatile_register(struct device *dev, unsigned int reg)switch (reg) {case WSA884X_ANA_WO_CTL_0:case WSA884X_ANA_WO_CTL_1:return true ;return wsa884x_readonly_register(dev, reg);static const struct regmap_config wsa884x_regmap_config = {true ,static const struct reg_sequence wsa884x_reg_init[] = {/* * Downstream suggests for batteries different than 1-Stacked (1S): * { WSA884X_TOP_CTRL1, 0xd3 & ~WSA884X_TOP_CTRL1_OCP_LOWVBAT_ITH_EN_MASK }, /* == 0xfe */ SK) |_SETTING_MASK, 0x8) |x6) |xf) },x20) },/* Speaker mode by default */ /* * WSA884X_CLSH_VTH values for speaker mode with G_21_DB system gain, * battery 1S and rload 8 Ohms. ,static void wsa884x_set_gain_parameters(struct wsa884x_priv *wsa884x)struct regmap *regmap = wsa884x->regmap;unsigned int min_gain, igain, vgain, comp_offset;/* * Downstream sets gain parameters customized per boards per use-case. * Choose here some sane values matching knowon users, like QRD8550 * board:. * * Values match here downstream: * For WSA884X_RECEIVER - G_7P5_DB system gain * For WSA884X_SPEAKER - G_21_DB system gain if (wsa884x->dev_mode == WSA884X_RECEIVER) {else {/* WSA884X_SPEAKER */ if (wsa884x->port_enable[WSA884X_PORT_COMP]) {else {
Messung V0.5 C=96 H=96 G=95
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