Quelle mt8186-reg.h
Sprache: C
/* SPDX-License-Identifier: GPL-2.0 * * mt8186-reg.h -- Mediatek 8186 audio driver reg definition * * Copyright (c) 2022 MediaTek Inc. * Author: Jiaxin Yu <jiaxin.yu@mediatek.com> #ifndef _MT8186_REG_H_#define _MT8186_REG_H_/* reg bit enum */ enum {/***************************************************************************** * R E G I S T E R D E F I N I T I O N /* AUDIO_TOP_CON0 */ #define RESERVED_SFT 31#define RESERVED_MASK_SFT BIT(31)#define AHB_IDLE_EN_INT_SFT 30#define AHB_IDLE_EN_INT_MASK_SFT BIT(30)#define AHB_IDLE_EN_EXT_SFT 29#define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)#define PDN_NLE_SFT 28#define PDN_NLE_MASK_SFT BIT(28)#define PDN_TML_SFT 27#define PDN_TML_MASK_SFT BIT(27)#define PDN_DAC_PREDIS_SFT 26#define PDN_DAC_PREDIS_MASK_SFT BIT(26)#define PDN_DAC_SFT 25#define PDN_DAC_MASK_SFT BIT(25)#define PDN_ADC_SFT 24#define PDN_ADC_MASK_SFT BIT(24)#define PDN_TDM_CK_SFT 20#define PDN_TDM_CK_MASK_SFT BIT(20)#define PDN_APLL_TUNER_SFT 19#define PDN_APLL_TUNER_MASK_SFT BIT(19)#define PDN_APLL2_TUNER_SFT 18#define PDN_APLL2_TUNER_MASK_SFT BIT(18)#define APB3_SEL_SFT 14#define APB3_SEL_MASK_SFT BIT(14)#define APB_R2T_SFT 13#define APB_R2T_MASK_SFT BIT(13)#define APB_W2T_SFT 12#define APB_W2T_MASK_SFT BIT(12)#define PDN_24M_SFT 9#define PDN_24M_MASK_SFT BIT(9)#define PDN_22M_SFT 8#define PDN_22M_MASK_SFT BIT(8)#define PDN_AFE_SFT 2#define PDN_AFE_MASK_SFT BIT(2)/* AUDIO_TOP_CON1 */ #define PDN_3RD_DAC_HIRES_SFT 31#define PDN_3RD_DAC_HIRES_MASK_SFT BIT(31)#define PDN_3RD_DAC_TML_SFT 30#define PDN_3RD_DAC_TML_MASK_SFT BIT(30)#define PDN_3RD_DAC_PREDIS_SFT 29#define PDN_3RD_DAC_PREDIS_MASK_SFT BIT(29)#define PDN_3RD_DAC_SFT 28#define PDN_3RD_DAC_MASK_SFT BIT(28)#define I2S_SOFT_RST5_SFT 22#define I2S_SOFT_RST5_MASK_SFT BIT(22)#define PDN_ADDA6_ADC_HIRES_SFT 21#define PDN_ADDA6_ADC_HIRES_MASK_SFT BIT(21)#define PDN_ADDA6_ADC_SFT 20#define PDN_ADDA6_ADC_MASK_SFT BIT(20)#define PDN_ADC_HIRES_TML_SFT 17#define PDN_ADC_HIRES_TML_MASK_SFT BIT(17)#define PDN_ADC_HIRES_SFT 16#define PDN_ADC_HIRES_MASK_SFT BIT(16)#define PDN_DAC_HIRES_SFT 15#define PDN_DAC_HIRES_MASK_SFT BIT(15)#define PDN_GENERAL2_ASRC_SFT 14#define PDN_GENERAL2_ASRC_MASK_SFT BIT(14)#define PDN_GENERAL1_ASRC_SFT 13#define PDN_GENERAL1_ASRC_MASK_SFT BIT(13)#define PDN_CONNSYS_I2S_ASRC_SFT 12#define PDN_CONNSYS_I2S_ASRC_MASK_SFT BIT(12)#define I2S4_BCLK_SW_CG_SFT 7#define I2S4_BCLK_SW_CG_MASK_SFT BIT(7)#define I2S3_BCLK_SW_CG_SFT 6#define I2S3_BCLK_SW_CG_MASK_SFT BIT(6)#define I2S2_BCLK_SW_CG_SFT 5#define I2S2_BCLK_SW_CG_MASK_SFT BIT(5)#define I2S1_BCLK_SW_CG_SFT 4#define I2S1_BCLK_SW_CG_MASK_SFT BIT(4)#define I2S_SOFT_RST2_SFT 2#define I2S_SOFT_RST2_MASK_SFT BIT(2)#define I2S_SOFT_RST_SFT 1#define I2S_SOFT_RST_MASK_SFT BIT(1)/* AUDIO_TOP_CON3 */ #define BUSY_SFT 31#define BUSY_MASK_SFT BIT(31)#define OS_DISABLE_SFT 30#define OS_DISABLE_MASK_SFT BIT(30)#define CG_DISABLE_SFT 29#define CG_DISABLE_MASK_SFT BIT(29)#define CLEAR_FLAG_SFT 0#define CLEAR_FLAG_MASK_SFT BIT(0)/* AFE_DAC_CON0 */ #define VUL12_ON_SFT 31#define VUL12_ON_MASK_SFT BIT(31)#define MOD_DAI_ON_SFT 30#define MOD_DAI_ON_MASK_SFT BIT(30)#define DAI_ON_SFT 29#define DAI_ON_MASK_SFT BIT(29)#define DAI2_ON_SFT 28#define DAI2_ON_MASK_SFT BIT(28)#define VUL6_ON_SFT 23#define VUL6_ON_MASK_SFT BIT(23)#define VUL5_ON_SFT 22#define VUL5_ON_MASK_SFT BIT(22)#define VUL4_ON_SFT 21#define VUL4_ON_MASK_SFT BIT(21)#define VUL3_ON_SFT 20#define VUL3_ON_MASK_SFT BIT(20)#define VUL2_ON_SFT 19#define VUL2_ON_MASK_SFT BIT(19)#define VUL_ON_SFT 18#define VUL_ON_MASK_SFT BIT(18)#define AWB2_ON_SFT 17#define AWB2_ON_MASK_SFT BIT(17)#define AWB_ON_SFT 16#define AWB_ON_MASK_SFT BIT(16)#define DL12_ON_SFT 15#define DL12_ON_MASK_SFT BIT(15)#define DL8_ON_SFT 11#define DL8_ON_MASK_SFT BIT(11)#define DL7_ON_SFT 10#define DL7_ON_MASK_SFT BIT(10)#define DL6_ON_SFT 9#define DL6_ON_MASK_SFT BIT(9)#define DL5_ON_SFT 8#define DL5_ON_MASK_SFT BIT(8)#define DL4_ON_SFT 7#define DL4_ON_MASK_SFT BIT(7)#define DL3_ON_SFT 6#define DL3_ON_MASK_SFT BIT(6)#define DL2_ON_SFT 5#define DL2_ON_MASK_SFT BIT(5)#define DL1_ON_SFT 4#define DL1_ON_MASK_SFT BIT(4)#define AUDIO_AFE_ON_SFT 0#define AUDIO_AFE_ON_MASK_SFT BIT(0)/* AFE_DAC_MON */ #define AFE_ON_RETM_SFT 0#define AFE_ON_RETM_MASK_SFT BIT(0)/* AFE_I2S_CON */ #define BCK_NEG_EG_LATCH_SFT 30#define BCK_NEG_EG_LATCH_MASK_SFT BIT(30)#define BCK_INV_SFT 29#define BCK_INV_MASK_SFT BIT(29)#define I2SIN_PAD_SEL_SFT 28#define I2SIN_PAD_SEL_MASK_SFT BIT(28)#define I2S_LOOPBACK_SFT 20#define I2S_LOOPBACK_MASK_SFT BIT(20)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)#define I2S1_HD_EN_SFT 12#define I2S1_HD_EN_MASK_SFT BIT(12)#define I2S_OUT_MODE_SFT 8#define I2S_OUT_MODE_MASK_SFT GENMASK(11, 8)#define INV_PAD_CTRL_SFT 7#define INV_PAD_CTRL_MASK_SFT BIT(7)#define I2S_BYPSRC_SFT 6#define I2S_BYPSRC_MASK_SFT BIT(6)#define INV_LRCK_SFT 5#define INV_LRCK_MASK_SFT BIT(5)#define I2S_FMT_SFT 3#define I2S_FMT_MASK_SFT BIT(3)#define I2S_SRC_SFT 2#define I2S_SRC_MASK_SFT BIT(2)#define I2S_WLEN_SFT 1#define I2S_WLEN_MASK_SFT BIT(1)#define I2S_EN_SFT 0#define I2S_EN_MASK_SFT BIT(0)/* AFE_I2S_CON1 */ #define I2S2_LR_SWAP_SFT 31#define I2S2_LR_SWAP_MASK_SFT BIT(31)#define I2S2_SEL_O19_O20_SFT 18#define I2S2_SEL_O19_O20_MASK_SFT BIT(18)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)#define I2S2_SEL_O03_O04_SFT 16#define I2S2_SEL_O03_O04_MASK_SFT BIT(16)#define I2S2_HD_EN_SFT 12#define I2S2_HD_EN_MASK_SFT BIT(12)#define I2S2_OUT_MODE_SFT 8#define I2S2_OUT_MODE_MASK_SFT GENMASK(11, 8)#define INV_LRCK_SFT 5#define INV_LRCK_MASK_SFT BIT(5)#define I2S2_FMT_SFT 3#define I2S2_FMT_MASK_SFT BIT(3)#define I2S2_WLEN_SFT 1#define I2S2_WLEN_MASK_SFT BIT(1)#define I2S2_EN_SFT 0#define I2S2_EN_MASK_SFT BIT(0)/* AFE_I2S_CON2 */ #define I2S3_LR_SWAP_SFT 31#define I2S3_LR_SWAP_MASK_SFT BIT(31)#define I2S3_UPDATE_WORD_SFT 24#define I2S3_UPDATE_WORD_MASK_SFT GENMASK(28, 24)#define I2S3_BCK_INV_SFT 23#define I2S3_BCK_INV_MASK_SFT BIT(23)#define I2S3_FPGA_BIT_TEST_SFT 22#define I2S3_FPGA_BIT_TEST_MASK_SFT BIT(22)#define I2S3_FPGA_BIT_SFT 21#define I2S3_FPGA_BIT_MASK_SFT BIT(21)#define I2S3_LOOPBACK_SFT 20#define I2S3_LOOPBACK_MASK_SFT BIT(20)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)#define I2S3_HD_EN_SFT 12#define I2S3_HD_EN_MASK_SFT BIT(12)#define I2S3_OUT_MODE_SFT 8#define I2S3_OUT_MODE_MASK_SFT GENMASK(11, 8)#define I2S3_FMT_SFT 3#define I2S3_FMT_MASK_SFT BIT(3)#define I2S3_WLEN_SFT 1#define I2S3_WLEN_MASK_SFT BIT(1)#define I2S3_EN_SFT 0#define I2S3_EN_MASK_SFT BIT(0)/* AFE_I2S_CON3 */ #define I2S4_LR_SWAP_SFT 31#define I2S4_LR_SWAP_MASK_SFT BIT(31)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)#define I2S4_HD_EN_SFT 12#define I2S4_HD_EN_MASK_SFT BIT(12)#define I2S4_OUT_MODE_SFT 8#define I2S4_OUT_MODE_MASK_SFT GENMASK(11, 8)#define INV_LRCK_SFT 5#define INV_LRCK_MASK_SFT BIT(5)#define I2S4_FMT_SFT 3#define I2S4_FMT_MASK_SFT BIT(3)#define I2S4_WLEN_SFT 1#define I2S4_WLEN_MASK_SFT BIT(1)#define I2S4_EN_SFT 0#define I2S4_EN_MASK_SFT BIT(0)/* AFE_I2S_CON4 */ #define I2S_LOOPBACK_SFT 20#define I2S_LOOPBACK_MASK 0x1#define I2S_LOOPBACK_MASK_SFT BIT(20)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT BIT(5)/* AFE_CONNSYS_I2S_CON */ #define BCK_NEG_EG_LATCH_SFT 30#define BCK_NEG_EG_LATCH_MASK_SFT BIT(30)#define BCK_INV_SFT 29#define BCK_INV_MASK_SFT BIT(29)#define I2SIN_PAD_SEL_SFT 28#define I2SIN_PAD_SEL_MASK_SFT BIT(28)#define I2S_LOOPBACK_SFT 20#define I2S_LOOPBACK_MASK_SFT BIT(20)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT BIT(17)#define I2S_MODE_SFT 8#define I2S_MODE_MASK_SFT GENMASK(11, 8)#define INV_PAD_CTRL_SFT 7#define INV_PAD_CTRL_MASK_SFT BIT(7)#define I2S_BYPSRC_SFT 6#define I2S_BYPSRC_MASK_SFT BIT(6)#define INV_LRCK_SFT 5#define INV_LRCK_MASK_SFT BIT(5)#define I2S_FMT_SFT 3#define I2S_FMT_MASK_SFT BIT(3)#define I2S_SRC_SFT 2#define I2S_SRC_MASK_SFT BIT(2)#define I2S_WLEN_SFT 1#define I2S_WLEN_MASK_SFT BIT(1)#define I2S_EN_SFT 0#define I2S_EN_MASK_SFT BIT(0)/* AFE_ASRC_2CH_CON2 */ #define CHSET_O16BIT_SFT 19#define CHSET_O16BIT_MASK_SFT BIT(19)#define CHSET_CLR_IIR_HISTORY_SFT 17#define CHSET_CLR_IIR_HISTORY_MASK_SFT BIT(17)#define CHSET_IS_MONO_SFT 16#define CHSET_IS_MONO_MASK_SFT BIT(16)#define CHSET_IIR_EN_SFT 11#define CHSET_IIR_EN_MASK_SFT BIT(11)#define CHSET_IIR_STAGE_SFT 8#define CHSET_IIR_STAGE_MASK_SFT GENMASK(10, 8)#define CHSET_STR_CLR_SFT 5#define CHSET_STR_CLR_MASK_SFT BIT(5)#define CHSET_ON_SFT 2#define CHSET_ON_MASK_SFT BIT(2)#define COEFF_SRAM_CTRL_SFT 1#define COEFF_SRAM_CTRL_MASK_SFT BIT(1)#define ASM_ON_SFT 0#define ASM_ON_MASK_SFT BIT(0)/* AFE_GAIN1_CON0 */ #define GAIN1_SAMPLE_PER_STEP_SFT 8#define GAIN1_SAMPLE_PER_STEP_MASK_SFT GENMASK(15, 8)#define GAIN1_MODE_SFT 4#define GAIN1_MODE_MASK_SFT GENMASK(7, 4)#define GAIN1_ON_SFT 0#define GAIN1_ON_MASK_SFT BIT(0)/* AFE_GAIN1_CON1 */ #define GAIN1_TARGET_SFT 0#define GAIN1_TARGET_MASK 0xfffffff#define GAIN1_TARGET_MASK_SFT GENMASK(27, 0)/* AFE_GAIN2_CON0 */ #define GAIN2_SAMPLE_PER_STEP_SFT 8#define GAIN2_SAMPLE_PER_STEP_MASK_SFT GENMASK(15, 8)#define GAIN2_MODE_SFT 4#define GAIN2_MODE_MASK_SFT GENMASK(7, 4)#define GAIN2_ON_SFT 0#define GAIN2_ON_MASK_SFT BIT(0)/* AFE_GAIN2_CON1 */ #define GAIN2_TARGET_SFT 0#define GAIN2_TARGET_MASK 0xfffffff#define GAIN2_TARGET_MASK_SFT GENMASK(27, 0)/* AFE_GAIN1_CUR */ #define AFE_GAIN1_CUR_SFT 0#define AFE_GAIN1_CUR_MASK_SFT GENMASK(27, 0)/* AFE_GAIN2_CUR */ #define AFE_GAIN2_CUR_SFT 0#define AFE_GAIN2_CUR_MASK_SFT GENMASK(27, 0)/* PCM_INTF_CON1 */ #define PCM_FIX_VALUE_SEL_SFT 31#define PCM_FIX_VALUE_SEL_MASK_SFT BIT(31)#define PCM_BUFFER_LOOPBACK_SFT 30#define PCM_BUFFER_LOOPBACK_MASK_SFT BIT(30)#define PCM_PARALLEL_LOOPBACK_SFT 29#define PCM_PARALLEL_LOOPBACK_MASK_SFT BIT(29)#define PCM_SERIAL_LOOPBACK_SFT 28#define PCM_SERIAL_LOOPBACK_MASK_SFT BIT(28)#define PCM_DAI_PCM_LOOPBACK_SFT 27#define PCM_DAI_PCM_LOOPBACK_MASK_SFT BIT(27)#define PCM_I2S_PCM_LOOPBACK_SFT 26#define PCM_I2S_PCM_LOOPBACK_MASK_SFT BIT(26)#define PCM_SYNC_DELSEL_SFT 25#define PCM_SYNC_DELSEL_MASK_SFT BIT(25)#define PCM_TX_LR_SWAP_SFT 24#define PCM_TX_LR_SWAP_MASK_SFT BIT(24)#define PCM_SYNC_OUT_INV_SFT 23#define PCM_SYNC_OUT_INV_MASK_SFT BIT(23)#define PCM_BCLK_OUT_INV_SFT 22#define PCM_BCLK_OUT_INV_MASK_SFT BIT(22)#define PCM_SYNC_IN_INV_SFT 21#define PCM_SYNC_IN_INV_MASK_SFT BIT(21)#define PCM_BCLK_IN_INV_SFT 20#define PCM_BCLK_IN_INV_MASK_SFT BIT(20)#define PCM_TX_LCH_RPT_SFT 19#define PCM_TX_LCH_RPT_MASK_SFT BIT(19)#define PCM_VBT_16K_MODE_SFT 18#define PCM_VBT_16K_MODE_MASK_SFT BIT(18)#define PCM_EXT_MODEM_SFT 17#define PCM_EXT_MODEM_MASK_SFT BIT(17)#define PCM_24BIT_SFT 16#define PCM_24BIT_MASK_SFT BIT(16)#define PCM_WLEN_SFT 14#define PCM_WLEN_MASK_SFT GENMASK(15, 14)#define PCM_SYNC_LENGTH_SFT 9#define PCM_SYNC_LENGTH_MASK_SFT GENMASK(13, 9)#define PCM_SYNC_TYPE_SFT 8#define PCM_SYNC_TYPE_MASK_SFT BIT(8)#define PCM_BT_MODE_SFT 7#define PCM_BT_MODE_MASK_SFT BIT(7)#define PCM_BYP_ASRC_SFT 6#define PCM_BYP_ASRC_MASK_SFT BIT(6)#define PCM_SLAVE_SFT 5#define PCM_SLAVE_MASK_SFT BIT(5)#define PCM_MODE_SFT 3#define PCM_MODE_MASK_SFT GENMASK(4, 3)#define PCM_FMT_SFT 1#define PCM_FMT_MASK_SFT GENMASK(2, 1)#define PCM_EN_SFT 0#define PCM_EN_MASK_SFT BIT(0)/* PCM_INTF_CON2 */ #define PCM1_TX_FIFO_OV_SFT 31#define PCM1_TX_FIFO_OV_MASK_SFT BIT(31)#define PCM1_RX_FIFO_OV_SFT 30#define PCM1_RX_FIFO_OV_MASK_SFT BIT(30)#define PCM2_TX_FIFO_OV_SFT 29#define PCM2_TX_FIFO_OV_MASK_SFT BIT(29)#define PCM2_RX_FIFO_OV_SFT 28#define PCM2_RX_FIFO_OV_MASK_SFT BIT(28)#define PCM1_SYNC_GLITCH_SFT 27#define PCM1_SYNC_GLITCH_MASK_SFT BIT(27)#define PCM2_SYNC_GLITCH_SFT 26#define PCM2_SYNC_GLITCH_MASK_SFT BIT(26)#define TX3_RCH_DBG_MODE_SFT 17#define TX3_RCH_DBG_MODE_MASK_SFT BIT(17)#define PCM1_PCM2_LOOPBACK_SFT 16#define PCM1_PCM2_LOOPBACK_MASK_SFT BIT(16)#define DAI_PCM_LOOPBACK_CH_SFT 14#define DAI_PCM_LOOPBACK_CH_MASK_SFT GENMASK(15, 14)#define I2S_PCM_LOOPBACK_CH_SFT 12#define I2S_PCM_LOOPBACK_CH_MASK_SFT GENMASK(13, 12)#define TX_FIX_VALUE_SFT 0#define TX_FIX_VALUE_MASK_SFT GENMASK(7, 0)/* PCM2_INTF_CON */ #define PCM2_TX_FIX_VALUE_SFT 24#define PCM2_TX_FIX_VALUE_MASK_SFT GENMASK(31, 24)#define PCM2_FIX_VALUE_SEL_SFT 23#define PCM2_FIX_VALUE_SEL_MASK_SFT BIT(23)#define PCM2_BUFFER_LOOPBACK_SFT 22#define PCM2_BUFFER_LOOPBACK_MASK_SFT BIT(22)#define PCM2_PARALLEL_LOOPBACK_SFT 21#define PCM2_PARALLEL_LOOPBACK_MASK_SFT BIT(21)#define PCM2_SERIAL_LOOPBACK_SFT 20#define PCM2_SERIAL_LOOPBACK_MASK_SFT BIT(20)#define PCM2_DAI_PCM_LOOPBACK_SFT 19#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT BIT(19)#define PCM2_I2S_PCM_LOOPBACK_SFT 18#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT BIT(18)#define PCM2_SYNC_DELSEL_SFT 17#define PCM2_SYNC_DELSEL_MASK_SFT BIT(17)#define PCM2_TX_LR_SWAP_SFT 16#define PCM2_TX_LR_SWAP_MASK_SFT BIT(16)#define PCM2_SYNC_IN_INV_SFT 15#define PCM2_SYNC_IN_INV_MASK_SFT BIT(15)#define PCM2_BCLK_IN_INV_SFT 14#define PCM2_BCLK_IN_INV_MASK_SFT BIT(14)#define PCM2_TX_LCH_RPT_SFT 13#define PCM2_TX_LCH_RPT_MASK_SFT BIT(13)#define PCM2_VBT_16K_MODE_SFT 12#define PCM2_VBT_16K_MODE_MASK_SFT BIT(12)#define PCM2_LOOPBACK_CH_SEL_SFT 10#define PCM2_LOOPBACK_CH_SEL_MASK_SFT GENMASK(11, 10)#define PCM2_TX2_BT_MODE_SFT 8#define PCM2_TX2_BT_MODE_MASK_SFT BIT(8)#define PCM2_BT_MODE_SFT 7#define PCM2_BT_MODE_MASK_SFT BIT(7)#define PCM2_AFIFO_SFT 6#define PCM2_AFIFO_MASK_SFT BIT(6)#define PCM2_WLEN_SFT 5#define PCM2_WLEN_MASK_SFT BIT(5)#define PCM2_MODE_SFT 3#define PCM2_MODE_MASK_SFT GENMASK(4, 3)#define PCM2_FMT_SFT 1#define PCM2_FMT_MASK_SFT GENMASK(2, 1)#define PCM2_EN_SFT 0#define PCM2_EN_MASK_SFT BIT(0)// AFE_CM1_CON #define CHANNEL_MERGE0_DEBUG_MODE_SFT (31)#define CHANNEL_MERGE0_DEBUG_MODE_MASK_SFT BIT(31)#define VUL3_BYPASS_CM_SFT (30)#define VUL3_BYPASS_CM_MASK (0x1)#define VUL3_BYPASS_CM_MASK_SFT BIT(30)#define CM1_DEBUG_MODE_SEL_SFT (29)#define CM1_DEBUG_MODE_SEL_MASK_SFT BIT(29)#define CHANNEL_MERGE0_UPDATE_CNT_SFT (16)#define CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT GENMASK(28, 16)#define CM1_FS_SELECT_SFT (8)#define CM1_FS_SELECT_MASK_SFT GENMASK(12, 8)#define CHANNEL_MERGE0_CHNUM_SFT (3)#define CHANNEL_MERGE0_CHNUM_MASK_SFT GENMASK(7, 3)#define CHANNEL_MERGE0_BYTE_SWAP_SFT (1)#define CHANNEL_MERGE0_BYTE_SWAP_MASK_SFT BIT(1)#define CHANNEL_MERGE0_EN_SFT (0)#define CHANNEL_MERGE0_EN_MASK_SFT BIT(0)/* AFE_ADDA_MTKAIF_CFG0 */ #define MTKAIF_RXIF_CLKINV_ADC_SFT 31#define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT BIT(31)#define MTKAIF_RXIF_BYPASS_SRC_SFT 17#define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT BIT(17)#define MTKAIF_RXIF_PROTOCOL2_SFT 16#define MTKAIF_RXIF_PROTOCOL2_MASK_SFT BIT(16)#define MTKAIF_TXIF_BYPASS_SRC_SFT 5#define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT BIT(5)#define MTKAIF_TXIF_PROTOCOL2_SFT 4#define MTKAIF_TXIF_PROTOCOL2_MASK_SFT BIT(4)#define MTKAIF_TXIF_8TO5_SFT 2#define MTKAIF_TXIF_8TO5_MASK_SFT BIT(2)#define MTKAIF_RXIF_8TO5_SFT 1#define MTKAIF_RXIF_8TO5_MASK_SFT BIT(1)#define MTKAIF_IF_LOOPBACK1_SFT 0#define MTKAIF_IF_LOOPBACK1_MASK_SFT BIT(0)/* AFE_ADDA_MTKAIF_RX_CFG2 */ #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 16#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT BIT(16)#define MTKAIF_RXIF_DELAY_CYCLE_SFT 12#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT GENMASK(15, 12)#define MTKAIF_RXIF_DELAY_DATA_SFT 8#define MTKAIF_RXIF_DELAY_DATA_MASK 0x1#define MTKAIF_RXIF_DELAY_DATA_MASK_SFT BIT(8)#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT GENMASK(6, 4)/* AFE_ADDA_DL_SRC2_CON0 */ #define DL_2_INPUT_MODE_CTL_SFT 28#define DL_2_INPUT_MODE_CTL_MASK_SFT GENMASK(31, 28)#define DL_2_CH1_SATURATION_EN_CTL_SFT 27#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT BIT(27)#define DL_2_CH2_SATURATION_EN_CTL_SFT 26#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT BIT(26)#define DL_2_OUTPUT_SEL_CTL_SFT 24#define DL_2_OUTPUT_SEL_CTL_MASK_SFT GENMASK(25, 24)#define DL_2_FADEIN_0START_EN_SFT 16#define DL_2_FADEIN_0START_EN_MASK_SFT GENMASK(17, 16)#define DL_DISABLE_HW_CG_CTL_SFT 15#define DL_DISABLE_HW_CG_CTL_MASK_SFT BIT(15)#define C_DATA_EN_SEL_CTL_PRE_SFT 14#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT BIT(14)#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT BIT(13)#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT BIT(12)#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT BIT(11)#define DL2_ARAMPSP_CTL_PRE_SFT 9#define DL2_ARAMPSP_CTL_PRE_MASK_SFT GENMASK(10, 9)#define DL_2_IIRMODE_CTL_PRE_SFT 6#define DL_2_IIRMODE_CTL_PRE_MASK_SFT GENMASK(8, 6)#define DL_2_VOICE_MODE_CTL_PRE_SFT 5#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT BIT(5)#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT BIT(4)#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT BIT(3)#define DL_2_IIR_ON_CTL_PRE_SFT 2#define DL_2_IIR_ON_CTL_PRE_MASK_SFT BIT(2)#define DL_2_GAIN_ON_CTL_PRE_SFT 1#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT BIT(1)#define DL_2_SRC_ON_CTL_PRE_SFT 0#define DL_2_SRC_ON_CTL_PRE_MASK_SFT BIT(0)/* AFE_ADDA_DL_SRC2_CON1 */ #define DL_2_GAIN_CTL_PRE_SFT 16#define DL_2_GAIN_CTL_PRE_MASK 0xffff#define DL_2_GAIN_CTL_PRE_MASK_SFT GENMASK(31, 16)#define DL_2_GAIN_MODE_CTL_SFT 0#define DL_2_GAIN_MODE_CTL_MASK_SFT BIT(0)/* AFE_ADDA_UL_SRC_CON0 */ #define ULCF_CFG_EN_CTL_SFT 31#define ULCF_CFG_EN_CTL_MASK_SFT BIT(31)#define UL_DMIC_PHASE_SEL_CH1_SFT 27#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT GENMASK(29, 27)#define UL_DMIC_PHASE_SEL_CH2_SFT 24#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT GENMASK(26, 24)#define UL_MODE_3P25M_CH2_CTL_SFT 22#define UL_MODE_3P25M_CH2_CTL_MASK_SFT BIT(22)#define UL_MODE_3P25M_CH1_CTL_SFT 21#define UL_MODE_3P25M_CH1_CTL_MASK_SFT BIT(21)#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT GENMASK(19, 17)#define UL_AP_DMIC_ON_SFT 16#define UL_AP_DMIC_ON_MASK_SFT BIT(16)#define DMIC_LOW_POWER_CTL_SFT 14#define DMIC_LOW_POWER_CTL_MASK_SFT GENMASK(15, 14)#define UL_DISABLE_HW_CG_CTL_SFT 12#define UL_DISABLE_HW_CG_CTL_MASK_SFT BIT(12)#define UL_IIR_ON_TMP_CTL_SFT 10#define UL_IIR_ON_TMP_CTL_MASK_SFT BIT(10)#define UL_IIRMODE_CTL_SFT 7#define UL_IIRMODE_CTL_MASK_SFT GENMASK(9, 7)#define DIGMIC_4P33M_SEL_SFT 6#define DIGMIC_4P33M_SEL_MASK_SFT BIT(6)#define DIGMIC_3P25M_1P625M_SEL_SFT 5#define DIGMIC_3P25M_1P625M_SEL_MASK_SFT BIT(5)#define UL_LOOP_BACK_MODE_SFT 2#define UL_LOOP_BACK_MODE_MASK_SFT BIT(2)#define UL_SDM_3_LEVEL_SFT 1#define UL_SDM_3_LEVEL_MASK_SFT BIT(1)#define UL_SRC_ON_CTL_SFT 0#define UL_SRC_ON_CTL_MASK_SFT BIT(0)/* AFE_ADDA_UL_SRC_CON1 */ #define C_DAC_EN_CTL_SFT 27#define C_DAC_EN_CTL_MASK_SFT BIT(27)#define C_MUTE_SW_CTL_SFT 26#define C_MUTE_SW_CTL_MASK_SFT BIT(26)#define ASDM_SRC_SEL_CTL_SFT 25#define ASDM_SRC_SEL_CTL_MASK_SFT BIT(25)#define C_AMP_DIV_CH2_CTL_SFT 21#define C_AMP_DIV_CH2_CTL_MASK_SFT GENMASK(23, 21)#define C_FREQ_DIV_CH2_CTL_SFT 16#define C_FREQ_DIV_CH2_CTL_MASK_SFT GENMASK(20, 16)#define C_SINE_MODE_CH2_CTL_SFT 12#define C_SINE_MODE_CH2_CTL_MASK_SFT GENMASK(15, 12)#define C_AMP_DIV_CH1_CTL_SFT 9#define C_AMP_DIV_CH1_CTL_MASK_SFT GENMASK(11, 9)#define C_FREQ_DIV_CH1_CTL_SFT 4#define C_FREQ_DIV_CH1_CTL_MASK_SFT GENMASK(8, 4)#define C_SINE_MODE_CH1_CTL_SFT 0#define C_SINE_MODE_CH1_CTL_MASK_SFT GENMASK(3, 0)/* AFE_ADDA_TOP_CON0 */ #define C_LOOP_BACK_MODE_CTL_SFT 12#define C_LOOP_BACK_MODE_CTL_MASK_SFT GENMASK(15, 12)#define ADDA_UL_GAIN_MODE_SFT 8#define ADDA_UL_GAIN_MODE_MASK_SFT GENMASK(9, 8)#define C_EXT_ADC_CTL_SFT 0#define C_EXT_ADC_CTL_MASK_SFT BIT(0)/* AFE_ADDA_UL_DL_CON0 */ #define AFE_ADDA_UL_LR_SWAP_SFT 31#define AFE_ADDA_UL_LR_SWAP_MASK_SFT BIT(31)#define AFE_ADDA_CKDIV_RST_SFT 30#define AFE_ADDA_CKDIV_RST_MASK_SFT BIT(30)#define AFE_ADDA_FIFO_AUTO_RST_SFT 29#define AFE_ADDA_FIFO_AUTO_RST_MASK_SFT BIT(29)#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_SFT 21#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK_SFT GENMASK(22, 21)#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 20#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT BIT(20)#define AFE_ADDA6_UL_LR_SWAP_SFT 15#define AFE_ADDA6_UL_LR_SWAP_MASK_SFT BIT(15)#define AFE_ADDA6_CKDIV_RST_SFT 14#define AFE_ADDA6_CKDIV_RST_MASK_SFT BIT(14)#define AFE_ADDA6_FIFO_AUTO_RST_SFT 13#define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT BIT(13)#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_SFT 5#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK_SFT GENMASK(6, 5)#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 4#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT BIT(4)#define ADDA_AFE_ON_SFT 0#define ADDA_AFE_ON_MASK_SFT BIT(0)/* AFE_SIDETONE_CON0 */ #define R_RDY_SFT 30#define R_RDY_MASK_SFT BIT(30)#define W_RDY_SFT 29#define W_RDY_MASK_SFT BIT(29)#define R_W_EN_SFT 25#define R_W_EN_MASK_SFT BIT(25)#define R_W_SEL_SFT 24#define R_W_SEL_MASK_SFT BIT(24)#define SEL_CH2_SFT 23#define SEL_CH2_MASK_SFT BIT(23)#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT GENMASK(20, 16)#define SIDE_TONE_COEFFICIENT_SFT 0#define SIDE_TONE_COEFFICIENT_MASK_SFT GENMASK(15, 0)/* AFE_SIDETONE_COEFF */ #define SIDE_TONE_COEFF_SFT 0#define SIDE_TONE_COEFF_MASK_SFT GENMASK(15, 0)/* AFE_SIDETONE_CON1 */ #define STF_BYPASS_MODE_SFT 31#define STF_BYPASS_MODE_MASK_SFT BIT(31)#define STF_BYPASS_MODE_O28_O29_SFT 30#define STF_BYPASS_MODE_O28_O29_MASK_SFT BIT(30)#define STF_BYPASS_MODE_I2S4_SFT 29#define STF_BYPASS_MODE_I2S4_MASK_SFT BIT(29)#define STF_BYPASS_MODE_DL3_SFT 27#define STF_BYPASS_MODE_DL3_MASK_SFT BIT(27)#define STF_BYPASS_MODE_I2S7_SFT 26#define STF_BYPASS_MODE_I2S7_MASK_SFT BIT(26)#define STF_BYPASS_MODE_I2S9_SFT 25#define STF_BYPASS_MODE_I2S9_MASK_SFT BIT(25)#define STF_O19O20_OUT_EN_SEL_SFT 13#define STF_O19O20_OUT_EN_SEL_MASK_SFT BIT(13)#define STF_SOURCE_FROM_O19O20_SFT 12#define STF_SOURCE_FROM_O19O20_MASK_SFT BIT(12)#define SIDE_TONE_ON_SFT 8#define SIDE_TONE_ON_MASK_SFT BIT(8)#define SIDE_TONE_HALF_TAP_NUM_SFT 0#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT GENMASK(5, 0)/* AFE_SIDETONE_GAIN */ #define POSITIVE_GAIN_SFT 16#define POSITIVE_GAIN_MASK_SFT GENMASK(18, 16)#define SIDE_TONE_GAIN_SFT 0#define SIDE_TONE_GAIN_MASK_SFT GENMASK(15, 0)/* AFE_ADDA_DL_SDM_DCCOMP_CON */ #define USE_3RD_SDM_SFT 28#define USE_3RD_SDM_MASK_SFT BIT(28)#define DL_FIFO_START_POINT_SFT 24#define DL_FIFO_START_POINT_MASK_SFT GENMASK(26, 24)#define DL_FIFO_SWAP_SFT 20#define DL_FIFO_SWAP_MASK_SFT BIT(20)#define C_AUDSDM1ORDSELECT_CTL_SFT 19#define C_AUDSDM1ORDSELECT_CTL_MASK_SFT BIT(19)#define C_SDM7BITSEL_CTL_SFT 18#define C_SDM7BITSEL_CTL_MASK_SFT BIT(18)#define GAIN_AT_SDM_RST_PRE_CTL_SFT 15#define GAIN_AT_SDM_RST_PRE_CTL_MASK_SFT BIT(15)#define DL_DCM_AUTO_IDLE_EN_SFT 14#define DL_DCM_AUTO_IDLE_EN_MASK_SFT BIT(14)#define AFE_DL_SRC_DCM_EN_SFT 13#define AFE_DL_SRC_DCM_EN_MASK_SFT BIT(13)#define AFE_DL_POST_SRC_DCM_EN_SFT 12#define AFE_DL_POST_SRC_DCM_EN_MASK_SFT BIT(12)#define AUD_SDM_MONO_SFT 9#define AUD_SDM_MONO_MASK_SFT BIT(9)#define AUD_DC_COMP_EN_SFT 8#define AUD_DC_COMP_EN_MASK_SFT BIT(8)#define ATTGAIN_CTL_SFT 0#define ATTGAIN_CTL_MASK_SFT GENMASK(5, 0)/* AFE_SINEGEN_CON0 */ #define DAC_EN_SFT 26#define DAC_EN_MASK 0x1#define DAC_EN_MASK_SFT BIT(26)#define MUTE_SW_CH2_SFT 25#define MUTE_SW_CH2_MASK 0x1#define MUTE_SW_CH2_MASK_SFT BIT(25)#define MUTE_SW_CH1_SFT 24#define MUTE_SW_CH1_MASK 0x1#define MUTE_SW_CH1_MASK_SFT BIT(24)#define SINE_MODE_CH2_SFT 20#define SINE_MODE_CH2_MASK 0xf#define SINE_MODE_CH2_MASK_SFT GENMASK(23, 20)#define AMP_DIV_CH2_SFT 17#define AMP_DIV_CH2_MASK 0x7#define AMP_DIV_CH2_MASK_SFT GENMASK(19, 17)#define FREQ_DIV_CH2_SFT 12#define FREQ_DIV_CH2_MASK 0x1f#define FREQ_DIV_CH2_MASK_SFT GENMASK(16, 12)#define SINE_MODE_CH1_SFT 8#define SINE_MODE_CH1_MASK 0xf#define SINE_MODE_CH1_MASK_SFT GENMASK(11, 8)#define AMP_DIV_CH1_SFT 5#define AMP_DIV_CH1_MASK 0x7#define AMP_DIV_CH1_MASK_SFT GENMASK(7, 5)#define FREQ_DIV_CH1_SFT 0#define FREQ_DIV_CH1_MASK 0x1f#define FREQ_DIV_CH1_MASK_SFT GENMASK(4, 0)/* AFE_SINEGEN_CON2 */ #define INNER_LOOP_BACK_MODE_SFT 0#define INNER_LOOP_BACK_MODE_MASK_SFT GENMASK(7, 0)/* AFE_HD_ENGEN_ENABLE */ #define AFE_24M_ON_SFT 1#define AFE_24M_ON_MASK_SFT BIT(1)#define AFE_22M_ON_SFT 0#define AFE_22M_ON_MASK_SFT BIT(0)/* AFE_ADDA_DL_NLE_FIFO_MON */ #define DL_NLE_FIFO_WBIN_SFT 8#define DL_NLE_FIFO_WBIN_MASK_SFT GENMASK(11, 8)#define DL_NLE_FIFO_RBIN_SFT 4#define DL_NLE_FIFO_RBIN_MASK_SFT GENMASK(7, 4)#define DL_NLE_FIFO_RDACTIVE_SFT 3#define DL_NLE_FIFO_RDACTIVE_MASK_SFT BIT(3)#define DL_NLE_FIFO_STARTRD_SFT 2#define DL_NLE_FIFO_STARTRD_MASK_SFT BIT(2)#define DL_NLE_FIFO_RD_EMPTY_SFT 1#define DL_NLE_FIFO_RD_EMPTY_MASK_SFT BIT(1)#define DL_NLE_FIFO_WR_FULL_SFT 0#define DL_NLE_FIFO_WR_FULL_MASK_SFT BIT(0)/* AFE_DL1_CON0 */ #define DL1_MODE_SFT 24#define DL1_MODE_MASK 0xf#define DL1_MODE_MASK_SFT GENMASK(27, 24)#define DL1_MINLEN_SFT 20#define DL1_MINLEN_MASK 0xf#define DL1_MINLEN_MASK_SFT GENMASK(23, 20)#define DL1_MAXLEN_SFT 16#define DL1_MAXLEN_MASK 0xf#define DL1_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL1_SW_CLEAR_BUF_EMPTY_SFT 15#define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL1_PBUF_SIZE_SFT 12#define DL1_PBUF_SIZE_MASK 0x3#define DL1_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL1_MONO_SFT 8#define DL1_MONO_MASK 0x1#define DL1_MONO_MASK_SFT BIT(8)#define DL1_NORMAL_MODE_SFT 5#define DL1_NORMAL_MODE_MASK 0x1#define DL1_NORMAL_MODE_MASK_SFT BIT(5)#define DL1_HALIGN_SFT 4#define DL1_HALIGN_MASK 0x1#define DL1_HALIGN_MASK_SFT BIT(4)#define DL1_HD_MODE_SFT 0#define DL1_HD_MODE_MASK 0x3#define DL1_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DL2_CON0 */ #define DL2_MODE_SFT 24#define DL2_MODE_MASK 0xf#define DL2_MODE_MASK_SFT GENMASK(27, 24)#define DL2_MINLEN_SFT 20#define DL2_MINLEN_MASK 0xf#define DL2_MINLEN_MASK_SFT GENMASK(23, 20)#define DL2_MAXLEN_SFT 16#define DL2_MAXLEN_MASK 0xf#define DL2_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL2_SW_CLEAR_BUF_EMPTY_SFT 15#define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL2_PBUF_SIZE_SFT 12#define DL2_PBUF_SIZE_MASK 0x3#define DL2_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL2_MONO_SFT 8#define DL2_MONO_MASK 0x1#define DL2_MONO_MASK_SFT BIT(8)#define DL2_NORMAL_MODE_SFT 5#define DL2_NORMAL_MODE_MASK 0x1#define DL2_NORMAL_MODE_MASK_SFT BIT(5)#define DL2_HALIGN_SFT 4#define DL2_HALIGN_MASK 0x1#define DL2_HALIGN_MASK_SFT BIT(4)#define DL2_HD_MODE_SFT 0#define DL2_HD_MODE_MASK 0x3#define DL2_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DL3_CON0 */ #define DL3_MODE_SFT 24#define DL3_MODE_MASK 0xf#define DL3_MODE_MASK_SFT GENMASK(27, 24)#define DL3_MINLEN_SFT 20#define DL3_MINLEN_MASK 0xf#define DL3_MINLEN_MASK_SFT GENMASK(23, 20)#define DL3_MAXLEN_SFT 16#define DL3_MAXLEN_MASK 0xf#define DL3_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL3_SW_CLEAR_BUF_EMPTY_SFT 15#define DL3_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL3_PBUF_SIZE_SFT 12#define DL3_PBUF_SIZE_MASK 0x3#define DL3_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL3_MONO_SFT 8#define DL3_MONO_MASK 0x1#define DL3_MONO_MASK_SFT BIT(8)#define DL3_NORMAL_MODE_SFT 5#define DL3_NORMAL_MODE_MASK 0x1#define DL3_NORMAL_MODE_MASK_SFT BIT(5)#define DL3_HALIGN_SFT 4#define DL3_HALIGN_MASK 0x1#define DL3_HALIGN_MASK_SFT BIT(4)#define DL3_HD_MODE_SFT 0#define DL3_HD_MODE_MASK 0x3#define DL3_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DL4_CON0 */ #define DL4_MODE_SFT 24#define DL4_MODE_MASK 0xf#define DL4_MODE_MASK_SFT GENMASK(27, 24)#define DL4_MINLEN_SFT 20#define DL4_MINLEN_MASK 0xf#define DL4_MINLEN_MASK_SFT GENMASK(23, 20)#define DL4_MAXLEN_SFT 16#define DL4_MAXLEN_MASK 0xf#define DL4_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL4_SW_CLEAR_BUF_EMPTY_SFT 15#define DL4_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL4_PBUF_SIZE_SFT 12#define DL4_PBUF_SIZE_MASK 0x3#define DL4_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL4_MONO_SFT 8#define DL4_MONO_MASK 0x1#define DL4_MONO_MASK_SFT BIT(8)#define DL4_NORMAL_MODE_SFT 5#define DL4_NORMAL_MODE_MASK 0x1#define DL4_NORMAL_MODE_MASK_SFT BIT(5)#define DL4_HALIGN_SFT 4#define DL4_HALIGN_MASK 0x1#define DL4_HALIGN_MASK_SFT BIT(4)#define DL4_HD_MODE_SFT 0#define DL4_HD_MODE_MASK 0x3#define DL4_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DL5_CON0 */ #define DL5_MODE_SFT 24#define DL5_MODE_MASK 0xf#define DL5_MODE_MASK_SFT GENMASK(27, 24)#define DL5_MINLEN_SFT 20#define DL5_MINLEN_MASK 0xf#define DL5_MINLEN_MASK_SFT GENMASK(23, 20)#define DL5_MAXLEN_SFT 16#define DL5_MAXLEN_MASK 0xf#define DL5_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL5_SW_CLEAR_BUF_EMPTY_SFT 15#define DL5_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL5_PBUF_SIZE_SFT 12#define DL5_PBUF_SIZE_MASK 0x3#define DL5_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL5_MONO_SFT 8#define DL5_MONO_MASK 0x1#define DL5_MONO_MASK_SFT BIT(8)#define DL5_NORMAL_MODE_SFT 5#define DL5_NORMAL_MODE_MASK 0x1#define DL5_NORMAL_MODE_MASK_SFT BIT(5)#define DL5_HALIGN_SFT 4#define DL5_HALIGN_MASK 0x1#define DL5_HALIGN_MASK_SFT BIT(4)#define DL5_HD_MODE_SFT 0#define DL5_HD_MODE_MASK 0x3#define DL5_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DL6_CON0 */ #define DL6_MODE_SFT 24#define DL6_MODE_MASK 0xf#define DL6_MODE_MASK_SFT GENMASK(27, 24)#define DL6_MINLEN_SFT 20#define DL6_MINLEN_MASK 0xf#define DL6_MINLEN_MASK_SFT GENMASK(23, 20)#define DL6_MAXLEN_SFT 16#define DL6_MAXLEN_MASK 0xf#define DL6_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL6_SW_CLEAR_BUF_EMPTY_SFT 15#define DL6_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL6_PBUF_SIZE_SFT 12#define DL6_PBUF_SIZE_MASK 0x3#define DL6_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL6_MONO_SFT 8#define DL6_MONO_MASK 0x1#define DL6_MONO_MASK_SFT BIT(8)#define DL6_NORMAL_MODE_SFT 5#define DL6_NORMAL_MODE_MASK 0x1#define DL6_NORMAL_MODE_MASK_SFT BIT(5)#define DL6_HALIGN_SFT 4#define DL6_HALIGN_MASK 0x1#define DL6_HALIGN_MASK_SFT BIT(4)#define DL6_HD_MODE_SFT 0#define DL6_HD_MODE_MASK 0x3#define DL6_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DL7_CON0 */ #define DL7_MODE_SFT 24#define DL7_MODE_MASK 0xf#define DL7_MODE_MASK_SFT GENMASK(27, 24)#define DL7_MINLEN_SFT 20#define DL7_MINLEN_MASK 0xf#define DL7_MINLEN_MASK_SFT GENMASK(23, 20)#define DL7_MAXLEN_SFT 16#define DL7_MAXLEN_MASK 0xf#define DL7_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL7_SW_CLEAR_BUF_EMPTY_SFT 15#define DL7_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL7_PBUF_SIZE_SFT 12#define DL7_PBUF_SIZE_MASK 0x3#define DL7_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL7_MONO_SFT 8#define DL7_MONO_MASK 0x1#define DL7_MONO_MASK_SFT BIT(8)#define DL7_NORMAL_MODE_SFT 5#define DL7_NORMAL_MODE_MASK 0x1#define DL7_NORMAL_MODE_MASK_SFT BIT(5)#define DL7_HALIGN_SFT 4#define DL7_HALIGN_MASK 0x1#define DL7_HALIGN_MASK_SFT BIT(4)#define DL7_HD_MODE_SFT 0#define DL7_HD_MODE_MASK 0x3#define DL7_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DL8_CON0 */ #define DL8_MODE_SFT 24#define DL8_MODE_MASK 0xf#define DL8_MODE_MASK_SFT GENMASK(27, 24)#define DL8_MINLEN_SFT 20#define DL8_MINLEN_MASK 0xf#define DL8_MINLEN_MASK_SFT GENMASK(23, 20)#define DL8_MAXLEN_SFT 16#define DL8_MAXLEN_MASK 0xf#define DL8_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL8_SW_CLEAR_BUF_EMPTY_SFT 15#define DL8_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL8_PBUF_SIZE_SFT 12#define DL8_PBUF_SIZE_MASK 0x3#define DL8_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL8_MONO_SFT 8#define DL8_MONO_MASK 0x1#define DL8_MONO_MASK_SFT BIT(8)#define DL8_NORMAL_MODE_SFT 5#define DL8_NORMAL_MODE_MASK 0x1#define DL8_NORMAL_MODE_MASK_SFT BIT(5)#define DL8_HALIGN_SFT 4#define DL8_HALIGN_MASK 0x1#define DL8_HALIGN_MASK_SFT BIT(4)#define DL8_HD_MODE_SFT 0#define DL8_HD_MODE_MASK 0x3#define DL8_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DL12_CON0 */ #define DL12_MODE_SFT 24#define DL12_MODE_MASK 0xf#define DL12_MODE_MASK_SFT GENMASK(27, 24)#define DL12_MINLEN_SFT 20#define DL12_MINLEN_MASK 0xf#define DL12_MINLEN_MASK_SFT GENMASK(23, 20)#define DL12_MAXLEN_SFT 16#define DL12_MAXLEN_MASK 0xf#define DL12_MAXLEN_MASK_SFT GENMASK(19, 16)#define DL12_SW_CLEAR_BUF_EMPTY_SFT 15#define DL12_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL12_SW_CLEAR_BUF_EMPTY_MASK_SFT BIT(15)#define DL12_PBUF_SIZE_SFT 12#define DL12_PBUF_SIZE_MASK 0x3#define DL12_PBUF_SIZE_MASK_SFT GENMASK(13, 12)#define DL12_4CH_EN_SFT 11#define DL12_4CH_EN_MASK 0x1#define DL12_4CH_EN_MASK_SFT BIT(11)#define DL12_MONO_SFT 8#define DL12_MONO_MASK 0x1#define DL12_MONO_MASK_SFT BIT(8)#define DL12_NORMAL_MODE_SFT 5#define DL12_NORMAL_MODE_MASK 0x1#define DL12_NORMAL_MODE_MASK_SFT BIT(5)#define DL12_HALIGN_SFT 4#define DL12_HALIGN_MASK 0x1#define DL12_HALIGN_MASK_SFT BIT(4)#define DL12_HD_MODE_SFT 0#define DL12_HD_MODE_MASK 0x3#define DL12_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_AWB_CON0 */ #define AWB_MODE_SFT 24#define AWB_MODE_MASK 0xf#define AWB_MODE_MASK_SFT GENMASK(27, 24)#define AWB_SW_CLEAR_BUF_FULL_SFT 15#define AWB_SW_CLEAR_BUF_FULL_MASK 0x1#define AWB_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define AWB_R_MONO_SFT 9#define AWB_R_MONO_MASK 0x1#define AWB_R_MONO_MASK_SFT BIT(9)#define AWB_MONO_SFT 8#define AWB_MONO_MASK 0x1#define AWB_MONO_MASK_SFT BIT(8)#define AWB_WR_SIGN_SFT 6#define AWB_WR_SIGN_MASK 0x1#define AWB_WR_SIGN_MASK_SFT BIT(6)#define AWB_NORMAL_MODE_SFT 5#define AWB_NORMAL_MODE_MASK 0x1#define AWB_NORMAL_MODE_MASK_SFT BIT(5)#define AWB_HALIGN_SFT 4#define AWB_HALIGN_MASK 0x1#define AWB_HALIGN_MASK_SFT BIT(4)#define AWB_HD_MODE_SFT 0#define AWB_HD_MODE_MASK 0x3#define AWB_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_AWB2_CON0 */ #define AWB2_MODE_SFT 24#define AWB2_MODE_MASK 0xf#define AWB2_MODE_MASK_SFT GENMASK(27, 24)#define AWB2_SW_CLEAR_BUF_FULL_SFT 15#define AWB2_SW_CLEAR_BUF_FULL_MASK 0x1#define AWB2_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define AWB2_R_MONO_SFT 9#define AWB2_R_MONO_MASK 0x1#define AWB2_R_MONO_MASK_SFT BIT(9)#define AWB2_MONO_SFT 8#define AWB2_MONO_MASK 0x1#define AWB2_MONO_MASK_SFT BIT(8)#define AWB2_WR_SIGN_SFT 6#define AWB2_WR_SIGN_MASK 0x1#define AWB2_WR_SIGN_MASK_SFT BIT(6)#define AWB2_NORMAL_MODE_SFT 5#define AWB2_NORMAL_MODE_MASK 0x1#define AWB2_NORMAL_MODE_MASK_SFT BIT(5)#define AWB2_HALIGN_SFT 4#define AWB2_HALIGN_MASK 0x1#define AWB2_HALIGN_MASK_SFT BIT(4)#define AWB2_HD_MODE_SFT 0#define AWB2_HD_MODE_MASK 0x3#define AWB2_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_VUL_CON0 */ #define VUL_MODE_SFT 24#define VUL_MODE_MASK 0xf#define VUL_MODE_MASK_SFT GENMASK(27, 24)#define VUL_SW_CLEAR_BUF_FULL_SFT 15#define VUL_SW_CLEAR_BUF_FULL_MASK 0x1#define VUL_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define VUL_R_MONO_SFT 9#define VUL_R_MONO_MASK 0x1#define VUL_R_MONO_MASK_SFT BIT(9)#define VUL_MONO_SFT 8#define VUL_MONO_MASK 0x1#define VUL_MONO_MASK_SFT BIT(8)#define VUL_WR_SIGN_SFT 6#define VUL_WR_SIGN_MASK 0x1#define VUL_WR_SIGN_MASK_SFT BIT(6)#define VUL_NORMAL_MODE_SFT 5#define VUL_NORMAL_MODE_MASK 0x1#define VUL_NORMAL_MODE_MASK_SFT BIT(5)#define VUL_HALIGN_SFT 4#define VUL_HALIGN_MASK 0x1#define VUL_HALIGN_MASK_SFT BIT(4)#define VUL_HD_MODE_SFT 0#define VUL_HD_MODE_MASK 0x3#define VUL_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_VUL12_CON0 */ #define VUL12_MODE_SFT 24#define VUL12_MODE_MASK 0xf#define VUL12_MODE_MASK_SFT GENMASK(27, 24)#define VUL12_SW_CLEAR_BUF_FULL_SFT 15#define VUL12_SW_CLEAR_BUF_FULL_MASK 0x1#define VUL12_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define VUL12_4CH_EN_SFT 11#define VUL12_4CH_EN_MASK 0x1#define VUL12_4CH_EN_MASK_SFT BIT(11)#define VUL12_R_MONO_SFT 9#define VUL12_R_MONO_MASK 0x1#define VUL12_R_MONO_MASK_SFT BIT(9)#define VUL12_MONO_SFT 8#define VUL12_MONO_MASK 0x1#define VUL12_MONO_MASK_SFT BIT(8)#define VUL12_WR_SIGN_SFT 6#define VUL12_WR_SIGN_MASK 0x1#define VUL12_WR_SIGN_MASK_SFT BIT(6)#define VUL12_NORMAL_MODE_SFT 5#define VUL12_NORMAL_MODE_MASK 0x1#define VUL12_NORMAL_MODE_MASK_SFT BIT(5)#define VUL12_HALIGN_SFT 4#define VUL12_HALIGN_MASK 0x1#define VUL12_HALIGN_MASK_SFT BIT(4)#define VUL12_HD_MODE_SFT 0#define VUL12_HD_MODE_MASK 0x3#define VUL12_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_VUL2_CON0 */ #define VUL2_MODE_SFT 24#define VUL2_MODE_MASK 0xf#define VUL2_MODE_MASK_SFT GENMASK(27, 24)#define VUL2_SW_CLEAR_BUF_FULL_SFT 15#define VUL2_SW_CLEAR_BUF_FULL_MASK 0x1#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define VUL2_R_MONO_SFT 9#define VUL2_R_MONO_MASK 0x1#define VUL2_R_MONO_MASK_SFT BIT(9)#define VUL2_MONO_SFT 8#define VUL2_MONO_MASK 0x1#define VUL2_MONO_MASK_SFT BIT(8)#define VUL2_WR_SIGN_SFT 6#define VUL2_WR_SIGN_MASK 0x1#define VUL2_WR_SIGN_MASK_SFT BIT(6)#define VUL2_NORMAL_MODE_SFT 5#define VUL2_NORMAL_MODE_MASK 0x1#define VUL2_NORMAL_MODE_MASK_SFT BIT(5)#define VUL2_HALIGN_SFT 4#define VUL2_HALIGN_MASK 0x1#define VUL2_HALIGN_MASK_SFT BIT(4)#define VUL2_HD_MODE_SFT 0#define VUL2_HD_MODE_MASK 0x3#define VUL2_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_VUL3_CON0 */ #define VUL3_MODE_SFT 24#define VUL3_MODE_MASK 0xf#define VUL3_MODE_MASK_SFT GENMASK(27, 24)#define VUL3_SW_CLEAR_BUF_FULL_SFT 15#define VUL3_SW_CLEAR_BUF_FULL_MASK 0x1#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define VUL3_R_MONO_SFT 9#define VUL3_R_MONO_MASK 0x1#define VUL3_R_MONO_MASK_SFT BIT(9)#define VUL3_MONO_SFT 8#define VUL3_MONO_MASK 0x1#define VUL3_MONO_MASK_SFT BIT(8)#define VUL3_WR_SIGN_SFT 6#define VUL3_WR_SIGN_MASK 0x1#define VUL3_WR_SIGN_MASK_SFT BIT(6)#define VUL3_NORMAL_MODE_SFT 5#define VUL3_NORMAL_MODE_MASK 0x1#define VUL3_NORMAL_MODE_MASK_SFT BIT(5)#define VUL3_HALIGN_SFT 4#define VUL3_HALIGN_MASK 0x1#define VUL3_HALIGN_MASK_SFT BIT(4)#define VUL3_HD_MODE_SFT 0#define VUL3_HD_MODE_MASK 0x3#define VUL3_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_VUL4_CON0 */ #define VUL4_MODE_SFT 24#define VUL4_MODE_MASK 0xf#define VUL4_MODE_MASK_SFT GENMASK(27, 24)#define VUL4_SW_CLEAR_BUF_FULL_SFT 15#define VUL4_SW_CLEAR_BUF_FULL_MASK 0x1#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define VUL4_R_MONO_SFT 9#define VUL4_R_MONO_MASK 0x1#define VUL4_R_MONO_MASK_SFT BIT(9)#define VUL4_MONO_SFT 8#define VUL4_MONO_MASK 0x1#define VUL4_MONO_MASK_SFT BIT(8)#define VUL4_WR_SIGN_SFT 6#define VUL4_WR_SIGN_MASK 0x1#define VUL4_WR_SIGN_MASK_SFT BIT(6)#define VUL4_NORMAL_MODE_SFT 5#define VUL4_NORMAL_MODE_MASK 0x1#define VUL4_NORMAL_MODE_MASK_SFT BIT(5)#define VUL4_HALIGN_SFT 4#define VUL4_HALIGN_MASK 0x1#define VUL4_HALIGN_MASK_SFT BIT(4)#define VUL4_HD_MODE_SFT 0#define VUL4_HD_MODE_MASK 0x3#define VUL4_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_VUL5_CON0 */ #define VUL5_MODE_SFT 24#define VUL5_MODE_MASK 0xf#define VUL5_MODE_MASK_SFT GENMASK(27, 24)#define VUL5_SW_CLEAR_BUF_FULL_SFT 15#define VUL5_SW_CLEAR_BUF_FULL_MASK 0x1#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define VUL5_R_MONO_SFT 9#define VUL5_R_MONO_MASK 0x1#define VUL5_R_MONO_MASK_SFT BIT(9)#define VUL5_MONO_SFT 8#define VUL5_MONO_MASK 0x1#define VUL5_MONO_MASK_SFT BIT(8)#define VUL5_WR_SIGN_SFT 6#define VUL5_WR_SIGN_MASK 0x1#define VUL5_WR_SIGN_MASK_SFT BIT(6)#define VUL5_NORMAL_MODE_SFT 5#define VUL5_NORMAL_MODE_MASK 0x1#define VUL5_NORMAL_MODE_MASK_SFT BIT(5)#define VUL5_HALIGN_SFT 4#define VUL5_HALIGN_MASK 0x1#define VUL5_HALIGN_MASK_SFT BIT(4)#define VUL5_HD_MODE_SFT 0#define VUL5_HD_MODE_MASK 0x3#define VUL5_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_VUL6_CON0 */ #define VUL6_MODE_SFT 24#define VUL6_MODE_MASK 0xf#define VUL6_MODE_MASK_SFT GENMASK(27, 24)#define VUL6_SW_CLEAR_BUF_FULL_SFT 15#define VUL6_SW_CLEAR_BUF_FULL_MASK 0x1#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define VUL6_R_MONO_SFT 9#define VUL6_R_MONO_MASK 0x1#define VUL6_R_MONO_MASK_SFT BIT(9)#define VUL6_MONO_SFT 8#define VUL6_MONO_MASK 0x1#define VUL6_MONO_MASK_SFT BIT(8)#define VUL6_WR_SIGN_SFT 6#define VUL6_WR_SIGN_MASK 0x1#define VUL6_WR_SIGN_MASK_SFT BIT(6)#define VUL6_NORMAL_MODE_SFT 5#define VUL6_NORMAL_MODE_MASK 0x1#define VUL6_NORMAL_MODE_MASK_SFT BIT(5)#define VUL6_HALIGN_SFT 4#define VUL6_HALIGN_MASK 0x1#define VUL6_HALIGN_MASK_SFT BIT(4)#define VUL6_HD_MODE_SFT 0#define VUL6_HD_MODE_MASK 0x3#define VUL6_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DAI_CON0 */ #define DAI_MODE_SFT 24#define DAI_MODE_MASK 0x3#define DAI_MODE_MASK_SFT GENMASK(25, 24)#define DAI_SW_CLEAR_BUF_FULL_SFT 15#define DAI_SW_CLEAR_BUF_FULL_MASK 0x1#define DAI_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define DAI_DUPLICATE_WR_SFT 10#define DAI_DUPLICATE_WR_MASK 0x1#define DAI_DUPLICATE_WR_MASK_SFT BIT(10)#define DAI_MONO_SFT 8#define DAI_MONO_MASK 0x1#define DAI_MONO_MASK_SFT BIT(8)#define DAI_WR_SIGN_SFT 6#define DAI_WR_SIGN_MASK 0x1#define DAI_WR_SIGN_MASK_SFT BIT(6)#define DAI_NORMAL_MODE_SFT 5#define DAI_NORMAL_MODE_MASK 0x1#define DAI_NORMAL_MODE_MASK_SFT BIT(5)#define DAI_HALIGN_SFT 4#define DAI_HALIGN_MASK 0x1#define DAI_HALIGN_MASK_SFT BIT(4)#define DAI_HD_MODE_SFT 0#define DAI_HD_MODE_MASK 0x3#define DAI_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_MOD_DAI_CON0 */ #define MOD_DAI_MODE_SFT 24#define MOD_DAI_MODE_MASK 0x3#define MOD_DAI_MODE_MASK_SFT GENMASK(25, 24)#define MOD_DAI_SW_CLEAR_BUF_FULL_SFT 15#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK 0x1#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define MOD_DAI_DUPLICATE_WR_SFT 10#define MOD_DAI_DUPLICATE_WR_MASK 0x1#define MOD_DAI_DUPLICATE_WR_MASK_SFT BIT(10)#define MOD_DAI_MONO_SFT 8#define MOD_DAI_MONO_MASK 0x1#define MOD_DAI_MONO_MASK_SFT BIT(8)#define MOD_DAI_WR_SIGN_SFT 6#define MOD_DAI_WR_SIGN_MASK 0x1#define MOD_DAI_WR_SIGN_MASK_SFT BIT(6)#define MOD_DAI_NORMAL_MODE_SFT 5#define MOD_DAI_NORMAL_MODE_MASK 0x1#define MOD_DAI_NORMAL_MODE_MASK_SFT BIT(5)#define MOD_DAI_HALIGN_SFT 4#define MOD_DAI_HALIGN_MASK 0x1#define MOD_DAI_HALIGN_MASK_SFT BIT(4)#define MOD_DAI_HD_MODE_SFT 0#define MOD_DAI_HD_MODE_MASK 0x3#define MOD_DAI_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_DAI2_CON0 */ #define DAI2_MODE_SFT 24#define DAI2_MODE_MASK 0xf#define DAI2_MODE_MASK_SFT GENMASK(27, 24)#define DAI2_SW_CLEAR_BUF_FULL_SFT 15#define DAI2_SW_CLEAR_BUF_FULL_MASK 0x1#define DAI2_SW_CLEAR_BUF_FULL_MASK_SFT BIT(15)#define DAI2_DUPLICATE_WR_SFT 10#define DAI2_DUPLICATE_WR_MASK 0x1#define DAI2_DUPLICATE_WR_MASK_SFT BIT(10)#define DAI2_MONO_SFT 8#define DAI2_MONO_MASK 0x1#define DAI2_MONO_MASK_SFT BIT(8)#define DAI2_WR_SIGN_SFT 6#define DAI2_WR_SIGN_MASK 0x1#define DAI2_WR_SIGN_MASK_SFT BIT(6)#define DAI2_NORMAL_MODE_SFT 5#define DAI2_NORMAL_MODE_MASK 0x1#define DAI2_NORMAL_MODE_MASK_SFT BIT(5)#define DAI2_HALIGN_SFT 4#define DAI2_HALIGN_MASK 0x1#define DAI2_HALIGN_MASK_SFT BIT(4)#define DAI2_HD_MODE_SFT 0#define DAI2_HD_MODE_MASK 0x3#define DAI2_HD_MODE_MASK_SFT GENMASK(1, 0)/* AFE_MEMIF_CON0 */ #define CPU_COMPACT_MODE_SFT 2#define CPU_COMPACT_MODE_MASK_SFT BIT(2)#define CPU_HD_ALIGN_SFT 1#define CPU_HD_ALIGN_MASK_SFT BIT(1)#define SYSRAM_SIGN_SFT 0#define SYSRAM_SIGN_MASK_SFT BIT(0)/* AFE_IRQ_MCU_CON0 */ #define IRQ31_MCU_ON_SFT 31#define IRQ31_MCU_ON_MASK 0x1#define IRQ31_MCU_ON_MASK_SFT BIT(31)#define IRQ26_MCU_ON_SFT 26#define IRQ26_MCU_ON_MASK 0x1#define IRQ26_MCU_ON_MASK_SFT BIT(26)#define IRQ25_MCU_ON_SFT 25#define IRQ25_MCU_ON_MASK 0x1#define IRQ25_MCU_ON_MASK_SFT BIT(25)#define IRQ24_MCU_ON_SFT 24#define IRQ24_MCU_ON_MASK 0x1#define IRQ24_MCU_ON_MASK_SFT BIT(24)#define IRQ23_MCU_ON_SFT 23#define IRQ23_MCU_ON_MASK 0x1#define IRQ23_MCU_ON_MASK_SFT BIT(23)#define IRQ22_MCU_ON_SFT 22#define IRQ22_MCU_ON_MASK 0x1#define IRQ22_MCU_ON_MASK_SFT BIT(22)#define IRQ21_MCU_ON_SFT 21#define IRQ21_MCU_ON_MASK 0x1#define IRQ21_MCU_ON_MASK_SFT BIT(21)#define IRQ20_MCU_ON_SFT 20#define IRQ20_MCU_ON_MASK 0x1#define IRQ20_MCU_ON_MASK_SFT BIT(20)#define IRQ19_MCU_ON_SFT 19#define IRQ19_MCU_ON_MASK 0x1#define IRQ19_MCU_ON_MASK_SFT BIT(19)#define IRQ18_MCU_ON_SFT 18#define IRQ18_MCU_ON_MASK 0x1#define IRQ18_MCU_ON_MASK_SFT BIT(18)#define IRQ17_MCU_ON_SFT 17#define IRQ17_MCU_ON_MASK 0x1#define IRQ17_MCU_ON_MASK_SFT BIT(17)#define IRQ16_MCU_ON_SFT 16#define IRQ16_MCU_ON_MASK 0x1#define IRQ16_MCU_ON_MASK_SFT BIT(16)#define IRQ15_MCU_ON_SFT 15#define IRQ15_MCU_ON_MASK 0x1#define IRQ15_MCU_ON_MASK_SFT BIT(15)#define IRQ14_MCU_ON_SFT 14#define IRQ14_MCU_ON_MASK 0x1#define IRQ14_MCU_ON_MASK_SFT BIT(14)#define IRQ13_MCU_ON_SFT 13#define IRQ13_MCU_ON_MASK 0x1#define IRQ13_MCU_ON_MASK_SFT BIT(13)#define IRQ12_MCU_ON_SFT 12#define IRQ12_MCU_ON_MASK 0x1#define IRQ12_MCU_ON_MASK_SFT BIT(12)#define IRQ11_MCU_ON_SFT 11#define IRQ11_MCU_ON_MASK 0x1#define IRQ11_MCU_ON_MASK_SFT BIT(11)#define IRQ10_MCU_ON_SFT 10#define IRQ10_MCU_ON_MASK 0x1#define IRQ10_MCU_ON_MASK_SFT BIT(10)#define IRQ9_MCU_ON_SFT 9#define IRQ9_MCU_ON_MASK 0x1#define IRQ9_MCU_ON_MASK_SFT BIT(9)#define IRQ8_MCU_ON_SFT 8#define IRQ8_MCU_ON_MASK 0x1#define IRQ8_MCU_ON_MASK_SFT BIT(8)#define IRQ7_MCU_ON_SFT 7#define IRQ7_MCU_ON_MASK 0x1#define IRQ7_MCU_ON_MASK_SFT BIT(7)#define IRQ6_MCU_ON_SFT 6#define IRQ6_MCU_ON_MASK 0x1#define IRQ6_MCU_ON_MASK_SFT BIT(6)#define IRQ5_MCU_ON_SFT 5#define IRQ5_MCU_ON_MASK 0x1#define IRQ5_MCU_ON_MASK_SFT BIT(5)#define IRQ4_MCU_ON_SFT 4#define IRQ4_MCU_ON_MASK 0x1#define IRQ4_MCU_ON_MASK_SFT BIT(4)#define IRQ3_MCU_ON_SFT 3#define IRQ3_MCU_ON_MASK 0x1#define IRQ3_MCU_ON_MASK_SFT BIT(3)#define IRQ2_MCU_ON_SFT 2#define IRQ2_MCU_ON_MASK 0x1#define IRQ2_MCU_ON_MASK_SFT BIT(2)#define IRQ1_MCU_ON_SFT 1#define IRQ1_MCU_ON_MASK 0x1#define IRQ1_MCU_ON_MASK_SFT BIT(1)#define IRQ0_MCU_ON_SFT 0#define IRQ0_MCU_ON_MASK 0x1#define IRQ0_MCU_ON_MASK_SFT BIT(0)/* AFE_IRQ_MCU_CON1 */ #define IRQ7_MCU_MODE_SFT 28#define IRQ7_MCU_MODE_MASK 0xf#define IRQ7_MCU_MODE_MASK_SFT GENMASK(31, 28)#define IRQ6_MCU_MODE_SFT 24#define IRQ6_MCU_MODE_MASK 0xf#define IRQ6_MCU_MODE_MASK_SFT GENMASK(27, 24)#define IRQ5_MCU_MODE_SFT 20#define IRQ5_MCU_MODE_MASK 0xf#define IRQ5_MCU_MODE_MASK_SFT GENMASK(23, 20)#define IRQ4_MCU_MODE_SFT 16#define IRQ4_MCU_MODE_MASK 0xf#define IRQ4_MCU_MODE_MASK_SFT GENMASK(19, 16)#define IRQ3_MCU_MODE_SFT 12#define IRQ3_MCU_MODE_MASK 0xf#define IRQ3_MCU_MODE_MASK_SFT GENMASK(15, 12)#define IRQ2_MCU_MODE_SFT 8#define IRQ2_MCU_MODE_MASK 0xf#define IRQ2_MCU_MODE_MASK_SFT GENMASK(11, 8)#define IRQ1_MCU_MODE_SFT 4#define IRQ1_MCU_MODE_MASK 0xf#define IRQ1_MCU_MODE_MASK_SFT GENMASK(7, 4)#define IRQ0_MCU_MODE_SFT 0#define IRQ0_MCU_MODE_MASK 0xf#define IRQ0_MCU_MODE_MASK_SFT GENMASK(3, 0)/* AFE_IRQ_MCU_CON2 */ #define IRQ15_MCU_MODE_SFT 28#define IRQ15_MCU_MODE_MASK 0xf#define IRQ15_MCU_MODE_MASK_SFT GENMASK(31, 28)#define IRQ14_MCU_MODE_SFT 24#define IRQ14_MCU_MODE_MASK 0xf#define IRQ14_MCU_MODE_MASK_SFT GENMASK(27, 24)#define IRQ13_MCU_MODE_SFT 20#define IRQ13_MCU_MODE_MASK 0xf#define IRQ13_MCU_MODE_MASK_SFT GENMASK(23, 20)#define IRQ12_MCU_MODE_SFT 16#define IRQ12_MCU_MODE_MASK 0xf#define IRQ12_MCU_MODE_MASK_SFT GENMASK(19, 16)#define IRQ11_MCU_MODE_SFT 12#define IRQ11_MCU_MODE_MASK 0xf#define IRQ11_MCU_MODE_MASK_SFT GENMASK(15, 12)#define IRQ10_MCU_MODE_SFT 8#define IRQ10_MCU_MODE_MASK 0xf#define IRQ10_MCU_MODE_MASK_SFT GENMASK(11, 8)#define IRQ9_MCU_MODE_SFT 4#define IRQ9_MCU_MODE_MASK 0xf#define IRQ9_MCU_MODE_MASK_SFT GENMASK(7, 4)#define IRQ8_MCU_MODE_SFT 0#define IRQ8_MCU_MODE_MASK 0xf#define IRQ8_MCU_MODE_MASK_SFT GENMASK(3, 0)/* AFE_IRQ_MCU_CON3 */ #define IRQ23_MCU_MODE_SFT 28#define IRQ23_MCU_MODE_MASK 0xf#define IRQ23_MCU_MODE_MASK_SFT GENMASK(31, 28)#define IRQ22_MCU_MODE_SFT 24#define IRQ22_MCU_MODE_MASK 0xf#define IRQ22_MCU_MODE_MASK_SFT GENMASK(27, 24)#define IRQ21_MCU_MODE_SFT 20#define IRQ21_MCU_MODE_MASK 0xf#define IRQ21_MCU_MODE_MASK_SFT GENMASK(23, 20)#define IRQ20_MCU_MODE_SFT 16#define IRQ20_MCU_MODE_MASK 0xf#define IRQ20_MCU_MODE_MASK_SFT GENMASK(19, 16)#define IRQ19_MCU_MODE_SFT 12#define IRQ19_MCU_MODE_MASK 0xf#define IRQ19_MCU_MODE_MASK_SFT GENMASK(15, 12)#define IRQ18_MCU_MODE_SFT 8#define IRQ18_MCU_MODE_MASK 0xf#define IRQ18_MCU_MODE_MASK_SFT GENMASK(11, 8)#define IRQ17_MCU_MODE_SFT 4#define IRQ17_MCU_MODE_MASK 0xf#define IRQ17_MCU_MODE_MASK_SFT GENMASK(7, 4)#define IRQ16_MCU_MODE_SFT 0#define IRQ16_MCU_MODE_MASK 0xf#define IRQ16_MCU_MODE_MASK_SFT GENMASK(3, 0)/* AFE_IRQ_MCU_CON4 */ #define IRQ26_MCU_MODE_SFT 8#define IRQ26_MCU_MODE_MASK 0xf#define IRQ26_MCU_MODE_MASK_SFT GENMASK(11, 8)#define IRQ25_MCU_MODE_SFT 4#define IRQ25_MCU_MODE_MASK 0xf#define IRQ25_MCU_MODE_MASK_SFT GENMASK(7, 4)#define IRQ24_MCU_MODE_SFT 0#define IRQ24_MCU_MODE_MASK 0xf#define IRQ24_MCU_MODE_MASK_SFT GENMASK(3, 0)/* AFE_IRQ_MCU_CLR */ #define IRQ31_MCU_CLR_SFT 31#define IRQ31_MCU_CLR_MASK_SFT BIT(31)#define IRQ26_MCU_CLR_SFT 26#define IRQ26_MCU_CLR_MASK_SFT BIT(26)#define IRQ25_MCU_CLR_SFT 25#define IRQ25_MCU_CLR_MASK_SFT BIT(25)#define IRQ24_MCU_CLR_SFT 24#define IRQ24_MCU_CLR_MASK_SFT BIT(24)#define IRQ23_MCU_CLR_SFT 23#define IRQ23_MCU_CLR_MASK_SFT BIT(23)#define IRQ22_MCU_CLR_SFT 22#define IRQ22_MCU_CLR_MASK_SFT BIT(22)#define IRQ21_MCU_CLR_SFT 21#define IRQ21_MCU_CLR_MASK_SFT BIT(21)#define IRQ20_MCU_CLR_SFT 20#define IRQ20_MCU_CLR_MASK_SFT BIT(20)#define IRQ19_MCU_CLR_SFT 19#define IRQ19_MCU_CLR_MASK_SFT BIT(19)#define IRQ18_MCU_CLR_SFT 18#define IRQ18_MCU_CLR_MASK_SFT BIT(18)#define IRQ17_MCU_CLR_SFT 17#define IRQ17_MCU_CLR_MASK_SFT BIT(17)#define IRQ16_MCU_CLR_SFT 16#define IRQ16_MCU_CLR_MASK_SFT BIT(16)#define IRQ15_MCU_CLR_SFT 15#define IRQ15_MCU_CLR_MASK_SFT BIT(15)#define IRQ14_MCU_CLR_SFT 14#define IRQ14_MCU_CLR_MASK_SFT BIT(14)#define IRQ13_MCU_CLR_SFT 13#define IRQ13_MCU_CLR_MASK_SFT BIT(13)#define IRQ12_MCU_CLR_SFT 12#define IRQ12_MCU_CLR_MASK_SFT BIT(12)#define IRQ11_MCU_CLR_SFT 11#define IRQ11_MCU_CLR_MASK_SFT BIT(11)#define IRQ10_MCU_CLR_SFT 10#define IRQ10_MCU_CLR_MASK_SFT BIT(10)#define IRQ9_MCU_CLR_SFT 9#define IRQ9_MCU_CLR_MASK_SFT BIT(9)#define IRQ8_MCU_CLR_SFT 8#define IRQ8_MCU_CLR_MASK_SFT BIT(8)#define IRQ7_MCU_CLR_SFT 7#define IRQ7_MCU_CLR_MASK_SFT BIT(7)#define IRQ6_MCU_CLR_SFT 6#define IRQ6_MCU_CLR_MASK_SFT BIT(6)#define IRQ5_MCU_CLR_SFT 5#define IRQ5_MCU_CLR_MASK_SFT BIT(5)#define IRQ4_MCU_CLR_SFT 4#define IRQ4_MCU_CLR_MASK_SFT BIT(4)#define IRQ3_MCU_CLR_SFT 3#define IRQ3_MCU_CLR_MASK_SFT BIT(3)#define IRQ2_MCU_CLR_SFT 2#define IRQ2_MCU_CLR_MASK_SFT BIT(2)#define IRQ1_MCU_CLR_SFT 1#define IRQ1_MCU_CLR_MASK_SFT BIT(1)#define IRQ0_MCU_CLR_SFT 0#define IRQ0_MCU_CLR_MASK_SFT BIT(0)/* AFE_IRQ_MCU_EN */ #define IRQ31_MCU_EN_SFT 31#define IRQ30_MCU_EN_SFT 30#define IRQ29_MCU_EN_SFT 29#define IRQ28_MCU_EN_SFT 28#define IRQ27_MCU_EN_SFT 27#define IRQ26_MCU_EN_SFT 26#define IRQ25_MCU_EN_SFT 25#define IRQ24_MCU_EN_SFT 24#define IRQ23_MCU_EN_SFT 23#define IRQ22_MCU_EN_SFT 22#define IRQ21_MCU_EN_SFT 21#define IRQ20_MCU_EN_SFT 20#define IRQ19_MCU_EN_SFT 19#define IRQ18_MCU_EN_SFT 18#define IRQ17_MCU_EN_SFT 17#define IRQ16_MCU_EN_SFT 16#define IRQ15_MCU_EN_SFT 15#define IRQ14_MCU_EN_SFT 14#define IRQ13_MCU_EN_SFT 13#define IRQ12_MCU_EN_SFT 12#define IRQ11_MCU_EN_SFT 11#define IRQ10_MCU_EN_SFT 10#define IRQ9_MCU_EN_SFT 9#define IRQ8_MCU_EN_SFT 8#define IRQ7_MCU_EN_SFT 7#define IRQ6_MCU_EN_SFT 6#define IRQ5_MCU_EN_SFT 5#define IRQ4_MCU_EN_SFT 4#define IRQ3_MCU_EN_SFT 3#define IRQ2_MCU_EN_SFT 2#define IRQ1_MCU_EN_SFT 1#define IRQ0_MCU_EN_SFT 0/* AFE_IRQ_MCU_SCP_EN */ #define IRQ31_MCU_SCP_EN_SFT 31#define IRQ30_MCU_SCP_EN_SFT 30#define IRQ29_MCU_SCP_EN_SFT 29#define IRQ28_MCU_SCP_EN_SFT 28#define IRQ27_MCU_SCP_EN_SFT 27#define IRQ26_MCU_SCP_EN_SFT 26#define IRQ25_MCU_SCP_EN_SFT 25#define IRQ24_MCU_SCP_EN_SFT 24#define IRQ23_MCU_SCP_EN_SFT 23#define IRQ22_MCU_SCP_EN_SFT 22#define IRQ21_MCU_SCP_EN_SFT 21#define IRQ20_MCU_SCP_EN_SFT 20#define IRQ19_MCU_SCP_EN_SFT 19#define IRQ18_MCU_SCP_EN_SFT 18#define IRQ17_MCU_SCP_EN_SFT 17#define IRQ16_MCU_SCP_EN_SFT 16#define IRQ15_MCU_SCP_EN_SFT 15#define IRQ14_MCU_SCP_EN_SFT 14#define IRQ13_MCU_SCP_EN_SFT 13#define IRQ12_MCU_SCP_EN_SFT 12#define IRQ11_MCU_SCP_EN_SFT 11#define IRQ10_MCU_SCP_EN_SFT 10#define IRQ9_MCU_SCP_EN_SFT 9#define IRQ8_MCU_SCP_EN_SFT 8#define IRQ7_MCU_SCP_EN_SFT 7#define IRQ6_MCU_SCP_EN_SFT 6#define IRQ5_MCU_SCP_EN_SFT 5#define IRQ4_MCU_SCP_EN_SFT 4#define IRQ3_MCU_SCP_EN_SFT 3#define IRQ2_MCU_SCP_EN_SFT 2#define IRQ1_MCU_SCP_EN_SFT 1#define IRQ0_MCU_SCP_EN_SFT 0/* AFE_IRQ_MCU_DSP_EN */ #define IRQ31_MCU_DSP_EN_SFT 31#define IRQ30_MCU_DSP_EN_SFT 30#define IRQ29_MCU_DSP_EN_SFT 29#define IRQ28_MCU_DSP_EN_SFT 28#define IRQ27_MCU_DSP_EN_SFT 27#define IRQ26_MCU_DSP_EN_SFT 26#define IRQ25_MCU_DSP_EN_SFT 25#define IRQ24_MCU_DSP_EN_SFT 24#define IRQ23_MCU_DSP_EN_SFT 23#define IRQ22_MCU_DSP_EN_SFT 22#define IRQ21_MCU_DSP_EN_SFT 21#define IRQ20_MCU_DSP_EN_SFT 20#define IRQ19_MCU_DSP_EN_SFT 19#define IRQ18_MCU_DSP_EN_SFT 18#define IRQ17_MCU_DSP_EN_SFT 17#define IRQ16_MCU_DSP_EN_SFT 16#define IRQ15_MCU_DSP_EN_SFT 15#define IRQ14_MCU_DSP_EN_SFT 14#define IRQ13_MCU_DSP_EN_SFT 13#define IRQ12_MCU_DSP_EN_SFT 12#define IRQ11_MCU_DSP_EN_SFT 11#define IRQ10_MCU_DSP_EN_SFT 10#define IRQ9_MCU_DSP_EN_SFT 9#define IRQ8_MCU_DSP_EN_SFT 8#define IRQ7_MCU_DSP_EN_SFT 7#define IRQ6_MCU_DSP_EN_SFT 6#define IRQ5_MCU_DSP_EN_SFT 5#define IRQ4_MCU_DSP_EN_SFT 4#define IRQ3_MCU_DSP_EN_SFT 3#define IRQ2_MCU_DSP_EN_SFT 2#define IRQ1_MCU_DSP_EN_SFT 1#define IRQ0_MCU_DSP_EN_SFT 0/* AFE_AUD_PAD_TOP */ #define AUD_PAD_TOP_MON_SFT 15#define AUD_PAD_TOP_MON_MASK_SFT GENMASK(31, 15)#define AUD_PAD_TOP_FIFO_RSP_SFT 4#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT GENMASK(7, 4)#define RG_RX_PROTOCOL2_SFT 3#define RG_RX_PROTOCOL2_MASK_SFT BIT(3)#define RESERVDED_01_SFT 1#define RESERVDED_01_MASK_SFT GENMASK(2, 1)#define RG_RX_FIFO_ON_SFT 0#define RG_RX_FIFO_ON_MASK_SFT BIT(0)/* AFE_ADDA_MTKAIF_SYNCWORD_CFG */ #define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT 23#define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK_SFT BIT(23)/* AFE_ADDA_MTKAIF_RX_CFG0 */ #define MTKAIF_RXIF_VOICE_MODE_SFT 20#define MTKAIF_RXIF_VOICE_MODE_MASK_SFT GENMASK(23, 20)#define MTKAIF_RXIF_DETECT_ON_SFT 16#define MTKAIF_RXIF_DETECT_ON_MASK_SFT BIT(16)#define MTKAIF_RXIF_DATA_BIT_SFT 8#define MTKAIF_RXIF_DATA_BIT_MASK_SFT GENMASK(10, 8)#define MTKAIF_RXIF_FIFO_RSP_SFT 4#define MTKAIF_RXIF_FIFO_RSP_MASK_SFT GENMASK(6, 4)#define MTKAIF_RXIF_DATA_MODE_SFT 0#define MTKAIF_RXIF_DATA_MODE_MASK_SFT BIT(0)/* GENERAL_ASRC_MODE */ #define GENERAL2_ASRCOUT_MODE_SFT 12#define GENERAL2_ASRCOUT_MODE_MASK 0xf#define GENERAL2_ASRCOUT_MODE_MASK_SFT GENMASK(15, 12)#define GENERAL2_ASRCIN_MODE_SFT 8#define GENERAL2_ASRCIN_MODE_MASK 0xf#define GENERAL2_ASRCIN_MODE_MASK_SFT GENMASK(11, 8)#define GENERAL1_ASRCOUT_MODE_SFT 4#define GENERAL1_ASRCOUT_MODE_MASK 0xf#define GENERAL1_ASRCOUT_MODE_MASK_SFT GENMASK(7, 4)#define GENERAL1_ASRCIN_MODE_SFT 0#define GENERAL1_ASRCIN_MODE_MASK 0xf#define GENERAL1_ASRCIN_MODE_MASK_SFT GENMASK(3, 0)/* GENERAL_ASRC_EN_ON */ #define GENERAL2_ASRC_EN_ON_SFT 1#define GENERAL2_ASRC_EN_ON_MASK_SFT BIT(1)#define GENERAL1_ASRC_EN_ON_SFT 0#define GENERAL1_ASRC_EN_ON_MASK_SFT BIT(0)/* AFE_GENERAL1_ASRC_2CH_CON0 */ #define G_SRC_CHSET_STR_CLR_SFT 4#define G_SRC_CHSET_STR_CLR_MASK_SFT BIT(4)#define G_SRC_CHSET_ON_SFT 2#define G_SRC_CHSET_ON_MASK_SFT BIT(2)#define G_SRC_COEFF_SRAM_CTRL_SFT 1#define G_SRC_COEFF_SRAM_CTRL_MASK_SFT BIT(1)#define G_SRC_ASM_ON_SFT 0#define G_SRC_ASM_ON_MASK_SFT BIT(0)/* AFE_GENERAL1_ASRC_2CH_CON3 */ #define G_SRC_ASM_FREQ_4_SFT 0#define G_SRC_ASM_FREQ_4_MASK_SFT GENMASK(23, 0)/* AFE_GENERAL1_ASRC_2CH_CON4 */ #define G_SRC_ASM_FREQ_5_SFT 0#define G_SRC_ASM_FREQ_5_MASK_SFT GENMASK(23, 0)/* AFE_GENERAL1_ASRC_2CH_CON13 */ #define G_SRC_COEFF_SRAM_ADR_SFT 0#define G_SRC_COEFF_SRAM_ADR_MASK_SFT GENMASK(5, 0)/* AFE_GENERAL1_ASRC_2CH_CON2 */ #define G_SRC_CHSET_O16BIT_SFT 19#define G_SRC_CHSET_O16BIT_MASK_SFT BIT(19)#define G_SRC_CHSET_CLR_IIR_HISTORY_SFT 17#define G_SRC_CHSET_CLR_IIR_HISTORY_MASK_SFT BIT(17)#define G_SRC_CHSET_IS_MONO_SFT 16#define G_SRC_CHSET_IS_MONO_MASK_SFT BIT(16)#define G_SRC_CHSET_IIR_EN_SFT 11#define G_SRC_CHSET_IIR_EN_MASK_SFT BIT(11)#define G_SRC_CHSET_IIR_STAGE_SFT 8#define G_SRC_CHSET_IIR_STAGE_MASK_SFT GENMASK(10, 8)#define G_SRC_CHSET_STR_CLR_RU_SFT 5#define G_SRC_CHSET_STR_CLR_RU_MASK_SFT BIT(5)#define G_SRC_CHSET_ON_SFT 2#define G_SRC_CHSET_ON_MASK_SFT BIT(2)#define G_SRC_COEFF_SRAM_CTRL_SFT 1#define G_SRC_COEFF_SRAM_CTRL_MASK_SFT BIT(1)#define G_SRC_ASM_ON_SFT 0#define G_SRC_ASM_ON_MASK_SFT BIT(0)/* AFE_ADDA_DL_SDM_DITHER_CON */ #define AFE_DL_SDM_DITHER_64TAP_EN_SFT 20#define AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT BIT(20)#define AFE_DL_SDM_DITHER_EN_SFT 16#define AFE_DL_SDM_DITHER_EN_MASK_SFT BIT(16)#define AFE_DL_SDM_DITHER_GAIN_SFT 0#define AFE_DL_SDM_DITHER_GAIN_MASK_SFT GENMASK(7, 0)/* AFE_ADDA_DL_SDM_AUTO_RESET_CON */ #define SDM_AUTO_RESET_TEST_ON_SFT 31#define SDM_AUTO_RESET_TEST_ON_MASK_SFT BIT(31)#define AFE_DL_USE_NEW_2ND_SDM_SFT 28#define AFE_DL_USE_NEW_2ND_SDM_MASK_SFT BIT(28)#define SDM_AUTO_RESET_COUNT_TH_SFT 0#define SDM_AUTO_RESET_COUNT_TH_MASK_SFT GENMASK(23, 0)/* AFE_ASRC_2CH_CON0 */ #define CON0_CHSET_STR_CLR_SFT 4#define CON0_CHSET_STR_CLR_MASK_SFT BIT(4)#define CON0_ASM_ON_SFT 0#define CON0_ASM_ON_MASK_SFT BIT(0)/* AFE_ASRC_2CH_CON5 */ #define CALI_EN_SFT 0#define CALI_EN_MASK_SFT BIT(0)/* FPGA_CFG4 */ #define IRQ_COUNTER_SFT 3#define IRQ_COUNTER_MASK_SFT GENMASK(31, 3)#define IRQ_CLK_COUNTER_CLEAN_SFT 2#define IRQ_CLK_COUNTER_CLEAN_MASK_SFT BIT(2)#define IRQ_CLK_COUNTER_PAUSE_SFT 1#define IRQ_CLK_COUNTER_PAUSE_MASK_SFT BIT(1)#define IRQ_CLK_COUNTER_ON_SFT 0#define IRQ_CLK_COUNTER_ON_MASK_SFT BIT(0)/* FPGA_CFG5 */ #define WR_MSTR_ON_SFT 16#define WR_MSTR_ON_MASK_SFT GENMASK(28, 16)#define WR_AG_SEL_SFT 0#define WR_AG_SEL_MASK_SFT GENMASK(12, 0)/* FPGA_CFG6 */ #define WR_MSTR_REQ_REAL_SFT 16#define WR_MSTR_REQ_REAL_MASK_SFT GENMASK(28, 16)#define WR_MSTR_REQ_IN_SFT 0#define WR_MSTR_REQ_IN_MASK_SFT GENMASK(12, 0)/* FPGA_CFG7 */ #define MEM1_WDATA_MON0_SFT 0#define MEM1_WDATA_MON0_MASK_SFT GENMASK(31, 0)/* FPGA_CFG8 */ #define MEM1_WDATA_MON1_SFT 0#define MEM1_WDATA_MON1_MASK_SFT GENMASK(31, 0)/* FPGA_CFG9 */ #define MEM_WE_SFT 31#define MEM_WE_MASK_SFT BIT(31)#define AFE_HREADY_SFT 30#define AFE_HREADY_MASK_SFT BIT(30)#define MEM_WR_REQ_SFT 29#define MEM_WR_REQ_MASK_SFT BIT(29)#define WR_AG_REG_MON_SFT 16#define WR_AG_REG_MON_MASK_SFT GENMASK(28, 16)#define HCLK_CK_SFT 15#define HCLK_CK_MASK_SFT BIT(15)#define MEM_RD_REQ_SFT 14#define MEM_RD_REQ_MASK_SFT BIT(14)#define RD_AG_REQ_MON_SFT 0#define RD_AG_REQ_MON_MASK_SFT GENMASK(13, 0)/* FPGA_CFG10 */ #define MEM_BYTE_0_SFT 0#define MEM_BYTE_0_MASK_SFT GENMASK(31, 0)/* FPGA_CFG11 */ #define MEM_BYTE_1_SFT 0#define MEM_BYTE_1_MASK_SFT GENMASK(31, 0)/* FPGA_CFG12 */ #define RDATA_CNT_SFT 30#define RDATA_CNT_MASK_SFT GENMASK(31, 30)#define MS2_HREADY_SFT 29#define MS2_HREADY_MASK_SFT BIT(29)#define MS1_HREADY_SFT 28#define MS1_HREADY_MASK_SFT BIT(28)#define AG_SEL_SFT 0#define AG_SEL_MASK_SFT GENMASK(25, 0)/* FPGA_CFG13 */ #define AFE_ST_SFT 27
Messung V0.5 C=95 H=97 G=95
¤ Dauer der Verarbeitung: 0.24 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
2026-04-07
