/* SPDX-License-Identifier: GPL-2.0 */ /* * mt8192-reg.h -- Mediatek 8192 audio driver reg definition * * Copyright (c) 2020 MediaTek Inc. * Author: Shane Chien <shane.chien@mediatek.com> #ifndef _MT8192_REG_H_#define _MT8192_REG_H_/* reg bit enum */ enum {/***************************************************************************** * R E G I S T E R D E F I N I T I O N /* AUDIO_TOP_CON3 */ #define BCK_INVERSE_SFT 3#define BCK_INVERSE_MASK 0x1#define BCK_INVERSE_MASK_SFT (0x1 << 3)/* AFE_DAC_CON0 */ #define VUL12_ON_SFT 31#define VUL12_ON_MASK 0x1#define VUL12_ON_MASK_SFT (0x1 << 31)#define MOD_DAI_ON_SFT 30#define MOD_DAI_ON_MASK 0x1#define MOD_DAI_ON_MASK_SFT (0x1 << 30)#define DAI_ON_SFT 29#define DAI_ON_MASK 0x1#define DAI_ON_MASK_SFT (0x1 << 29)#define DAI2_ON_SFT 28#define DAI2_ON_MASK 0x1#define DAI2_ON_MASK_SFT (0x1 << 28)#define VUL6_ON_SFT 23#define VUL6_ON_MASK 0x1#define VUL6_ON_MASK_SFT (0x1 << 23)#define VUL5_ON_SFT 22#define VUL5_ON_MASK 0x1#define VUL5_ON_MASK_SFT (0x1 << 22)#define VUL4_ON_SFT 21#define VUL4_ON_MASK 0x1#define VUL4_ON_MASK_SFT (0x1 << 21)#define VUL3_ON_SFT 20#define VUL3_ON_MASK 0x1#define VUL3_ON_MASK_SFT (0x1 << 20)#define VUL2_ON_SFT 19#define VUL2_ON_MASK 0x1#define VUL2_ON_MASK_SFT (0x1 << 19)#define VUL_ON_SFT 18#define VUL_ON_MASK 0x1#define VUL_ON_MASK_SFT (0x1 << 18)#define AWB2_ON_SFT 17#define AWB2_ON_MASK 0x1#define AWB2_ON_MASK_SFT (0x1 << 17)#define AWB_ON_SFT 16#define AWB_ON_MASK 0x1#define AWB_ON_MASK_SFT (0x1 << 16)#define DL12_ON_SFT 15#define DL12_ON_MASK 0x1#define DL12_ON_MASK_SFT (0x1 << 15)#define DL9_ON_SFT 12#define DL9_ON_MASK 0x1#define DL9_ON_MASK_SFT (0x1 << 12)#define DL8_ON_SFT 11#define DL8_ON_MASK 0x1#define DL8_ON_MASK_SFT (0x1 << 11)#define DL7_ON_SFT 10#define DL7_ON_MASK 0x1#define DL7_ON_MASK_SFT (0x1 << 10)#define DL6_ON_SFT 9#define DL6_ON_MASK 0x1#define DL6_ON_MASK_SFT (0x1 << 9)#define DL5_ON_SFT 8#define DL5_ON_MASK 0x1#define DL5_ON_MASK_SFT (0x1 << 8)#define DL4_ON_SFT 7#define DL4_ON_MASK 0x1#define DL4_ON_MASK_SFT (0x1 << 7)#define DL3_ON_SFT 6#define DL3_ON_MASK 0x1#define DL3_ON_MASK_SFT (0x1 << 6)#define DL2_ON_SFT 5#define DL2_ON_MASK 0x1#define DL2_ON_MASK_SFT (0x1 << 5)#define DL1_ON_SFT 4#define DL1_ON_MASK 0x1#define DL1_ON_MASK_SFT (0x1 << 4)#define HDMI_OUT_ON_SFT 1#define HDMI_OUT_ON_MASK 0x1#define HDMI_OUT_ON_MASK_SFT (0x1 << 1)#define AFE_ON_SFT 0#define AFE_ON_MASK 0x1#define AFE_ON_MASK_SFT (0x1 << 0)/* AFE_DAC_MON */ #define AFE_ON_RETM_SFT 0#define AFE_ON_RETM_MASK 0x1#define AFE_ON_RETM_MASK_SFT (0x1 << 0)/* AFE_I2S_CON */ #define BCK_NEG_EG_LATCH_SFT 30#define BCK_NEG_EG_LATCH_MASK 0x1#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)#define BCK_INV_SFT 29#define BCK_INV_MASK 0x1#define BCK_INV_MASK_SFT (0x1 << 29)#define I2SIN_PAD_SEL_SFT 28#define I2SIN_PAD_SEL_MASK 0x1#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)#define I2S_LOOPBACK_SFT 20#define I2S_LOOPBACK_MASK 0x1#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S1_HD_EN_SFT 12#define I2S1_HD_EN_MASK 0x1#define I2S1_HD_EN_MASK_SFT (0x1 << 12)#define I2S_OUT_MODE_SFT 8#define I2S_OUT_MODE_MASK 0xf#define I2S_OUT_MODE_MASK_SFT (0xf << 8)#define INV_PAD_CTRL_SFT 7#define INV_PAD_CTRL_MASK 0x1#define INV_PAD_CTRL_MASK_SFT (0x1 << 7)#define I2S_BYPSRC_SFT 6#define I2S_BYPSRC_MASK 0x1#define I2S_BYPSRC_MASK_SFT (0x1 << 6)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S_FMT_SFT 3#define I2S_FMT_MASK 0x1#define I2S_FMT_MASK_SFT (0x1 << 3)#define I2S_SRC_SFT 2#define I2S_SRC_MASK 0x1#define I2S_SRC_MASK_SFT (0x1 << 2)#define I2S_WLEN_SFT 1#define I2S_WLEN_MASK 0x1#define I2S_WLEN_MASK_SFT (0x1 << 1)#define I2S_EN_SFT 0#define I2S_EN_MASK 0x1#define I2S_EN_MASK_SFT (0x1 << 0)/* AFE_I2S_CON1 */ #define I2S2_LR_SWAP_SFT 31#define I2S2_LR_SWAP_MASK 0x1#define I2S2_LR_SWAP_MASK_SFT (0x1 << 31)#define I2S2_SEL_O19_O20_SFT 18#define I2S2_SEL_O19_O20_MASK 0x1#define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S2_SEL_O03_O04_SFT 16#define I2S2_SEL_O03_O04_MASK 0x1#define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16)#define I2S2_32BIT_EN_SFT 13#define I2S2_32BIT_EN_MASK 0x1#define I2S2_32BIT_EN_MASK_SFT (0x1 << 13)#define I2S2_HD_EN_SFT 12#define I2S2_HD_EN_MASK 0x1#define I2S2_HD_EN_MASK_SFT (0x1 << 12)#define I2S2_OUT_MODE_SFT 8#define I2S2_OUT_MODE_MASK 0xf#define I2S2_OUT_MODE_MASK_SFT (0xf << 8)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S2_FMT_SFT 3#define I2S2_FMT_MASK 0x1#define I2S2_FMT_MASK_SFT (0x1 << 3)#define I2S2_WLEN_SFT 1#define I2S2_WLEN_MASK 0x1#define I2S2_WLEN_MASK_SFT (0x1 << 1)#define I2S2_EN_SFT 0#define I2S2_EN_MASK 0x1#define I2S2_EN_MASK_SFT (0x1 << 0)/* AFE_I2S_CON2 */ #define I2S3_LR_SWAP_SFT 31#define I2S3_LR_SWAP_MASK 0x1#define I2S3_LR_SWAP_MASK_SFT (0x1 << 31)#define I2S3_UPDATE_WORD_SFT 24#define I2S3_UPDATE_WORD_MASK 0x1f#define I2S3_UPDATE_WORD_MASK_SFT (0x1f << 24)#define I2S3_BCK_INV_SFT 23#define I2S3_BCK_INV_MASK 0x1#define I2S3_BCK_INV_MASK_SFT (0x1 << 23)#define I2S3_FPGA_BIT_TEST_SFT 22#define I2S3_FPGA_BIT_TEST_MASK 0x1#define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22)#define I2S3_FPGA_BIT_SFT 21#define I2S3_FPGA_BIT_MASK 0x1#define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21)#define I2S3_LOOPBACK_SFT 20#define I2S3_LOOPBACK_MASK 0x1#define I2S3_LOOPBACK_MASK_SFT (0x1 << 20)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S3_HD_EN_SFT 12#define I2S3_HD_EN_MASK 0x1#define I2S3_HD_EN_MASK_SFT (0x1 << 12)#define I2S3_OUT_MODE_SFT 8#define I2S3_OUT_MODE_MASK 0xf#define I2S3_OUT_MODE_MASK_SFT (0xf << 8)#define I2S3_FMT_SFT 3#define I2S3_FMT_MASK 0x1#define I2S3_FMT_MASK_SFT (0x1 << 3)#define I2S3_WLEN_SFT 1#define I2S3_WLEN_MASK 0x1#define I2S3_WLEN_MASK_SFT (0x1 << 1)#define I2S3_EN_SFT 0#define I2S3_EN_MASK 0x1#define I2S3_EN_MASK_SFT (0x1 << 0)/* AFE_I2S_CON3 */ #define I2S4_LR_SWAP_SFT 31#define I2S4_LR_SWAP_MASK 0x1#define I2S4_LR_SWAP_MASK_SFT (0x1 << 31)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S4_32BIT_EN_SFT 13#define I2S4_32BIT_EN_MASK 0x1#define I2S4_32BIT_EN_MASK_SFT (0x1 << 13)#define I2S4_HD_EN_SFT 12#define I2S4_HD_EN_MASK 0x1#define I2S4_HD_EN_MASK_SFT (0x1 << 12)#define I2S4_OUT_MODE_SFT 8#define I2S4_OUT_MODE_MASK 0xf#define I2S4_OUT_MODE_MASK_SFT (0xf << 8)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S4_FMT_SFT 3#define I2S4_FMT_MASK 0x1#define I2S4_FMT_MASK_SFT (0x1 << 3)#define I2S4_WLEN_SFT 1#define I2S4_WLEN_MASK 0x1#define I2S4_WLEN_MASK_SFT (0x1 << 1)#define I2S4_EN_SFT 0#define I2S4_EN_MASK 0x1#define I2S4_EN_MASK_SFT (0x1 << 0)/* AFE_I2S_CON4 */ #define I2S5_LR_SWAP_SFT 31#define I2S5_LR_SWAP_MASK 0x1#define I2S5_LR_SWAP_MASK_SFT (0x1 << 31)#define I2S_LOOPBACK_SFT 20#define I2S_LOOPBACK_MASK 0x1#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S5_32BIT_EN_SFT 13#define I2S5_32BIT_EN_MASK 0x1#define I2S5_32BIT_EN_MASK_SFT (0x1 << 13)#define I2S5_HD_EN_SFT 12#define I2S5_HD_EN_MASK 0x1#define I2S5_HD_EN_MASK_SFT (0x1 << 12)#define I2S5_OUT_MODE_SFT 8#define I2S5_OUT_MODE_MASK 0xf#define I2S5_OUT_MODE_MASK_SFT (0xf << 8)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S5_FMT_SFT 3#define I2S5_FMT_MASK 0x1#define I2S5_FMT_MASK_SFT (0x1 << 3)#define I2S5_WLEN_SFT 1#define I2S5_WLEN_MASK 0x1#define I2S5_WLEN_MASK_SFT (0x1 << 1)#define I2S5_EN_SFT 0#define I2S5_EN_MASK 0x1#define I2S5_EN_MASK_SFT (0x1 << 0)/* AFE_CONNSYS_I2S_CON */ #define BCK_NEG_EG_LATCH_SFT 30#define BCK_NEG_EG_LATCH_MASK 0x1#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)#define BCK_INV_SFT 29#define BCK_INV_MASK 0x1#define BCK_INV_MASK_SFT (0x1 << 29)#define I2SIN_PAD_SEL_SFT 28#define I2SIN_PAD_SEL_MASK 0x1#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)#define I2S_LOOPBACK_SFT 20#define I2S_LOOPBACK_MASK 0x1#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S_MODE_SFT 8#define I2S_MODE_MASK 0xf#define I2S_MODE_MASK_SFT (0xf << 8)#define INV_PAD_CTRL_SFT 7#define INV_PAD_CTRL_MASK 0x1#define INV_PAD_CTRL_MASK_SFT (0x1 << 7)#define I2S_BYPSRC_SFT 6#define I2S_BYPSRC_MASK 0x1#define I2S_BYPSRC_MASK_SFT (0x1 << 6)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S_FMT_SFT 3#define I2S_FMT_MASK 0x1#define I2S_FMT_MASK_SFT (0x1 << 3)#define I2S_SRC_SFT 2#define I2S_SRC_MASK 0x1#define I2S_SRC_MASK_SFT (0x1 << 2)#define I2S_WLEN_SFT 1#define I2S_WLEN_MASK 0x1#define I2S_WLEN_MASK_SFT (0x1 << 1)#define I2S_EN_SFT 0#define I2S_EN_MASK 0x1#define I2S_EN_MASK_SFT (0x1 << 0)/* AFE_I2S_CON6 */ #define BCK_NEG_EG_LATCH_SFT 30#define BCK_NEG_EG_LATCH_MASK 0x1#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)#define BCK_INV_SFT 29#define BCK_INV_MASK 0x1#define BCK_INV_MASK_SFT (0x1 << 29)#define I2S6_LOOPBACK_SFT 20#define I2S6_LOOPBACK_MASK 0x1#define I2S6_LOOPBACK_MASK_SFT (0x1 << 20)#define I2S6_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S6_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S6_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S6_HD_EN_SFT 12#define I2S6_HD_EN_MASK 0x1#define I2S6_HD_EN_MASK_SFT (0x1 << 12)#define I2S6_OUT_MODE_SFT 8#define I2S6_OUT_MODE_MASK 0xf#define I2S6_OUT_MODE_MASK_SFT (0xf << 8)#define I2S6_BYPSRC_SFT 6#define I2S6_BYPSRC_MASK 0x1#define I2S6_BYPSRC_MASK_SFT (0x1 << 6)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S6_FMT_SFT 3#define I2S6_FMT_MASK 0x1#define I2S6_FMT_MASK_SFT (0x1 << 3)#define I2S6_SRC_SFT 2#define I2S6_SRC_MASK 0x1#define I2S6_SRC_MASK_SFT (0x1 << 2)#define I2S6_WLEN_SFT 1#define I2S6_WLEN_MASK 0x1#define I2S6_WLEN_MASK_SFT (0x1 << 1)#define I2S6_EN_SFT 0#define I2S6_EN_MASK 0x1#define I2S6_EN_MASK_SFT (0x1 << 0)/* AFE_I2S_CON7 */ #define I2S7_LR_SWAP_SFT 31#define I2S7_LR_SWAP_MASK 0x1#define I2S7_LR_SWAP_MASK_SFT (0x1 << 31)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S7_32BIT_EN_SFT 13#define I2S7_32BIT_EN_MASK 0x1#define I2S7_32BIT_EN_MASK_SFT (0x1 << 13)#define I2S7_HD_EN_SFT 12#define I2S7_HD_EN_MASK 0x1#define I2S7_HD_EN_MASK_SFT (0x1 << 12)#define I2S7_OUT_MODE_SFT 8#define I2S7_OUT_MODE_MASK 0xf#define I2S7_OUT_MODE_MASK_SFT (0xf << 8)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S7_FMT_SFT 3#define I2S7_FMT_MASK 0x1#define I2S7_FMT_MASK_SFT (0x1 << 3)#define I2S7_WLEN_SFT 1#define I2S7_WLEN_MASK 0x1#define I2S7_WLEN_MASK_SFT (0x1 << 1)#define I2S7_EN_SFT 0#define I2S7_EN_MASK 0x1#define I2S7_EN_MASK_SFT (0x1 << 0)/* AFE_I2S_CON8 */ #define BCK_NEG_EG_LATCH_SFT 30#define BCK_NEG_EG_LATCH_MASK 0x1#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)#define BCK_INV_SFT 29#define BCK_INV_MASK 0x1#define BCK_INV_MASK_SFT (0x1 << 29)#define I2S8_LOOPBACK_SFT 20#define I2S8_LOOPBACK_MASK 0x1#define I2S8_LOOPBACK_MASK_SFT (0x1 << 20)#define I2S8_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S8_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S8_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S8_HD_EN_SFT 12#define I2S8_HD_EN_MASK 0x1#define I2S8_HD_EN_MASK_SFT (0x1 << 12)#define I2S8_OUT_MODE_SFT 8#define I2S8_OUT_MODE_MASK 0xf#define I2S8_OUT_MODE_MASK_SFT (0xf << 8)#define I2S8_BYPSRC_SFT 6#define I2S8_BYPSRC_MASK 0x1#define I2S8_BYPSRC_MASK_SFT (0x1 << 6)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S8_FMT_SFT 3#define I2S8_FMT_MASK 0x1#define I2S8_FMT_MASK_SFT (0x1 << 3)#define I2S8_SRC_SFT 2#define I2S8_SRC_MASK 0x1#define I2S8_SRC_MASK_SFT (0x1 << 2)#define I2S8_WLEN_SFT 1#define I2S8_WLEN_MASK 0x1#define I2S8_WLEN_MASK_SFT (0x1 << 1)#define I2S8_EN_SFT 0#define I2S8_EN_MASK 0x1#define I2S8_EN_MASK_SFT (0x1 << 0)/* AFE_I2S_CON9 */ #define I2S9_LR_SWAP_SFT 31#define I2S9_LR_SWAP_MASK 0x1#define I2S9_LR_SWAP_MASK_SFT (0x1 << 31)#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)#define I2S9_32BIT_EN_SFT 13#define I2S9_32BIT_EN_MASK 0x1#define I2S9_32BIT_EN_MASK_SFT (0x1 << 13)#define I2S9_HD_EN_SFT 12#define I2S9_HD_EN_MASK 0x1#define I2S9_HD_EN_MASK_SFT (0x1 << 12)#define I2S9_OUT_MODE_SFT 8#define I2S9_OUT_MODE_MASK 0xf#define I2S9_OUT_MODE_MASK_SFT (0xf << 8)#define INV_LRCK_SFT 5#define INV_LRCK_MASK 0x1#define INV_LRCK_MASK_SFT (0x1 << 5)#define I2S9_FMT_SFT 3#define I2S9_FMT_MASK 0x1#define I2S9_FMT_MASK_SFT (0x1 << 3)#define I2S9_WLEN_SFT 1#define I2S9_WLEN_MASK 0x1#define I2S9_WLEN_MASK_SFT (0x1 << 1)#define I2S9_EN_SFT 0#define I2S9_EN_MASK 0x1#define I2S9_EN_MASK_SFT (0x1 << 0)/* AFE_ASRC_2CH_CON2 */ #define CHSET_O16BIT_SFT 19#define CHSET_O16BIT_MASK 0x1#define CHSET_O16BIT_MASK_SFT (0x1 << 19)#define CHSET_CLR_IIR_HISTORY_SFT 17#define CHSET_CLR_IIR_HISTORY_MASK 0x1#define CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)#define CHSET_IS_MONO_SFT 16#define CHSET_IS_MONO_MASK 0x1#define CHSET_IS_MONO_MASK_SFT (0x1 << 16)#define CHSET_IIR_EN_SFT 11#define CHSET_IIR_EN_MASK 0x1#define CHSET_IIR_EN_MASK_SFT (0x1 << 11)#define CHSET_IIR_STAGE_SFT 8#define CHSET_IIR_STAGE_MASK 0x7#define CHSET_IIR_STAGE_MASK_SFT (0x7 << 8)#define CHSET_STR_CLR_SFT 5#define CHSET_STR_CLR_MASK 0x1#define CHSET_STR_CLR_MASK_SFT (0x1 << 5)#define CHSET_ON_SFT 2#define CHSET_ON_MASK 0x1#define CHSET_ON_MASK_SFT (0x1 << 2)#define COEFF_SRAM_CTRL_SFT 1#define COEFF_SRAM_CTRL_MASK 0x1#define COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)#define ASM_ON_SFT 0#define ASM_ON_MASK 0x1#define ASM_ON_MASK_SFT (0x1 << 0)/* AFE_GAIN1_CON0 */ #define GAIN1_SAMPLE_PER_STEP_SFT 8#define GAIN1_SAMPLE_PER_STEP_MASK 0xff#define GAIN1_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)#define GAIN1_MODE_SFT 4#define GAIN1_MODE_MASK 0xf#define GAIN1_MODE_MASK_SFT (0xf << 4)#define GAIN1_ON_SFT 0#define GAIN1_ON_MASK 0x1#define GAIN1_ON_MASK_SFT (0x1 << 0)/* AFE_GAIN1_CON1 */ #define GAIN1_TARGET_SFT 0#define GAIN1_TARGET_MASK 0xfffffff#define GAIN1_TARGET_MASK_SFT (0xfffffff << 0)/* AFE_GAIN2_CON0 */ #define GAIN2_SAMPLE_PER_STEP_SFT 8#define GAIN2_SAMPLE_PER_STEP_MASK 0xff#define GAIN2_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)#define GAIN2_MODE_SFT 4#define GAIN2_MODE_MASK 0xf#define GAIN2_MODE_MASK_SFT (0xf << 4)#define GAIN2_ON_SFT 0#define GAIN2_ON_MASK 0x1#define GAIN2_ON_MASK_SFT (0x1 << 0)/* AFE_GAIN2_CON1 */ #define GAIN2_TARGET_SFT 0#define GAIN2_TARGET_MASK 0xfffffff#define GAIN2_TARGET_MASK_SFT (0xfffffff << 0)/* AFE_GAIN1_CUR */ #define AFE_GAIN1_CUR_SFT 0#define AFE_GAIN1_CUR_MASK 0xfffffff#define AFE_GAIN1_CUR_MASK_SFT (0xfffffff << 0)/* AFE_GAIN2_CUR */ #define AFE_GAIN2_CUR_SFT 0#define AFE_GAIN2_CUR_MASK 0xfffffff#define AFE_GAIN2_CUR_MASK_SFT (0xfffffff << 0)/* PCM_INTF_CON1 */ #define PCM_FIX_VALUE_SEL_SFT 31#define PCM_FIX_VALUE_SEL_MASK 0x1#define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)#define PCM_BUFFER_LOOPBACK_SFT 30#define PCM_BUFFER_LOOPBACK_MASK 0x1#define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)#define PCM_PARALLEL_LOOPBACK_SFT 29#define PCM_PARALLEL_LOOPBACK_MASK 0x1#define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)#define PCM_SERIAL_LOOPBACK_SFT 28#define PCM_SERIAL_LOOPBACK_MASK 0x1#define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)#define PCM_DAI_PCM_LOOPBACK_SFT 27#define PCM_DAI_PCM_LOOPBACK_MASK 0x1#define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)#define PCM_I2S_PCM_LOOPBACK_SFT 26#define PCM_I2S_PCM_LOOPBACK_MASK 0x1#define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)#define PCM_SYNC_DELSEL_SFT 25#define PCM_SYNC_DELSEL_MASK 0x1#define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)#define PCM_TX_LR_SWAP_SFT 24#define PCM_TX_LR_SWAP_MASK 0x1#define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)#define PCM_SYNC_OUT_INV_SFT 23#define PCM_SYNC_OUT_INV_MASK 0x1#define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)#define PCM_BCLK_OUT_INV_SFT 22#define PCM_BCLK_OUT_INV_MASK 0x1#define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)#define PCM_SYNC_IN_INV_SFT 21#define PCM_SYNC_IN_INV_MASK 0x1#define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)#define PCM_BCLK_IN_INV_SFT 20#define PCM_BCLK_IN_INV_MASK 0x1#define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)#define PCM_TX_LCH_RPT_SFT 19#define PCM_TX_LCH_RPT_MASK 0x1#define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)#define PCM_VBT_16K_MODE_SFT 18#define PCM_VBT_16K_MODE_MASK 0x1#define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)#define PCM_EXT_MODEM_SFT 17#define PCM_EXT_MODEM_MASK 0x1#define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)#define PCM_24BIT_SFT 16#define PCM_24BIT_MASK 0x1#define PCM_24BIT_MASK_SFT (0x1 << 16)#define PCM_WLEN_SFT 14#define PCM_WLEN_MASK 0x3#define PCM_WLEN_MASK_SFT (0x3 << 14)#define PCM_SYNC_LENGTH_SFT 9#define PCM_SYNC_LENGTH_MASK 0x1f#define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)#define PCM_SYNC_TYPE_SFT 8#define PCM_SYNC_TYPE_MASK 0x1#define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)#define PCM_BT_MODE_SFT 7#define PCM_BT_MODE_MASK 0x1#define PCM_BT_MODE_MASK_SFT (0x1 << 7)#define PCM_BYP_ASRC_SFT 6#define PCM_BYP_ASRC_MASK 0x1#define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)#define PCM_SLAVE_SFT 5#define PCM_SLAVE_MASK 0x1#define PCM_SLAVE_MASK_SFT (0x1 << 5)#define PCM_MODE_SFT 3#define PCM_MODE_MASK 0x3#define PCM_MODE_MASK_SFT (0x3 << 3)#define PCM_FMT_SFT 1#define PCM_FMT_MASK 0x3#define PCM_FMT_MASK_SFT (0x3 << 1)#define PCM_EN_SFT 0#define PCM_EN_MASK 0x1#define PCM_EN_MASK_SFT (0x1 << 0)/* PCM_INTF_CON2 */ #define PCM1_TX_FIFO_OV_SFT 31#define PCM1_TX_FIFO_OV_MASK 0x1#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)#define PCM1_RX_FIFO_OV_SFT 30#define PCM1_RX_FIFO_OV_MASK 0x1#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)#define PCM2_TX_FIFO_OV_SFT 29#define PCM2_TX_FIFO_OV_MASK 0x1#define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)#define PCM2_RX_FIFO_OV_SFT 28#define PCM2_RX_FIFO_OV_MASK 0x1#define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)#define PCM1_SYNC_GLITCH_SFT 27#define PCM1_SYNC_GLITCH_MASK 0x1#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)#define PCM2_SYNC_GLITCH_SFT 26#define PCM2_SYNC_GLITCH_MASK 0x1#define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)#define TX3_RCH_DBG_MODE_SFT 17#define TX3_RCH_DBG_MODE_MASK 0x1#define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)#define PCM1_PCM2_LOOPBACK_SFT 16#define PCM1_PCM2_LOOPBACK_MASK 0x1#define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16)#define DAI_PCM_LOOPBACK_CH_SFT 14#define DAI_PCM_LOOPBACK_CH_MASK 0x3#define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 14)#define I2S_PCM_LOOPBACK_CH_SFT 12#define I2S_PCM_LOOPBACK_CH_MASK 0x3#define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 12)#define TX_FIX_VALUE_SFT 0#define TX_FIX_VALUE_MASK 0xff#define TX_FIX_VALUE_MASK_SFT (0xff << 0)/* PCM2_INTF_CON */ #define PCM2_TX_FIX_VALUE_SFT 24#define PCM2_TX_FIX_VALUE_MASK 0xff#define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)#define PCM2_FIX_VALUE_SEL_SFT 23#define PCM2_FIX_VALUE_SEL_MASK 0x1#define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)#define PCM2_BUFFER_LOOPBACK_SFT 22#define PCM2_BUFFER_LOOPBACK_MASK 0x1#define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)#define PCM2_PARALLEL_LOOPBACK_SFT 21#define PCM2_PARALLEL_LOOPBACK_MASK 0x1#define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)#define PCM2_SERIAL_LOOPBACK_SFT 20#define PCM2_SERIAL_LOOPBACK_MASK 0x1#define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)#define PCM2_DAI_PCM_LOOPBACK_SFT 19#define PCM2_DAI_PCM_LOOPBACK_MASK 0x1#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)#define PCM2_I2S_PCM_LOOPBACK_SFT 18#define PCM2_I2S_PCM_LOOPBACK_MASK 0x1#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)#define PCM2_SYNC_DELSEL_SFT 17#define PCM2_SYNC_DELSEL_MASK 0x1#define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)#define PCM2_TX_LR_SWAP_SFT 16#define PCM2_TX_LR_SWAP_MASK 0x1#define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)#define PCM2_SYNC_IN_INV_SFT 15#define PCM2_SYNC_IN_INV_MASK 0x1#define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)#define PCM2_BCLK_IN_INV_SFT 14#define PCM2_BCLK_IN_INV_MASK 0x1#define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)#define PCM2_TX_LCH_RPT_SFT 13#define PCM2_TX_LCH_RPT_MASK 0x1#define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)#define PCM2_VBT_16K_MODE_SFT 12#define PCM2_VBT_16K_MODE_MASK 0x1#define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)#define PCM2_LOOPBACK_CH_SEL_SFT 10#define PCM2_LOOPBACK_CH_SEL_MASK 0x3#define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)#define PCM2_TX2_BT_MODE_SFT 8#define PCM2_TX2_BT_MODE_MASK 0x1#define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)#define PCM2_BT_MODE_SFT 7#define PCM2_BT_MODE_MASK 0x1#define PCM2_BT_MODE_MASK_SFT (0x1 << 7)#define PCM2_AFIFO_SFT 6#define PCM2_AFIFO_MASK 0x1#define PCM2_AFIFO_MASK_SFT (0x1 << 6)#define PCM2_WLEN_SFT 5#define PCM2_WLEN_MASK 0x1#define PCM2_WLEN_MASK_SFT (0x1 << 5)#define PCM2_MODE_SFT 3#define PCM2_MODE_MASK 0x3#define PCM2_MODE_MASK_SFT (0x3 << 3)#define PCM2_FMT_SFT 1#define PCM2_FMT_MASK 0x3#define PCM2_FMT_MASK_SFT (0x3 << 1)#define PCM2_EN_SFT 0#define PCM2_EN_MASK 0x1#define PCM2_EN_MASK_SFT (0x1 << 0)/* AFE_ADDA_MTKAIF_CFG0 */ #define MTKAIF_RXIF_CLKINV_ADC_SFT 31#define MTKAIF_RXIF_CLKINV_ADC_MASK 0x1#define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)#define MTKAIF_RXIF_BYPASS_SRC_SFT 17#define MTKAIF_RXIF_BYPASS_SRC_MASK 0x1#define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)#define MTKAIF_RXIF_PROTOCOL2_SFT 16#define MTKAIF_RXIF_PROTOCOL2_MASK 0x1#define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)#define MTKAIF_TXIF_BYPASS_SRC_SFT 5#define MTKAIF_TXIF_BYPASS_SRC_MASK 0x1#define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)#define MTKAIF_TXIF_PROTOCOL2_SFT 4#define MTKAIF_TXIF_PROTOCOL2_MASK 0x1#define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)#define MTKAIF_TXIF_8TO5_SFT 2#define MTKAIF_TXIF_8TO5_MASK 0x1#define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2)#define MTKAIF_RXIF_8TO5_SFT 1#define MTKAIF_RXIF_8TO5_MASK 0x1#define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1)#define MTKAIF_IF_LOOPBACK1_SFT 0#define MTKAIF_IF_LOOPBACK1_MASK 0x1#define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0)/* AFE_ADDA_MTKAIF_RX_CFG2 */ #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 16#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16)#define MTKAIF_RXIF_DELAY_CYCLE_SFT 12#define MTKAIF_RXIF_DELAY_CYCLE_MASK 0xf#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)#define MTKAIF_RXIF_DELAY_DATA_SFT 8#define MTKAIF_RXIF_DELAY_DATA_MASK 0x1#define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)/* AFE_ADDA_DL_SRC2_CON0 */ #define DL_2_INPUT_MODE_CTL_SFT 28#define DL_2_INPUT_MODE_CTL_MASK 0xf#define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28)#define DL_2_CH1_SATURATION_EN_CTL_SFT 27#define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)#define DL_2_CH2_SATURATION_EN_CTL_SFT 26#define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)#define DL_2_OUTPUT_SEL_CTL_SFT 24#define DL_2_OUTPUT_SEL_CTL_MASK 0x3#define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)#define DL_2_FADEIN_0START_EN_SFT 16#define DL_2_FADEIN_0START_EN_MASK 0x3#define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)#define DL_DISABLE_HW_CG_CTL_SFT 15#define DL_DISABLE_HW_CG_CTL_MASK 0x1#define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)#define C_DATA_EN_SEL_CTL_PRE_SFT 14#define C_DATA_EN_SEL_CTL_PRE_MASK 0x1#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)#define DL2_ARAMPSP_CTL_PRE_SFT 9#define DL2_ARAMPSP_CTL_PRE_MASK 0x3#define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)#define DL_2_IIRMODE_CTL_PRE_SFT 6#define DL_2_IIRMODE_CTL_PRE_MASK 0x7#define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6)#define DL_2_VOICE_MODE_CTL_PRE_SFT 5#define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)#define DL_2_IIR_ON_CTL_PRE_SFT 2#define DL_2_IIR_ON_CTL_PRE_MASK 0x1#define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)#define DL_2_GAIN_ON_CTL_PRE_SFT 1#define DL_2_GAIN_ON_CTL_PRE_MASK 0x1#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)#define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0#define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1#define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)/* AFE_ADDA_DL_SRC2_CON1 */ #define DL_2_GAIN_CTL_PRE_SFT 16#define DL_2_GAIN_CTL_PRE_MASK 0xffff#define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16)#define DL_2_GAIN_MODE_CTL_SFT 0#define DL_2_GAIN_MODE_CTL_MASK 0x1#define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)/* AFE_ADDA_UL_SRC_CON0 */ #define ULCF_CFG_EN_CTL_SFT 31#define ULCF_CFG_EN_CTL_MASK 0x1#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)#define UL_DMIC_PHASE_SEL_CH1_SFT 27#define UL_DMIC_PHASE_SEL_CH1_MASK 0x7#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 27)#define UL_DMIC_PHASE_SEL_CH2_SFT 24#define UL_DMIC_PHASE_SEL_CH2_MASK 0x7#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 24)#define UL_MODE_3P25M_CH2_CTL_SFT 22#define UL_MODE_3P25M_CH2_CTL_MASK 0x1#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)#define UL_MODE_3P25M_CH1_CTL_SFT 21#define UL_MODE_3P25M_CH1_CTL_MASK 0x1#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)#define UL_AP_DMIC_ON_SFT 16#define UL_AP_DMIC_ON_MASK 0x1#define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16)#define DMIC_LOW_POWER_MODE_CTL_SFT 14#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)#define UL_DISABLE_HW_CG_CTL_SFT 12#define UL_DISABLE_HW_CG_CTL_MASK 0x1#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)#define UL_IIR_ON_TMP_CTL_SFT 10#define UL_IIR_ON_TMP_CTL_MASK 0x1#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)#define UL_IIRMODE_CTL_SFT 7#define UL_IIRMODE_CTL_MASK 0x7#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)#define DIGMIC_4P33M_SEL_SFT 6#define DIGMIC_4P33M_SEL_MASK 0x1#define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6)#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)#define UL_LOOP_BACK_MODE_CTL_SFT 2#define UL_LOOP_BACK_MODE_CTL_MASK 0x1#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)#define UL_SDM_3_LEVEL_CTL_SFT 1#define UL_SDM_3_LEVEL_CTL_MASK 0x1#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)#define UL_SRC_ON_TMP_CTL_SFT 0#define UL_SRC_ON_TMP_CTL_MASK 0x1#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)/* AFE_ADDA_UL_SRC_CON1 */ #define C_DAC_EN_CTL_SFT 27#define C_DAC_EN_CTL_MASK 0x1#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)#define C_MUTE_SW_CTL_SFT 26#define C_MUTE_SW_CTL_MASK 0x1#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)#define ASDM_SRC_SEL_CTL_SFT 25#define ASDM_SRC_SEL_CTL_MASK 0x1#define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)#define C_AMP_DIV_CH2_CTL_SFT 21#define C_AMP_DIV_CH2_CTL_MASK 0x7#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)#define C_FREQ_DIV_CH2_CTL_SFT 16#define C_FREQ_DIV_CH2_CTL_MASK 0x1f#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)#define C_SINE_MODE_CH2_CTL_SFT 12#define C_SINE_MODE_CH2_CTL_MASK 0xf#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)#define C_AMP_DIV_CH1_CTL_SFT 9#define C_AMP_DIV_CH1_CTL_MASK 0x7#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)#define C_FREQ_DIV_CH1_CTL_SFT 4#define C_FREQ_DIV_CH1_CTL_MASK 0x1f#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)#define C_SINE_MODE_CH1_CTL_SFT 0#define C_SINE_MODE_CH1_CTL_MASK 0xf#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)/* AFE_ADDA_TOP_CON0 */ #define C_LOOP_BACK_MODE_CTL_SFT 12#define C_LOOP_BACK_MODE_CTL_MASK 0xf#define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12)#define ADDA_UL_GAIN_MODE_SFT 8#define ADDA_UL_GAIN_MODE_MASK 0x3#define ADDA_UL_GAIN_MODE_MASK_SFT (0x3 << 8)#define C_EXT_ADC_CTL_SFT 0#define C_EXT_ADC_CTL_MASK 0x1#define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)/* AFE_ADDA_UL_DL_CON0 */ #define AFE_ADDA_UL_LR_SWAP_SFT 31#define AFE_ADDA_UL_LR_SWAP_MASK 0x1#define AFE_ADDA_UL_LR_SWAP_MASK_SFT (0x1 << 31)#define AFE_ADDA_CKDIV_RST_SFT 30#define AFE_ADDA_CKDIV_RST_MASK 0x1#define AFE_ADDA_CKDIV_RST_MASK_SFT (0x1 << 30)#define AFE_ADDA_FIFO_AUTO_RST_SFT 29#define AFE_ADDA_FIFO_AUTO_RST_MASK 0x1#define AFE_ADDA_FIFO_AUTO_RST_MASK_SFT (0x1 << 29)#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_SFT 21#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK 0x3#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 21)#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 20#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 20)#define AFE_ADDA6_UL_LR_SWAP_SFT 15#define AFE_ADDA6_UL_LR_SWAP_MASK 0x1#define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15)#define AFE_ADDA6_CKDIV_RST_SFT 14#define AFE_ADDA6_CKDIV_RST_MASK 0x1#define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14)#define AFE_ADDA6_FIFO_AUTO_RST_SFT 13#define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1#define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13)#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_SFT 5#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK 0x3#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 5)#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 4#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4)#define ADDA_AFE_ON_SFT 0#define ADDA_AFE_ON_MASK 0x1#define ADDA_AFE_ON_MASK_SFT (0x1 << 0)/* AFE_SIDETONE_CON0 */ #define R_RDY_SFT 30#define R_RDY_MASK 0x1#define R_RDY_MASK_SFT (0x1 << 30)#define W_RDY_SFT 29#define W_RDY_MASK 0x1#define W_RDY_MASK_SFT (0x1 << 29)#define R_W_EN_SFT 25#define R_W_EN_MASK 0x1#define R_W_EN_MASK_SFT (0x1 << 25)#define R_W_SEL_SFT 24#define R_W_SEL_MASK 0x1#define R_W_SEL_MASK_SFT (0x1 << 24)#define SEL_CH2_SFT 23#define SEL_CH2_MASK 0x1#define SEL_CH2_MASK_SFT (0x1 << 23)#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16#define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16)#define SIDE_TONE_COEFFICIENT_SFT 0#define SIDE_TONE_COEFFICIENT_MASK 0xffff#define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0)/* AFE_SIDETONE_COEFF */ #define SIDE_TONE_COEFF_SFT 0#define SIDE_TONE_COEFF_MASK 0xffff#define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0)/* AFE_SIDETONE_CON1 */ #define STF_BYPASS_MODE_SFT 31#define STF_BYPASS_MODE_MASK 0x1#define STF_BYPASS_MODE_MASK_SFT (0x1 << 31)#define STF_BYPASS_MODE_O28_O29_SFT 30#define STF_BYPASS_MODE_O28_O29_MASK 0x1#define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30)#define STF_BYPASS_MODE_I2S4_SFT 29#define STF_BYPASS_MODE_I2S4_MASK 0x1#define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29)#define STF_BYPASS_MODE_I2S5_SFT 28#define STF_BYPASS_MODE_I2S5_MASK 0x1#define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28)#define STF_BYPASS_MODE_DL3_SFT 27#define STF_BYPASS_MODE_DL3_MASK 0x1#define STF_BYPASS_MODE_DL3_MASK_SFT (0x1 << 27)#define STF_BYPASS_MODE_I2S7_SFT 26#define STF_BYPASS_MODE_I2S7_MASK 0x1#define STF_BYPASS_MODE_I2S7_MASK_SFT (0x1 << 26)#define STF_BYPASS_MODE_I2S9_SFT 25#define STF_BYPASS_MODE_I2S9_MASK 0x1#define STF_BYPASS_MODE_I2S9_MASK_SFT (0x1 << 25)#define STF_O19O20_OUT_EN_SEL_SFT 13#define STF_O19O20_OUT_EN_SEL_MASK 0x1#define STF_O19O20_OUT_EN_SEL_MASK_SFT (0x1 << 13)#define STF_SOURCE_FROM_O19O20_SFT 12#define STF_SOURCE_FROM_O19O20_MASK 0x1#define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12)#define SIDE_TONE_ON_SFT 8#define SIDE_TONE_ON_MASK 0x1#define SIDE_TONE_ON_MASK_SFT (0x1 << 8)#define SIDE_TONE_HALF_TAP_NUM_SFT 0#define SIDE_TONE_HALF_TAP_NUM_MASK 0x3f#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x3f << 0)/* AFE_SIDETONE_GAIN */ #define POSITIVE_GAIN_SFT 16#define POSITIVE_GAIN_MASK 0x7#define POSITIVE_GAIN_MASK_SFT (0x7 << 16)#define SIDE_TONE_GAIN_SFT 0#define SIDE_TONE_GAIN_MASK 0xffff#define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0)/* AFE_ADDA_DL_SDM_DCCOMP_CON */ #define USE_3RD_SDM_SFT 28#define USE_3RD_SDM_MASK 0x1#define USE_3RD_SDM_MASK_SFT (0x1 << 28)#define DL_FIFO_START_POINT_SFT 24#define DL_FIFO_START_POINT_MASK 0x7#define DL_FIFO_START_POINT_MASK_SFT (0x7 << 24)#define DL_FIFO_SWAP_SFT 20#define DL_FIFO_SWAP_MASK 0x1#define DL_FIFO_SWAP_MASK_SFT (0x1 << 20)#define C_AUDSDM1ORDSELECT_CTL_SFT 19#define C_AUDSDM1ORDSELECT_CTL_MASK 0x1#define C_AUDSDM1ORDSELECT_CTL_MASK_SFT (0x1 << 19)#define C_SDM7BITSEL_CTL_SFT 18#define C_SDM7BITSEL_CTL_MASK 0x1#define C_SDM7BITSEL_CTL_MASK_SFT (0x1 << 18)#define GAIN_AT_SDM_RST_PRE_CTL_SFT 15#define GAIN_AT_SDM_RST_PRE_CTL_MASK 0x1#define GAIN_AT_SDM_RST_PRE_CTL_MASK_SFT (0x1 << 15)#define DL_DCM_AUTO_IDLE_EN_SFT 14#define DL_DCM_AUTO_IDLE_EN_MASK 0x1#define DL_DCM_AUTO_IDLE_EN_MASK_SFT (0x1 << 14)#define AFE_DL_SRC_DCM_EN_SFT 13#define AFE_DL_SRC_DCM_EN_MASK 0x1#define AFE_DL_SRC_DCM_EN_MASK_SFT (0x1 << 13)#define AFE_DL_POST_SRC_DCM_EN_SFT 12#define AFE_DL_POST_SRC_DCM_EN_MASK 0x1#define AFE_DL_POST_SRC_DCM_EN_MASK_SFT (0x1 << 12)#define AUD_SDM_MONO_SFT 9#define AUD_SDM_MONO_MASK 0x1#define AUD_SDM_MONO_MASK_SFT (0x1 << 9)#define AUD_DC_COMP_EN_SFT 8#define AUD_DC_COMP_EN_MASK 0x1#define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)#define ATTGAIN_CTL_SFT 0#define ATTGAIN_CTL_MASK 0x3f#define ATTGAIN_CTL_MASK_SFT (0x3f << 0)/* AFE_SINEGEN_CON0 */ #define DAC_EN_SFT 26#define DAC_EN_MASK 0x1#define DAC_EN_MASK_SFT (0x1 << 26)#define MUTE_SW_CH2_SFT 25#define MUTE_SW_CH2_MASK 0x1#define MUTE_SW_CH2_MASK_SFT (0x1 << 25)#define MUTE_SW_CH1_SFT 24#define MUTE_SW_CH1_MASK 0x1#define MUTE_SW_CH1_MASK_SFT (0x1 << 24)#define SINE_MODE_CH2_SFT 20#define SINE_MODE_CH2_MASK 0xf#define SINE_MODE_CH2_MASK_SFT (0xf << 20)#define AMP_DIV_CH2_SFT 17#define AMP_DIV_CH2_MASK 0x7#define AMP_DIV_CH2_MASK_SFT (0x7 << 17)#define FREQ_DIV_CH2_SFT 12#define FREQ_DIV_CH2_MASK 0x1f#define FREQ_DIV_CH2_MASK_SFT (0x1f << 12)#define SINE_MODE_CH1_SFT 8#define SINE_MODE_CH1_MASK 0xf#define SINE_MODE_CH1_MASK_SFT (0xf << 8)#define AMP_DIV_CH1_SFT 5#define AMP_DIV_CH1_MASK 0x7#define AMP_DIV_CH1_MASK_SFT (0x7 << 5)#define FREQ_DIV_CH1_SFT 0#define FREQ_DIV_CH1_MASK 0x1f#define FREQ_DIV_CH1_MASK_SFT (0x1f << 0)/* AFE_SINEGEN_CON2 */ #define INNER_LOOP_BACK_MODE_SFT 0#define INNER_LOOP_BACK_MODE_MASK 0x3f#define INNER_LOOP_BACK_MODE_MASK_SFT (0x3f << 0)/* AFE_HD_ENGEN_ENABLE */ #define AFE_24M_ON_SFT 1#define AFE_24M_ON_MASK 0x1#define AFE_24M_ON_MASK_SFT (0x1 << 1)#define AFE_22M_ON_SFT 0#define AFE_22M_ON_MASK 0x1#define AFE_22M_ON_MASK_SFT (0x1 << 0)/* AFE_ADDA_DL_NLE_FIFO_MON */ #define DL_NLE_FIFO_WBIN_SFT 8#define DL_NLE_FIFO_WBIN_MASK 0xf#define DL_NLE_FIFO_WBIN_MASK_SFT (0xf << 8)#define DL_NLE_FIFO_RBIN_SFT 4#define DL_NLE_FIFO_RBIN_MASK 0xf#define DL_NLE_FIFO_RBIN_MASK_SFT (0xf << 4)#define DL_NLE_FIFO_RDACTIVE_SFT 3#define DL_NLE_FIFO_RDACTIVE_MASK 0x1#define DL_NLE_FIFO_RDACTIVE_MASK_SFT (0x1 << 3)#define DL_NLE_FIFO_STARTRD_SFT 2#define DL_NLE_FIFO_STARTRD_MASK 0x1#define DL_NLE_FIFO_STARTRD_MASK_SFT (0x1 << 2)#define DL_NLE_FIFO_RD_EMPTY_SFT 1#define DL_NLE_FIFO_RD_EMPTY_MASK 0x1#define DL_NLE_FIFO_RD_EMPTY_MASK_SFT (0x1 << 1)#define DL_NLE_FIFO_WR_FULL_SFT 0#define DL_NLE_FIFO_WR_FULL_MASK 0x1#define DL_NLE_FIFO_WR_FULL_MASK_SFT (0x1 << 0)/* AFE_DL1_CON0 */ #define DL1_MODE_SFT 24#define DL1_MODE_MASK 0xf#define DL1_MODE_MASK_SFT (0xf << 24)#define DL1_MINLEN_SFT 20#define DL1_MINLEN_MASK 0xf#define DL1_MINLEN_MASK_SFT (0xf << 20)#define DL1_MAXLEN_SFT 16#define DL1_MAXLEN_MASK 0xf#define DL1_MAXLEN_MASK_SFT (0xf << 16)#define DL1_SW_CLEAR_BUF_EMPTY_SFT 15#define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)#define DL1_PBUF_SIZE_SFT 12#define DL1_PBUF_SIZE_MASK 0x3#define DL1_PBUF_SIZE_MASK_SFT (0x3 << 12)#define DL1_MONO_SFT 8#define DL1_MONO_MASK 0x1#define DL1_MONO_MASK_SFT (0x1 << 8)#define DL1_NORMAL_MODE_SFT 5#define DL1_NORMAL_MODE_MASK 0x1#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 5)#define DL1_HALIGN_SFT 4#define DL1_HALIGN_MASK 0x1#define DL1_HALIGN_MASK_SFT (0x1 << 4)#define DL1_HD_MODE_SFT 0#define DL1_HD_MODE_MASK 0x3#define DL1_HD_MODE_MASK_SFT (0x3 << 0)/* AFE_DL2_CON0 */ #define DL2_MODE_SFT 24#define DL2_MODE_MASK 0xf#define DL2_MODE_MASK_SFT (0xf << 24)#define DL2_MINLEN_SFT 20#define DL2_MINLEN_MASK 0xf#define DL2_MINLEN_MASK_SFT (0xf << 20)#define DL2_MAXLEN_SFT 16#define DL2_MAXLEN_MASK 0xf#define DL2_MAXLEN_MASK_SFT (0xf << 16)#define DL2_SW_CLEAR_BUF_EMPTY_SFT 15#define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x1#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)#define DL2_PBUF_SIZE_SFT 12
Messung V0.5 C=97 H=96 G=96
¤ Dauer der Verarbeitung: 0.35 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
