Quelle arm-cmn.c
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// SPDX-License-Identifier: GPL-2.0 // Copyright (C) 2016-2020 Arm Limited // ARM CMN/CI interconnect PMU driver #include <linux/acpi.h>#include <linux/bitfield.h>#include <linux/bitops.h>#include <linux/debugfs.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/io-64 -nonatomic-lo-hi.h>#include <linux/kernel.h>#include <linux/list.h>#include <linux/module.h>#include <linux/of.h>#include <linux/perf_event.h>#include <linux/platform_device.h>#include <linux/slab.h>#include <linux/sort.h>/* Common register stuff */ #define CMN_NODE_INFO 0 x0000#define CMN_NI_NODE_TYPE GENMASK_ULL(15 , 0 )#define CMN_NI_NODE_ID GENMASK_ULL(31 , 16 )#define CMN_NI_LOGICAL_ID GENMASK_ULL(47 , 32 )#define CMN_CHILD_INFO 0 x0080#define CMN_CI_CHILD_COUNT GENMASK_ULL(15 , 0 )#define CMN_CI_CHILD_PTR_OFFSET GENMASK_ULL(31 , 16 )#define CMN_CHILD_NODE_ADDR GENMASK(29 , 0 )#define CMN_CHILD_NODE_EXTERNAL BIT(31 )#define CMN_MAX_DIMENSION 12 #define CMN_MAX_XPS (CMN_MAX_DIMENSION * CMN_MAX_DIMENSION)#define CMN_MAX_DTMS (CMN_MAX_XPS + (CMN_MAX_DIMENSION - 1 ) * 4 )/* Currently XPs are the node type we can have most of; others top out at 128 */ #define CMN_MAX_NODES_PER_EVENT CMN_MAX_XPS/* The CFG node has various info besides the discovery tree */ #define CMN_CFGM_PERIPH_ID_01 0 x0008#define CMN_CFGM_PID0_PART_0 GENMASK_ULL(7 , 0 )#define CMN_CFGM_PID1_PART_1 GENMASK_ULL(35 , 32 )#define CMN_CFGM_PERIPH_ID_23 0 x0010#define CMN_CFGM_PID2_REVISION GENMASK_ULL(7 , 4 )#define CMN_CFGM_INFO_GLOBAL 0 x0900#define CMN_INFO_MULTIPLE_DTM_EN BIT_ULL(63 )#define CMN_INFO_RSP_VC_NUM GENMASK_ULL(53 , 52 )#define CMN_INFO_DAT_VC_NUM GENMASK_ULL(51 , 50 )#define CMN_INFO_DEVICE_ISO_ENABLE BIT_ULL(44 )#define CMN_CFGM_INFO_GLOBAL_1 0 x0908#define CMN_INFO_SNP_VC_NUM GENMASK_ULL(3 , 2 )#define CMN_INFO_REQ_VC_NUM GENMASK_ULL(1 , 0 )/* XPs also have some local topology info which has uses too */ #define CMN_MXP__CONNECT_INFO(p) (0 x0008 + 8 * (p))#define CMN__CONNECT_INFO_DEVICE_TYPE GENMASK_ULL(5 , 0 )#define CMN_MAX_PORTS 6 #define CI700_CONNECT_INFO_P2_5_OFFSET 0 x10/* PMU registers occupy the 3rd 4KB page of each node's region */ #define CMN_PMU_OFFSET 0 x2000/* ...except when they don't :( */ #define CMN_S3_R1_DTM_OFFSET 0 xa000#define CMN_S3_PMU_OFFSET 0 xd900/* For most nodes, this is all there is */ #define CMN_PMU_EVENT_SEL 0 x000#define CMN__PMU_CBUSY_SNTHROTTLE_SEL GENMASK_ULL(44 , 42 )#define CMN__PMU_SN_HOME_SEL GENMASK_ULL(40 , 39 )#define CMN__PMU_HBT_LBT_SEL GENMASK_ULL(38 , 37 )#define CMN__PMU_CLASS_OCCUP_ID GENMASK_ULL(36 , 35 )/* Technically this is 4 bits wide on DNs, but we only use 2 there anyway */ #define CMN__PMU_OCCUP1_ID GENMASK_ULL(34 , 32 )/* Some types are designed to coexist with another device in the same node */ #define CMN_CCLA_PMU_EVENT_SEL 0 x008#define CMN_HNP_PMU_EVENT_SEL 0 x008/* DTMs live in the PMU space of XP registers */ #define CMN_DTM_WPn(n) (0 x1A0 + (n) * 0 x18)#define CMN_DTM_WPn_CONFIG(n) (CMN_DTM_WPn(n) + 0 x00)#define CMN_DTM_WPn_CONFIG_WP_CHN_NUM GENMASK_ULL(20 , 19 )#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL2 GENMASK_ULL(18 , 17 )#define CMN_DTM_WPn_CONFIG_WP_COMBINE BIT(9 )#define CMN_DTM_WPn_CONFIG_WP_EXCLUSIVE BIT(8 )#define CMN600_WPn_CONFIG_WP_COMBINE BIT(6 )#define CMN600_WPn_CONFIG_WP_EXCLUSIVE BIT(5 )#define CMN_DTM_WPn_CONFIG_WP_GRP GENMASK_ULL(5 , 4 )#define CMN_DTM_WPn_CONFIG_WP_CHN_SEL GENMASK_ULL(3 , 1 )#define CMN_DTM_WPn_CONFIG_WP_DEV_SEL BIT(0 )#define CMN_DTM_WPn_VAL(n) (CMN_DTM_WPn(n) + 0 x08)#define CMN_DTM_WPn_MASK(n) (CMN_DTM_WPn(n) + 0 x10)#define CMN_DTM_PMU_CONFIG 0 x210#define CMN__PMEVCNT0_INPUT_SEL GENMASK_ULL(37 , 32 )#define CMN__PMEVCNT0_INPUT_SEL_WP 0 x00#define CMN__PMEVCNT0_INPUT_SEL_XP 0 x04#define CMN__PMEVCNT0_INPUT_SEL_DEV 0 x10#define CMN__PMEVCNT0_GLOBAL_NUM GENMASK_ULL(18 , 16 )#define CMN__PMEVCNTn_GLOBAL_NUM_SHIFT(n) ((n) * 4 )#define CMN__PMEVCNT_PAIRED(n) BIT(4 + (n))#define CMN__PMEVCNT23_COMBINED BIT(2 )#define CMN__PMEVCNT01_COMBINED BIT(1 )#define CMN_DTM_PMU_CONFIG_PMU_EN BIT(0 )#define CMN_DTM_PMEVCNT 0 x220#define CMN_DTM_PMEVCNTSR 0 x240#define CMN650_DTM_UNIT_INFO 0 x0910#define CMN_DTM_UNIT_INFO 0 x0960#define CMN_DTM_UNIT_INFO_DTC_DOMAIN GENMASK_ULL(1 , 0 )#define CMN_DTM_NUM_COUNTERS 4 /* Want more local counters? Why not replicate the whole DTM! Ugh... */ #define CMN_DTM_OFFSET(n) ((n) * 0 x200)/* The DTC node is where the magic happens */ #define CMN_DT_DTC_CTL 0 x0a00#define CMN_DT_DTC_CTL_DT_EN BIT(0 )#define CMN_DT_DTC_CTL_CG_DISABLE BIT(10 )/* DTC counters are paired in 64-bit registers on a 16-byte stride. Yuck */ #define _CMN_DT_CNT_REG(n) ((((n) / 2 ) * 4 + (n) % 2 ) * 4 )#define CMN_DT_PMEVCNT(dtc, n) ((dtc)->pmu_base + _CMN_DT_CNT_REG(n))#define CMN_DT_PMCCNTR(dtc) ((dtc)->pmu_base + 0 x40)#define CMN_DT_PMEVCNTSR(dtc, n) ((dtc)->pmu_base + 0 x50 + _CMN_DT_CNT_REG(n))#define CMN_DT_PMCCNTRSR(dtc) ((dtc)->pmu_base + 0 x90)#define CMN_DT_PMCR(dtc) ((dtc)->pmu_base + 0 x100)#define CMN_DT_PMCR_PMU_EN BIT(0 )#define CMN_DT_PMCR_CNTR_RST BIT(5 )#define CMN_DT_PMCR_OVFL_INTR_EN BIT(6 )#define CMN_DT_PMOVSR(dtc) ((dtc)->pmu_base + 0 x118)#define CMN_DT_PMOVSR_CLR(dtc) ((dtc)->pmu_base + 0 x120)#define CMN_DT_PMSSR(dtc) ((dtc)->pmu_base + 0 x128)#define CMN_DT_PMSSR_SS_STATUS(n) BIT(n)#define CMN_DT_PMSRR(dtc) ((dtc)->pmu_base + 0 x130)#define CMN_DT_PMSRR_SS_REQ BIT(0 )#define CMN_DT_NUM_COUNTERS 8 #define CMN_MAX_DTCS 4 /* * Even in the worst case a DTC counter can't wrap in fewer than 2^42 cycles, * so throwing away one bit to make overflow handling easy is no big deal. #define CMN_COUNTER_INIT 0 x80000000/* Similarly for the 40-bit cycle counter */ #define CMN_CC_INIT 0 x8000000000ULL/* Event attributes */ #define CMN_CONFIG_TYPE GENMASK_ULL(15 , 0 )#define CMN_CONFIG_EVENTID GENMASK_ULL(26 , 16 )#define CMN_CONFIG_OCCUPID GENMASK_ULL(30 , 27 )#define CMN_CONFIG_BYNODEID BIT_ULL(31 )#define CMN_CONFIG_NODEID GENMASK_ULL(47 , 32 )#define CMN_EVENT_TYPE(event) FIELD_GET(CMN_CONFIG_TYPE, (event)->attr.config)#define CMN_EVENT_EVENTID(event) FIELD_GET(CMN_CONFIG_EVENTID, (event)->attr.config)#define CMN_EVENT_OCCUPID(event) FIELD_GET(CMN_CONFIG_OCCUPID, (event)->attr.config)#define CMN_EVENT_BYNODEID(event) FIELD_GET(CMN_CONFIG_BYNODEID, (event)->attr.config)#define CMN_EVENT_NODEID(event) FIELD_GET(CMN_CONFIG_NODEID, (event)->attr.config)#define CMN_CONFIG_WP_COMBINE GENMASK_ULL(30 , 27 )#define CMN_CONFIG_WP_DEV_SEL GENMASK_ULL(50 , 48 )#define CMN_CONFIG_WP_CHN_SEL GENMASK_ULL(55 , 51 )#define CMN_CONFIG_WP_GRP GENMASK_ULL(57 , 56 )#define CMN_CONFIG_WP_EXCLUSIVE BIT_ULL(58 )#define CMN_CONFIG1_WP_VAL GENMASK_ULL(63 , 0 )#define CMN_CONFIG2_WP_MASK GENMASK_ULL(63 , 0 )#define CMN_EVENT_WP_COMBINE(event) FIELD_GET(CMN_CONFIG_WP_COMBINE, (event)->attr.config)#define CMN_EVENT_WP_DEV_SEL(event) FIELD_GET(CMN_CONFIG_WP_DEV_SEL, (event)->attr.config)#define CMN_EVENT_WP_CHN_SEL(event) FIELD_GET(CMN_CONFIG_WP_CHN_SEL, (event)->attr.config)#define CMN_EVENT_WP_GRP(event) FIELD_GET(CMN_CONFIG_WP_GRP, (event)->attr.config)#define CMN_EVENT_WP_EXCLUSIVE(event) FIELD_GET(CMN_CONFIG_WP_EXCLUSIVE, (event)->attr.config)#define CMN_EVENT_WP_VAL(event) FIELD_GET(CMN_CONFIG1_WP_VAL, (event)->attr.config1)#define CMN_EVENT_WP_MASK(event) FIELD_GET(CMN_CONFIG2_WP_MASK, (event)->attr.config2)/* Made-up event IDs for watchpoint direction */ #define CMN_WP_UP 0 #define CMN_WP_DOWN 2 /* Internal values for encoding event support */ enum cmn_model {1 ,2 ,4 ,8 ,16 ,/* ...and then we can use bitmap tricks for commonality */ 1 ,2 ,/* Actual part numbers and revision IDs defined by the hardware */ enum cmn_part {0 x434,0 x436,0 x43c,0 x43a,0 x43e,/* CMN-600 r0px shouldn't exist in silicon, thankfully */ enum cmn_revision {0 ,0 ,0 ,0 ,enum cmn_node_type {0 xd,0 xf,0 x100,0 x200,0 x1000,/* Not a real node type */ 0 x7770enum cmn_filter_select {1 ,struct arm_cmn_node {void __iomem *pmu_base;enum cmn_node_type type;/* XP properties really, but replicated to children for convenience */ 4 ;4 ;/* DN/HN-F/CXHA */ struct {4 ;4 ;union {4 ];4 ];struct arm_cmn_dtm {void __iomem *base;union {4 ];4 ];struct arm_cmn_dtc {void __iomem *base;void __iomem *pmu_base;int irq;bool cc_active;struct perf_event *counters[CMN_DT_NUM_COUNTERS];struct perf_event *cycles;#define CMN_STATE_DISABLED BIT(0 )#define CMN_STATE_TXN BIT(1 )struct arm_cmn {struct device *dev;void __iomem *base;unsigned int state;enum cmn_revision rev;enum cmn_part part;bool multi_dtm;struct {unsigned int rsp_vc_num : 2 ;unsigned int dat_vc_num : 2 ;unsigned int snp_vc_num : 2 ;unsigned int req_vc_num : 2 ;struct arm_cmn_node *xps;struct arm_cmn_node *dns;struct arm_cmn_dtm *dtms;struct arm_cmn_dtc *dtc;unsigned int num_dtcs;int cpu;struct hlist_node cpuhp_node;struct pmu pmu;struct dentry *debug;#define to_cmn(p) container_of(p, struct arm_cmn, pmu)static int arm_cmn_hp_state;struct arm_cmn_nodeid {static int arm_cmn_xyidbits(const struct arm_cmn *cmn)return fls((cmn->mesh_x - 1 ) | (cmn->mesh_y - 1 ));static struct arm_cmn_nodeid arm_cmn_nid(const struct arm_cmn_node *dn)struct arm_cmn_nodeid nid;1 U << dn->deviceid_bits) - 1 );1 U << dn->portid_bits) - 1 );return nid;static struct arm_cmn_node *arm_cmn_node_to_xp(const struct arm_cmn *cmn,const struct arm_cmn_node *dn)int id = dn->id >> (dn->portid_bits + dn->deviceid_bits);int bits = arm_cmn_xyidbits(cmn);int x = id >> bits;int y = id & ((1 U << bits) - 1 );return cmn->xps + cmn->mesh_x * y + x;static struct arm_cmn_node *arm_cmn_node(const struct arm_cmn *cmn,enum cmn_node_type type)struct arm_cmn_node *dn;for (dn = cmn->dns; dn->type; dn++)if (dn->type == type)return dn;return NULL;static enum cmn_model arm_cmn_model(const struct arm_cmn *cmn)switch (cmn->part) {case PART_CMN600:return CMN600;case PART_CMN650:return CMN650;case PART_CMN700:return CMN700;case PART_CI700:return CI700;case PART_CMN_S3:return CMNS3;default :return 0 ;static int arm_cmn_pmu_offset(const struct arm_cmn *cmn, const struct arm_cmn_node *dn)if (cmn->part == PART_CMN_S3) {if (cmn->rev >= REV_CMNS3_R1P0 && dn->type == CMN_TYPE_XP)return CMN_S3_R1_DTM_OFFSET;return CMN_S3_PMU_OFFSET;return CMN_PMU_OFFSET;static u32 arm_cmn_device_connect_info(const struct arm_cmn *cmn,const struct arm_cmn_node *xp, int port)int offset = CMN_MXP__CONNECT_INFO(port) - arm_cmn_pmu_offset(cmn, xp);if (port >= 2 ) {if (cmn->part == PART_CMN600 || cmn->part == PART_CMN650)return 0 ;/* * CI-700 may have extra ports, but still has the * mesh_port_connect_info registers in the way. if (cmn->part == PART_CI700)return readl_relaxed(xp->pmu_base + offset);static struct dentry *arm_cmn_debugfs;#ifdef CONFIG_DEBUG_FSstatic const char *arm_cmn_device_type(u8 type)switch (FIELD_GET(CMN__CONNECT_INFO_DEVICE_TYPE, type)) {case 0 x00: return " |" ;case 0 x01: return " RN-I |" ;case 0 x02: return " RN-D |" ;case 0 x04: return " RN-F_B |" ;case 0 x05: return "RN-F_B_E|" ;case 0 x06: return " RN-F_A |" ;case 0 x07: return "RN-F_A_E|" ;case 0 x08: return " HN-T |" ;case 0 x09: return " HN-I |" ;case 0 x0a: return " HN-D |" ;case 0 x0b: return " HN-P |" ;case 0 x0c: return " SN-F |" ;case 0 x0d: return " SBSX |" ;case 0 x0e: return " HN-F |" ;case 0 x0f: return " SN-F_E |" ;case 0 x10: return " SN-F_D |" ;case 0 x11: return " CXHA |" ;case 0 x12: return " CXRA |" ;case 0 x13: return " CXRH |" ;case 0 x14: return " RN-F_D |" ;case 0 x15: return "RN-F_D_E|" ;case 0 x16: return " RN-F_C |" ;case 0 x17: return "RN-F_C_E|" ;case 0 x18: return " RN-F_E |" ;case 0 x19: return "RN-F_E_E|" ;case 0 x1a: return " HN-S |" ;case 0 x1b: return " LCN |" ;case 0 x1c: return " MTSX |" ;case 0 x1d: return " HN-V |" ;case 0 x1e: return " CCG |" ;case 0 x20: return " RN-F_F |" ;case 0 x21: return "RN-F_F_E|" ;case 0 x22: return " SN-F_F |" ;default : return " ???? |" ;static void arm_cmn_show_logid(struct seq_file *s, const struct arm_cmn_node *xp, int p, int d)struct arm_cmn *cmn = s->private ;struct arm_cmn_node *dn;for (dn = cmn->dns; dn->type; dn++) {int pad = dn->logid < 10 ;if (dn->type == CMN_TYPE_XP)continue ;/* Ignore the extra components that will overlap on some ports */ if (dn->type < CMN_TYPE_HNI)continue ;if (dn->id != id)continue ;" %*c#%-*d |" , pad + 1 , ' ' , 3 - pad, dn->logid);return ;" |" );static int arm_cmn_map_show(struct seq_file *s, void *data)struct arm_cmn *cmn = s->private ;int x, y, p, pmax = fls(cmn->ports_used);" X" );for (x = 0 ; x < cmn->mesh_x; x++)" %-2d " , x);"\nY P D+" );while (y--) {int xp_base = cmn->mesh_x * y;struct arm_cmn_node *xp = cmn->xps + xp_base;for (x = 0 ; x < cmn->mesh_x; x++)"--------+" );"\n%-2d |" , y);for (x = 0 ; x < cmn->mesh_x; x++) {for (p = 0 ; p < CMN_MAX_PORTS; p++)" XP #%-3d|" , xp_base + x);"\n |" );for (x = 0 ; x < cmn->mesh_x; x++) {if (dtc < 0 )" DTC ?? |" );else " DTC %d |" , dtc);"\n |" );for (x = 0 ; x < cmn->mesh_x; x++)"........|" );for (p = 0 ; p < pmax; p++) {"\n %d |" , p);for (x = 0 ; x < cmn->mesh_x; x++)"\n 0|" );for (x = 0 ; x < cmn->mesh_x; x++)0 );"\n 1|" );for (x = 0 ; x < cmn->mesh_x; x++)1 );"\n-----+" );for (x = 0 ; x < cmn->mesh_x; x++)"--------+" );"\n" );return 0 ;static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id)const char *name = "map" ;if (id > 0 )"map_%d" , id);if (!name)return ;0444 , arm_cmn_debugfs, cmn, &arm_cmn_map_fops);#else static void arm_cmn_debugfs_init(struct arm_cmn *cmn, int id) {}#endif struct arm_cmn_hw_event {struct arm_cmn_node *dn;2 , 64 )];/* * WP config registers are divided to UP and DOWN events. We need to * keep to track only one of them. bool wide_sel;enum cmn_filter_select filter_sel;sizeof (struct arm_cmn_hw_event) <= offsetof(struct hw_perf_event, target));#define for_each_hw_dn(hw, dn, i) \for (i = 0 , dn = hw->dn; i < hw->num_dns; i++, dn++)/* @i is the DTC number, @idx is the counter index on that DTC */ #define for_each_hw_dtc_idx(hw, i, idx) \for (int i = 0 , idx; i < CMN_MAX_DTCS; i++) if ((idx = hw->dtc_idx[i]) >= 0 )static struct arm_cmn_hw_event *to_cmn_hw(struct perf_event *event)return (struct arm_cmn_hw_event *)&event->hw;static void arm_cmn_set_index(u64 x[], unsigned int pos, unsigned int val)32 ] |= (u64)val << ((pos % 32 ) * 2 );static unsigned int arm_cmn_get_index(u64 x[], unsigned int pos)return (x[pos / 32 ] >> ((pos % 32 ) * 2 )) & 3 ;static void arm_cmn_set_wp_idx(unsigned long *wp_idx, unsigned int pos, bool val)if (val)static unsigned int arm_cmn_get_wp_idx(unsigned long *wp_idx, unsigned int pos)return test_bit(pos, wp_idx);struct arm_cmn_event_attr {struct device_attribute attr;enum cmn_model model;enum cmn_node_type type;enum cmn_filter_select fsel;struct arm_cmn_format_attr {struct device_attribute attr;int config;#define _CMN_EVENT_ATTR(_model, _name, _type, _eventid, _occupid, _fsel)\struct arm_cmn_event_attr[]) {{ \0444 , arm_cmn_event_show, NULL), \0 ].attr.attr)#define CMN_EVENT_ATTR(_model, _name, _type, _eventid) \0 , SEL_NONE)static ssize_t arm_cmn_event_show(struct device *dev,struct device_attribute *attr, char *buf)struct arm_cmn_event_attr *eattr;if (eattr->type == CMN_TYPE_DTC)return sysfs_emit(buf, "type=0x%x\n" , eattr->type);if (eattr->type == CMN_TYPE_WP)return sysfs_emit(buf,"type=0x%x,eventid=0x%x,wp_dev_sel=?,wp_chn_sel=?,wp_grp=?,wp_val=?,wp_mask=?\n" ,if (eattr->fsel > SEL_NONE)return sysfs_emit(buf, "type=0x%x,eventid=0x%x,occupid=0x%x\n" ,return sysfs_emit(buf, "type=0x%x,eventid=0x%x\n" , eattr->type,static umode_t arm_cmn_event_attr_is_visible(struct kobject *kobj,struct attribute *attr,int unused)struct device *dev = kobj_to_dev(kobj);struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));struct arm_cmn_event_attr *eattr;enum cmn_node_type type;if (!(eattr->model & arm_cmn_model(cmn)))return 0 ;/* Watchpoints aren't nodes, so avoid confusion */ if (type == CMN_TYPE_WP)return attr->mode;/* Hide XP events for unused interfaces/channels */ if (type == CMN_TYPE_XP) {unsigned int intf = (eventid >> 2 ) & 7 ;unsigned int chan = eventid >> 5 ;if ((intf & 4 ) && !(cmn->ports_used & BIT(intf & 3 )))return 0 ;if (chan == 4 && cmn->part == PART_CMN600)return 0 ;if ((chan == 5 && cmn->rsp_vc_num < 2 ) ||6 && cmn->dat_vc_num < 2 ) ||7 && cmn->req_vc_num < 2 ) ||8 && cmn->snp_vc_num < 2 ))return 0 ;/* Revision-specific differences */ if (cmn->part == PART_CMN600) {if (cmn->rev < REV_CMN600_R1P3) {if (type == CMN_TYPE_CXRA && eventid > 0 x10)return 0 ;if (cmn->rev < REV_CMN600_R1P2) {if (type == CMN_TYPE_HNF && eventid == 0 x1b)return 0 ;if (type == CMN_TYPE_CXRA || type == CMN_TYPE_CXHA)return 0 ;else if (cmn->part == PART_CMN650) {if (cmn->rev < REV_CMN650_R2P0 || cmn->rev == REV_CMN650_R1P2) {if (type == CMN_TYPE_HNF && eventid > 0 x22)return 0 ;if (type == CMN_TYPE_SBSX && eventid == 0 x17)return 0 ;if (type == CMN_TYPE_RNI && eventid > 0 x10)return 0 ;else if (cmn->part == PART_CMN700) {if (cmn->rev < REV_CMN700_R2P0) {if (type == CMN_TYPE_HNF && eventid > 0 x2c)return 0 ;if (type == CMN_TYPE_CCHA && eventid > 0 x74)return 0 ;if (type == CMN_TYPE_CCLA && eventid > 0 x27)return 0 ;if (cmn->rev < REV_CMN700_R1P0) {if (type == CMN_TYPE_HNF && eventid > 0 x2b)return 0 ;if (!arm_cmn_node(cmn, type))return 0 ;return attr->mode;#define _CMN_EVENT_DVM(_model, _name, _event, _occup, _fsel) \## _name, CMN_TYPE_DVM, _event, _occup, _fsel)#define CMN_EVENT_DTC(_name) \## _name, CMN_TYPE_DTC, 0 )#define CMN_EVENT_HNF(_model, _name, _event) \## _name, CMN_TYPE_HNF, _event)#define CMN_EVENT_HNI(_name, _event) \## _name, CMN_TYPE_HNI, _event)#define CMN_EVENT_HNP(_name, _event) \## _name, CMN_TYPE_HNP, _event)#define __CMN_EVENT_XP(_name, _event) \## _name, CMN_TYPE_XP, _event)#define CMN_EVENT_SBSX(_model, _name, _event) \## _name, CMN_TYPE_SBSX, _event)#define CMN_EVENT_RNID(_model, _name, _event) \## _name, CMN_TYPE_RNI, _event)#define CMN_EVENT_MTSX(_name, _event) \## _name, CMN_TYPE_MTSX, _event)#define CMN_EVENT_CXRA(_model, _name, _event) \## _name, CMN_TYPE_CXRA, _event)#define CMN_EVENT_CXHA(_name, _event) \## _name, CMN_TYPE_CXHA, _event)#define CMN_EVENT_CCRA(_name, _event) \## _name, CMN_TYPE_CCRA, _event)#define CMN_EVENT_CCHA(_model, _name, _event) \## _name, CMN_TYPE_CCHA, _event)#define CMN_EVENT_CCLA(_name, _event) \## _name, CMN_TYPE_CCLA, _event)#define CMN_EVENT_HNS(_name, _event) \## _name, CMN_TYPE_HNS, _event)#define CMN_EVENT_DVM(_model, _name, _event) \0 , SEL_NONE)#define CMN_EVENT_DVM_OCC(_model, _name, _event) \## _all, _event, 0 , SEL_OCCUP1ID), \## _dvmop, _event, 1 , SEL_OCCUP1ID), \## _dvmsync, _event, 2 , SEL_OCCUP1ID)#define CMN_EVENT_HN_OCC(_model, _name, _type, _event) \## _all, _type, _event, 0 , SEL_OCCUP1ID), \## _read, _type, _event, 1 , SEL_OCCUP1ID), \## _write, _type, _event, 2 , SEL_OCCUP1ID), \## _atomic, _type, _event, 3 , SEL_OCCUP1ID), \## _stash, _type, _event, 4 , SEL_OCCUP1ID)#define CMN_EVENT_HN_CLS(_model, _name, _type, _event) \## _class0, _type, _event, 0 , SEL_CLASS_OCCUP_ID), \## _class1, _type, _event, 1 , SEL_CLASS_OCCUP_ID), \## _class2, _type, _event, 2 , SEL_CLASS_OCCUP_ID), \## _class3, _type, _event, 3 , SEL_CLASS_OCCUP_ID)#define CMN_EVENT_HN_SNT(_model, _name, _type, _event) \## _all, _type, _event, 0 , SEL_CBUSY_SNTHROTTLE_SEL), \## _group0_read, _type, _event, 1 , SEL_CBUSY_SNTHROTTLE_SEL), \## _group0_write, _type, _event, 2 , SEL_CBUSY_SNTHROTTLE_SEL), \## _group1_read, _type, _event, 3 , SEL_CBUSY_SNTHROTTLE_SEL), \## _group1_write, _type, _event, 4 , SEL_CBUSY_SNTHROTTLE_SEL), \## _read, _type, _event, 5 , SEL_CBUSY_SNTHROTTLE_SEL), \## _write, _type, _event, 6 , SEL_CBUSY_SNTHROTTLE_SEL)#define CMN_EVENT_HNF_OCC(_model, _name, _event) \## _name, CMN_TYPE_HNF, _event)#define CMN_EVENT_HNF_CLS(_model, _name, _event) \## _name, CMN_TYPE_HNF, _event)#define CMN_EVENT_HNF_SNT(_model, _name, _event) \## _name, CMN_TYPE_HNF, _event)#define CMN_EVENT_HNS_OCC(_name, _event) \## _name, CMN_TYPE_HNS, _event), \## _name## _rxsnp, CMN_TYPE_HNS, _event, 5 , SEL_OCCUP1ID), \## _name## _lbt, CMN_TYPE_HNS, _event, 6 , SEL_OCCUP1ID), \## _name## _hbt, CMN_TYPE_HNS, _event, 7 , SEL_OCCUP1ID)#define CMN_EVENT_HNS_CLS( _name, _event) \## _name, CMN_TYPE_HNS, _event)#define CMN_EVENT_HNS_SNT(_name, _event) \## _name, CMN_TYPE_HNS, _event)#define CMN_EVENT_HNS_HBT(_name, _event) \## _name## _all, CMN_TYPE_HNS, _event, 0 , SEL_HBT_LBT_SEL), \## _name## _hbt, CMN_TYPE_HNS, _event, 1 , SEL_HBT_LBT_SEL), \## _name## _lbt, CMN_TYPE_HNS, _event, 2 , SEL_HBT_LBT_SEL)#define CMN_EVENT_HNS_SNH(_name, _event) \## _name## _all, CMN_TYPE_HNS, _event, 0 , SEL_SN_HOME_SEL), \## _name## _sn, CMN_TYPE_HNS, _event, 1 , SEL_SN_HOME_SEL), \## _name## _home, CMN_TYPE_HNS, _event, 2 , SEL_SN_HOME_SEL)#define _CMN_EVENT_XP_MESH(_name, _event) \## _name, (_event) | (0 << 2 )), \## _name, (_event) | (1 << 2 )), \## _name, (_event) | (2 << 2 )), \## _name, (_event) | (3 << 2 ))#define _CMN_EVENT_XP_PORT(_name, _event) \## _name, (_event) | (4 << 2 )), \## _name, (_event) | (5 << 2 )), \## _name, (_event) | (6 << 2 )), \## _name, (_event) | (7 << 2 ))#define _CMN_EVENT_XP(_name, _event) \/* Good thing there are only 3 fundamental XP events... */ #define CMN_EVENT_XP(_name, _event) \## _name, (_event) | (0 << 5 )), \## _name, (_event) | (1 << 5 )), \## _name, (_event) | (2 << 5 )), \## _name, (_event) | (3 << 5 )), \## _name, (_event) | (4 << 5 )), \## _name, (_event) | (5 << 5 )), \## _name, (_event) | (6 << 5 )), \## _name, (_event) | (7 << 5 )), \## _name, (_event) | (8 << 5 ))#define CMN_EVENT_XP_DAT(_name, _event) \## _name, (_event) | (3 << 5 )), \## _name, (_event) | (6 << 5 ))static struct attribute *arm_cmn_event_attrs[] = {/* * DVM node events conflict with HN-I events in the equivalent PMU * slot, but our lazy short-cut of using the DTM counter index for * the PMU index as well happens to avoid that by construction. 0 x01),0 x02),0 x03),0 x04),0 x05),0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x0f),0 x10),0 x11),0 x12),0 x13),0 x14),0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x0f),0 x10),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x18),0 x19),0 x1a),0 x1b),0 x1c),0 x1d),0 x1e),0 x1f),0 x20),0 x21),0 x22),0 x23),0 x24),0 x25),0 x26),0 x27),0 x28),0 x29),0 x2a),0 x2b),0 x2c),0 x2d),0 x2e),0 x2f),0 x20),0 x21),0 x22),0 x23),0 x24),0 x25),0 x26),0 x27),0 x28),0 x29),0 x2a),0 x2b),0 x2c),0 x2d),0 x2e),0 x2f),0 x30),0 x31),0 x32),/* * HN-P events squat on top of the HN-I similarly to DVM events, except * for being crammed into the same physical node as well. And of course * where would the fun be if the same events were in the same order... 0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x01),0 x02),0 x03),/* We treat watchpoints as a special made-up class of XP events */ 0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x21),0 x22),0 x23),0 x24),0 x25),0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x0f),0 x10),0 x11),0 x12),0 x13),0 x14),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x18),0 x19),0 x1a),0 x1b),0 x1c),0 x1d),0 x1e),0 x1f),0 x20),0 x21),0 x22),0 x23),0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x0f),0 x10),0 x11),0 x12),0 x13),0 x14),0 x15),0 x21),0 x22),0 x23),0 x24),0 x25),0 x26),0 x27),0 x28),0 x29),0 x2a),0 x2b),0 x2c),0 x2d),0 x41),0 x42),0 x43),0 x44),0 x45),0 x46),0 x47),0 x48),0 x49),0 x4a),0 x4b),0 x4c),0 x4d),0 x4e),0 x4f),0 x50),0 x51),0 x52),0 x53),0 x54),0 x55),0 x56),0 x57),0 x58),0 x59),0 x5a),0 x61),0 x62),0 x63),0 x64),0 x65),0 x66),0 x67),0 x68),0 x69),0 x6a),0 x6b),0 x6c),0 x6d),0 x6e),0 x6f),0 x70),0 x71),0 x72),0 x73),0 x74),0 x75),0 x76),0 x77),0 x78),0 x79),0 x7a),0 x7b),0 x7c),0 x7d),0 x7e),0 x7f),0 x80),0 x81),0 x82),0 x83),0 x84),0 x85),0 x21),0 x22),0 x23),0 x24),0 x25),0 x26),0 x27),0 x28),0 x29),0 x2a),0 x2b),0 x01),0 x02),0 x03),0 x04),0 x05),0 x06),0 x07),0 x08),0 x09),0 x0a),0 x0b),0 x0c),0 x0d),0 x0e),0 x0f),0 x10),0 x11),0 x12),0 x13),0 x14),0 x15),0 x16),0 x17),0 x18),0 x19),0 x1a),0 x1c),0 x1d),0 x1e),0 x1f),0 x20),0 x21),0 x22),0 x23),0 x24),0 x25),0 x26),0 x27),0 x28),0 x29),0 x2a),0 x2b),0 x2c),0 x2d),0 x2e),0 x2f),0 x30),0 x31),0 x32),0 x33),0 x34),0 x35),0 x36),0 x37),0 x38),0 x39),0 x3a),0 x3b),0 x3c),static const struct attribute_group arm_cmn_event_attrs_group = {"events" ,static ssize_t arm_cmn_format_show(struct device *dev,struct device_attribute *attr, char *buf)struct arm_cmn_format_attr *fmt = container_of(attr, typeof(*fmt), attr);if (!fmt->config)return sysfs_emit(buf, "config:%*pbl\n" , 64 , &fmt->field);return sysfs_emit(buf, "config%d:%*pbl\n" , fmt->config, 64 , &fmt->field);#define _CMN_FORMAT_ATTR(_name, _cfg, _fld) \struct arm_cmn_format_attr[]) {{ \0444 , arm_cmn_format_show, NULL), \0 ].attr.attr)#define CMN_FORMAT_ATTR(_name, _fld) _CMN_FORMAT_ATTR(_name, 0 , _fld)static struct attribute *arm_cmn_format_attrs[] = {1 , CMN_CONFIG1_WP_VAL),2 , CMN_CONFIG2_WP_MASK),static const struct attribute_group arm_cmn_format_attrs_group = {"format" ,static ssize_t arm_cmn_cpumask_show(struct device *dev,struct device_attribute *attr, char *buf)struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));return cpumap_print_to_pagebuf(true , buf, cpumask_of(cmn->cpu));static struct device_attribute arm_cmn_cpumask_attr =0444 , arm_cmn_cpumask_show, NULL);static ssize_t arm_cmn_identifier_show(struct device *dev,struct device_attribute *attr, char *buf)struct arm_cmn *cmn = to_cmn(dev_get_drvdata(dev));return sysfs_emit(buf, "%03x%02x\n" , cmn->part, cmn->rev);static struct device_attribute arm_cmn_identifier_attr =0444 , arm_cmn_identifier_show, NULL);static struct attribute *arm_cmn_other_attrs[] = {static const struct attribute_group arm_cmn_other_attrs_group = {static const struct attribute_group *arm_cmn_attr_groups[] = {static int arm_cmn_find_free_wp_idx(struct arm_cmn_dtm *dtm,struct perf_event *event)int wp_idx = CMN_EVENT_EVENTID(event);if (dtm->wp_event[wp_idx] >= 0 )if (dtm->wp_event[++wp_idx] >= 0 )return -ENOSPC;return wp_idx;static int arm_cmn_get_assigned_wp_idx(struct perf_event *event,struct arm_cmn_hw_event *hw,unsigned int pos)return CMN_EVENT_EVENTID(event) + arm_cmn_get_wp_idx(hw->wp_idx, pos);static void arm_cmn_claim_wp_idx(struct arm_cmn_dtm *dtm,struct perf_event *event,unsigned int dtc, int wp_idx,unsigned int pos)struct arm_cmn_hw_event *hw = to_cmn_hw(event);static u32 arm_cmn_wp_config(struct perf_event *event, int wp_idx)bool is_cmn600 = to_cmn(event->pmu)->part == PART_CMN600;/* CMN-600 supports only primary and secondary matching groups */ if (is_cmn600)1 ;1 );if (exc)/* wp_combine is available only on WP0 and WP2 */ if (combine && !(wp_idx & 0 x1))return config;static void arm_cmn_set_state(struct arm_cmn *cmn, u32 state)if (!cmn->state)0 , CMN_DT_PMCR(&cmn->dtc[0 ]));static void arm_cmn_clear_state(struct arm_cmn *cmn, u32 state)if (!cmn->state)0 ]));static void arm_cmn_pmu_enable(struct pmu *pmu)static void arm_cmn_pmu_disable(struct pmu *pmu)static u64 arm_cmn_read_dtm(struct arm_cmn *cmn, struct arm_cmn_hw_event *hw,bool snapshot)struct arm_cmn_dtm *dtm = NULL;struct arm_cmn_node *dn;unsigned int i, offset, dtm_idx;0 ;if (dtm != &cmn->dtms[dn->dtm]) {16 ));return count;static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)void __iomem *pmccntr = CMN_DT_PMCCNTR(dtc);return (val - CMN_CC_INIT) & ((CMN_CC_INIT << 1 ) - 1 );static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)void __iomem *pmevcnt = CMN_DT_PMEVCNT(dtc, idx);return val - CMN_COUNTER_INIT;static void arm_cmn_init_counter(struct perf_event *event)struct arm_cmn *cmn = to_cmn(event->pmu);struct arm_cmn_hw_event *hw = to_cmn_hw(event);false );static void arm_cmn_event_read(struct perf_event *event)struct arm_cmn *cmn = to_cmn(event->pmu);struct arm_cmn_hw_event *hw = to_cmn_hw(event);new , prev;unsigned long flags;if (CMN_EVENT_TYPE(event) == CMN_TYPE_DTC) {0 ]);return ;new = arm_cmn_read_dtm(cmn, hw, false );new );new - prev;new = arm_cmn_read_counter(cmn->dtc + i, idx);new << 16 ;static int arm_cmn_set_event_sel_hi(struct arm_cmn_node *dn,enum cmn_filter_select fsel, u8 occupid)if (fsel == SEL_NONE)return 0 ;if (!dn->occupid[fsel].count) {32 , dn->pmu_base + CMN_PMU_EVENT_SEL + 4 );else if (dn->occupid[fsel].val != occupid) {return -EBUSY;return 0 ;static void arm_cmn_set_event_sel_lo(struct arm_cmn_node *dn, int dtm_idx,int eventid, bool wide_sel)if (wide_sel) {else {static void arm_cmn_event_start(struct perf_event *event, int flags)struct arm_cmn *cmn = to_cmn(event->pmu);struct arm_cmn_hw_event *hw = to_cmn_hw(event);struct arm_cmn_node *dn;enum cmn_node_type type = CMN_EVENT_TYPE(event);int i;if (type == CMN_TYPE_DTC) {struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0 ];true ;else if (type == CMN_TYPE_WP) {void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);else for_each_hw_dn(hw, dn, i) {int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);static void arm_cmn_event_stop(struct perf_event *event, int flags)struct arm_cmn *cmn = to_cmn(event->pmu);struct arm_cmn_hw_event *hw = to_cmn_hw(event);struct arm_cmn_node *dn;enum cmn_node_type type = CMN_EVENT_TYPE(event);int i;if (type == CMN_TYPE_DTC) {struct arm_cmn_dtc *dtc = cmn->dtc + hw->dtc_idx[0 ];false ;else if (type == CMN_TYPE_WP) {void __iomem *base = dn->pmu_base + CMN_DTM_OFFSET(hw->dtm_offset);int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);0 , base + CMN_DTM_WPn_MASK(wp_idx));0 ULL, base + CMN_DTM_WPn_VAL(wp_idx));else for_each_hw_dn(hw, dn, i) {int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);0 , hw->wide_sel);struct arm_cmn_val {4 ];2 ];int dtc_count[CMN_MAX_DTCS];bool cycles;static int arm_cmn_val_find_free_wp_config(struct perf_event *event,struct arm_cmn_val *val, int dtm)int wp_idx = CMN_EVENT_EVENTID(event);if (val->wp[dtm][wp_idx])if (val->wp[dtm][++wp_idx])return -ENOSPC;return wp_idx;static void arm_cmn_val_add_event(struct arm_cmn *cmn, struct arm_cmn_val *val,struct perf_event *event)struct arm_cmn_hw_event *hw = to_cmn_hw(event);struct arm_cmn_node *dn;enum cmn_node_type type;int i;if (is_software_event(event))return ;if (type == CMN_TYPE_DTC) {true ;return ;int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;if (sel > SEL_NONE)1 ;if (type != CMN_TYPE_WP)continue ;1 ;1 ] += !!CMN_EVENT_WP_COMBINE(event);static int arm_cmn_validate_group(struct arm_cmn *cmn, struct perf_event *event)struct arm_cmn_hw_event *hw = to_cmn_hw(event);struct arm_cmn_node *dn;struct perf_event *sibling, *leader = event->group_leader;enum cmn_node_type type;struct arm_cmn_val *val;int i, ret = -EINVAL;if (leader == event)return 0 ;if (event->pmu != leader->pmu && !is_software_event(leader))return -EINVAL;sizeof (*val), GFP_KERNEL);if (!val)return -ENOMEM;if (type == CMN_TYPE_DTC) {0 ;goto done;if (val->dtc_count[dtc] == CMN_DT_NUM_COUNTERS)goto done;int wp_idx, dtm = dn->dtm, sel = hw->filter_sel;if (val->dtm_count[dtm] == CMN_DTM_NUM_COUNTERS)goto done;if (sel > SEL_NONE && val->occupid[dtm][sel] &&1 )goto done;if (type != CMN_TYPE_WP)continue ;if (wp_idx < 0 )goto done;if (wp_idx & 1 &&1 ] != !!CMN_EVENT_WP_COMBINE(event))goto done;0 ;return ret;static enum cmn_filter_select arm_cmn_filter_sel(const struct arm_cmn *cmn,enum cmn_node_type type,unsigned int eventid)struct arm_cmn_event_attr *e;enum cmn_model model = arm_cmn_model(cmn);for (int i = 0 ; i < ARRAY_SIZE(arm_cmn_event_attrs) - 1 ; i++) {if (e->model & model && e->type == type && e->eventid == eventid)return e->fsel;return SEL_NONE;static int arm_cmn_event_init(struct perf_event *event)struct arm_cmn *cmn = to_cmn(event->pmu);struct arm_cmn_hw_event *hw = to_cmn_hw(event);struct arm_cmn_node *dn;enum cmn_node_type type;bool bynodeid;if (event->attr.type != event->pmu->type)return -ENOENT;if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)return -EINVAL;if (event->cpu < 0 )return -EINVAL;/* DTC events (i.e. cycles) already have everything they need */ if (type == CMN_TYPE_DTC)return arm_cmn_validate_group(cmn, event);/* For watchpoints we need the actual XP node here */ if (type == CMN_TYPE_WP) {/* ...and we need a "real" direction */ if (eventid != CMN_WP_UP && eventid != CMN_WP_DOWN)return -EINVAL;/* ...but the DTM may depend on which port we're watching */ if (cmn->multi_dtm)2 ;else if (type == CMN_TYPE_XP &&true ;else if (type == CMN_TYPE_RND) {/* Secretly permit this as an alias for "rnid" events */ /* This is sufficiently annoying to recalculate, so cache it */ if (!hw->dn)return -EINVAL;1 , sizeof (hw->dtc_idx));for (dn = hw->dn; dn->type == type; dn++) {if (bynodeid && dn->id != nodeid) {continue ;if (dn->dtc < 0 )0 , cmn->num_dtcs);else 0 ;if (bynodeid)break ;if (!hw->num_dns) {"invalid node 0x%x type 0x%x\n" , nodeid, type);return -EINVAL;return arm_cmn_validate_group(cmn, event);static void arm_cmn_event_clear(struct arm_cmn *cmn, struct perf_event *event,int i)struct arm_cmn_hw_event *hw = to_cmn_hw(event);enum cmn_node_type type = CMN_EVENT_TYPE(event);while (i--) {struct arm_cmn_dtm *dtm = &cmn->dtms[hw->dn[i].dtm] + hw->dtm_offset;unsigned int dtm_idx = arm_cmn_get_index(hw->dtm_idx, i);if (type == CMN_TYPE_WP) {int wp_idx = arm_cmn_get_assigned_wp_idx(event, hw, i);1 ;if (hw->filter_sel > SEL_NONE)0 , sizeof (hw->dtm_idx));0 , sizeof (hw->wp_idx));static int arm_cmn_event_add(struct perf_event *event, int flags)struct arm_cmn *cmn = to_cmn(event->pmu);struct arm_cmn_hw_event *hw = to_cmn_hw(event);struct arm_cmn_node *dn;enum cmn_node_type type = CMN_EVENT_TYPE(event);unsigned int input_sel, i = 0 ;if (type == CMN_TYPE_DTC) {while (cmn->dtc[i].cycles)if (++i == cmn->num_dtcs)return -ENOSPC;0 ] = i;if (flags & PERF_EF_START)0 );return 0 ;/* Grab the global counters first... */ if (cmn->part == PART_CMN600 && j > 0 ) {0 ];else {0 ;while (cmn->dtc[j].counters[idx])if (++idx == CMN_DT_NUM_COUNTERS)return -ENOSPC;/* ...then the local counters to feed them */ struct arm_cmn_dtm *dtm = &cmn->dtms[dn->dtm] + hw->dtm_offset;unsigned int dtm_idx, shift, d = max_t(int , dn->dtc, 0 );0 ;while (dtm->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))if (++dtm_idx == CMN_DTM_NUM_COUNTERS)goto free_dtms;if (type == CMN_TYPE_XP) {else if (type == CMN_TYPE_WP) {int tmp, wp_idx;if (wp_idx < 0 )goto free_dtms;1 ];if (tmp >= 0 && CMN_EVENT_WP_COMBINE(event) !=goto free_dtms;else {struct arm_cmn_nodeid nid = arm_cmn_nid(dn);if (cmn->multi_dtm)2 ;4 ) + (nid.dev << 2 );if (arm_cmn_set_event_sel_hi(dn, hw->filter_sel, CMN_EVENT_OCCUPID(event)))goto free_dtms;32 | dtm->pmu_config_low;/* Go go go! */ if (flags & PERF_EF_START)0 );return 0 ;return -ENOSPC;static void arm_cmn_event_del(struct perf_event *event, int flags)struct arm_cmn *cmn = to_cmn(event->pmu);struct arm_cmn_hw_event *hw = to_cmn_hw(event);enum cmn_node_type type = CMN_EVENT_TYPE(event);if (type == CMN_TYPE_DTC)0 ]].cycles = NULL;else /* * We stop the PMU for both add and read, to avoid skew across DTM counters. * In theory we could use snapshots to read without stopping, but then it * becomes a lot trickier to deal with overlow and racing against interrupts, * plus it seems they don't work properly on some hardware anyway :( static void arm_cmn_start_txn(struct pmu *pmu, unsigned int flags)static void arm_cmn_end_txn(struct pmu *pmu)static int arm_cmn_commit_txn(struct pmu *pmu)return 0 ;static void arm_cmn_migrate(struct arm_cmn *cmn, unsigned int cpu)unsigned int i;for (i = 0 ; i < cmn->num_dtcs; i++)static int arm_cmn_pmu_online_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)struct arm_cmn *cmn;int node;struct arm_cmn, cpuhp_node);if (cpu_to_node(cmn->cpu) != node && cpu_to_node(cpu) == node)return 0 ;static int arm_cmn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *cpuhp_node)struct arm_cmn *cmn;unsigned int target;int node;struct arm_cmn, cpuhp_node);if (cpu != cmn->cpu)return 0 ;if (target >= nr_cpu_ids)if (target < nr_cpu_ids)return 0 ;static irqreturn_t arm_cmn_handle_irq(int irq, void *dev_id)struct arm_cmn_dtc *dtc = dev_id;for (;;) {int i;for (i = 0 ; i < CMN_DT_NUM_COUNTERS; i++) {if (status & (1 U << i)) {if (WARN_ON(!dtc->counters[i]))continue ;16 ;if (status & (1 U << CMN_DT_NUM_COUNTERS)) {if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {if (!dtc->irq_friend)return ret;/* We can reasonably accommodate DTCs of the same CMN sharing IRQs */ static int arm_cmn_init_irqs(struct arm_cmn *cmn)int i, j, irq, err;for (i = 0 ; i < cmn->num_dtcs; i++) {for (j = i; j--; ) {if (cmn->dtc[j].irq == irq) {goto next;if (err)return err;if (err)return err;/* isn't C great? */ return 0 ;static void arm_cmn_init_dtm(struct arm_cmn_dtm *dtm, struct arm_cmn_node *xp, int idx)int i;for (i = 0 ; i < 4 ; i++) {1 ;0 , dtm->base + CMN_DTM_WPn_MASK(i));0 ULL, dtm->base + CMN_DTM_WPn_VAL(i));static int arm_cmn_init_dtc(struct arm_cmn *cmn, struct arm_cmn_node *dn, int idx)struct arm_cmn_dtc *dtc = cmn->dtc + idx;if (dtc->irq < 0 )return dtc->irq;0 , CMN_DT_PMCCNTR(dtc));0 x1ff, CMN_DT_PMOVSR_CLR(dtc));return 0 ;static int arm_cmn_node_cmp(const void *a, const void *b)const struct arm_cmn_node *dna = a, *dnb = b;int cmp;if (!cmp)return cmp;static int arm_cmn_init_dtcs(struct arm_cmn *cmn)struct arm_cmn_node *dn, *xp;int dtc_idx = 0 ;sizeof (cmn->dtc[0 ]), GFP_KERNEL);if (!cmn->dtc)return -ENOMEM;sizeof (cmn->dns[0 ]), arm_cmn_node_cmp, NULL);for (dn = cmn->dns; dn->type; dn++) {if (dn->type == CMN_TYPE_XP)continue ;if (cmn->multi_dtm)2 ;if (dn->type == CMN_TYPE_DTC) {int err = arm_cmn_init_dtc(cmn, dn, dtc_idx++);if (err)return err;/* To the PMU, RN-Ds don't add anything over RN-Is, so smoosh them together */ if (dn->type == CMN_TYPE_RND)/* We split the RN-I off already, so let the CCLA part match CCLA events */ if (dn->type == CMN_TYPE_CCLA_RNI)return 0 ;static unsigned int arm_cmn_dtc_domain(struct arm_cmn *cmn, void __iomem *xp_region)int offset = CMN_DTM_UNIT_INFO;if (cmn->part == PART_CMN650 || cmn->part == PART_CI700)return FIELD_GET(CMN_DTM_UNIT_INFO_DTC_DOMAIN, readl_relaxed(xp_region + offset));static void arm_cmn_init_node_info(struct arm_cmn *cmn, u32 offset, struct arm_cmn_node *node)int level;if (node->type == CMN_TYPE_CFG)0 ;else if (node->type == CMN_TYPE_XP)1 ;else 2 ;"node%*c%#06hx%*ctype:%-#6x id:%-4hd off:%#x\n" ,2 ) + 1 , ' ' , node->id, 5 - (level * 2 ), ' ' ,static enum cmn_node_type arm_cmn_subtype(enum cmn_node_type type)switch (type) {case CMN_TYPE_HNP:return CMN_TYPE_HNI;case CMN_TYPE_CCLA_RNI:return CMN_TYPE_RNI;default :return CMN_TYPE_INVALID;static int arm_cmn_discover(struct arm_cmn *cmn, unsigned int rgn_offset)void __iomem *cfg_region, __iomem *xp_region;struct arm_cmn_node cfg, *dn;struct arm_cmn_dtm *dtm;enum cmn_part part;int i, j;if (cfg.type != CMN_TYPE_CFG)return -ENODEV;8 ;if (cmn->part && cmn->part != part)"Firmware binding mismatch: expected part number 0x%x, found 0x%x\n" ,if (!arm_cmn_model(cmn))"Unknown part number: 0x%x\n" , part);/* * With the device isolation feature, if firmware has neglected to enable * an XP port then we risk locking up if we try to access anything behind * it; however we also have no way to tell from Non-Secure whether any * given port is disabled or not, so the only way to win is not to play... if (reg & CMN_INFO_DEVICE_ISO_ENABLE) {"Device isolation enabled, not continuing due to risk of lockup\n" );return -ENODEV;/* Pass 1: visit the XPs, enumerate their children */ for (i = 0 ; i < cmn->num_xps; i++) {8 );/* * Some nodes effectively have two separate types, which we'll handle * by creating one of each internally. For a (very) safe initial upper * bound, account for double the number of non-XP nodes. 2 - cmn->num_xps,sizeof (*dn), GFP_KERNEL);if (!dn)return -ENOMEM;/* Initial safe upper bound on DTMs for any possible mesh layout */ if (cmn->multi_dtm)1 ;sizeof (*dtm), GFP_KERNEL);if (!dtm)return -ENOMEM;/* Pass 2: now we can actually populate the nodes */ for (i = 0 ; i < cmn->num_xps; i++) {struct arm_cmn_node *xp = dn++;unsigned int xp_ports = 0 ;8 );/* * Thanks to the order in which XP logical IDs seem to be * assigned, we can handily infer the mesh X dimension by * looking out for the XP at (0,1) without needing to know * the exact node ID format, which we can later derive. if (xp->id == (1 << 3 ))if (cmn->part == PART_CMN600)1 ;else 0 );/* * Keeping track of connected ports will let us filter out * unnecessary XP events easily, and also infer the per-XP * part of the node ID format. for (int p = 0 ; p < CMN_MAX_PORTS; p++)if (arm_cmn_device_connect_info(cmn, xp, p))if (cmn->num_xps == 1 ) {3 ;2 ;else if (xp_ports > 0 x3) {2 ;1 ;else {1 ;2 ;if (cmn->multi_dtm && (xp_ports > 0 x3))1 );if (cmn->multi_dtm && (xp_ports > 0 xf))2 );for (j = 0 ; j < child_count; j++) {8 );/* * Don't even try to touch anything external, since in general * we haven't a clue how to power up arbitrary CHI requesters. * As of CMN-600r1 these could only be RN-SAMs or CXLAs, * neither of which have any PMU events anyway. * (Actually, CXLAs do seem to have grown some events in r1p2, * but they don't go to regular XP DTMs, and they depend on * secure configuration which we can't easily deal with) if (reg & CMN_CHILD_NODE_EXTERNAL) {"ignoring external node %llx\n" , reg);continue ;/* * AmpereOneX erratum AC04_MESH_1 makes some XPs report a bogus * child count larger than the number of valid child pointers. * A child offset of 0 can only occur on CMN-600; otherwise it * would imply the root node being its own grandchild, which * we can safely dismiss in general. if (reg == 0 && cmn->part != PART_CMN600) {"bogus child pointer?\n" );continue ;switch (dn->type) {case CMN_TYPE_DTC:break ;/* These guys have PMU events */ case CMN_TYPE_DVM:case CMN_TYPE_HNI:case CMN_TYPE_HNF:case CMN_TYPE_SBSX:case CMN_TYPE_RNI:case CMN_TYPE_RND:case CMN_TYPE_MTSX:case CMN_TYPE_CXRA:case CMN_TYPE_CXHA:case CMN_TYPE_CCRA:case CMN_TYPE_CCHA:case CMN_TYPE_HNS:break ;case CMN_TYPE_CCLA:break ;/* Nothing to see here */ case CMN_TYPE_MPAM_S:case CMN_TYPE_MPAM_NS:case CMN_TYPE_RNSAM:case CMN_TYPE_CXLA:case CMN_TYPE_HNS_MPAM_S:case CMN_TYPE_HNS_MPAM_NS:case CMN_TYPE_APB:break ;/* * Split "optimised" combination nodes into separate * types for the different event sets. Offsetting the * base address lets us handle the second pmu_event_sel * register via the normal mechanism later. case CMN_TYPE_HNP:case CMN_TYPE_CCLA_RNI:1 ] = dn[0 ];0 ].pmu_base += CMN_CCLA_PMU_EVENT_SEL;1 ].type = arm_cmn_subtype(dn->type);2 ;break ;/* Something has gone horribly wrong */ default :"invalid device node type: 0x%x\n" , dn->type);return -ENODEV;/* Correct for any nodes we added or skipped */ /* Cheeky +1 to help terminate pointer-based iteration later */ void *)(dn + 1 ) - (void *)cmn->dns;if (dn)void *)dtm - (void *)cmn->dtms;if (dtm)/* * If mesh_x wasn't set during discovery then we never saw * an XP at (0,1), thus we must have an Nx1 configuration. if (!cmn->mesh_x)/* 1x1 config plays havoc with XP event encodings */ if (cmn->num_xps == 1 )"1x1 config not fully supported, translate XP events manually\n" );"periph_id part 0x%03x revision %d\n" , cmn->part, cmn->rev);"mesh %dx%d, ID width %d, ports %6pbl%s\n" ,", multi-DTM" : "" );return 0 ;static int arm_cmn600_acpi_probe(struct platform_device *pdev, struct arm_cmn *cmn)struct resource *cfg, *root;0 );if (!cfg)return -EINVAL;1 );if (!root)return -EINVAL;if (!resource_contains(cfg, root))/* * Note that devm_ioremap_resource() is dumb and won't let the platform * device claim cfg when the ACPI companion device has already claimed * root within it. But since they *are* already both claimed in the * appropriate name, we don't really need to do it again here anyway. if (!cmn->base)return -ENOMEM;return root->start - cfg->start;static int arm_cmn600_of_probe(struct device_node *np)return of_property_read_u32(np, "arm,root-node" , &rootnode) ?: rootnode;static int arm_cmn_probe(struct platform_device *pdev)struct arm_cmn *cmn;const char *name;static atomic_t id;int err, rootnode, this_id;sizeof (*cmn), GFP_KERNEL);if (!cmn)return -ENOMEM;unsigned long )device_get_match_data(cmn->dev);0 , dev_to_node(cmn->dev));if (cmn->part == PART_CMN600 && has_acpi_companion(cmn->dev)) {else {0 ;0 );if (IS_ERR(cmn->base))return PTR_ERR(cmn->base);if (cmn->part == PART_CMN600)if (rootnode < 0 )return rootnode;if (err)return err;if (err)return err;if (err)return err;struct pmu) {"arm_cmn_%d" , this_id);if (!name)return -ENOMEM;if (err)return err;1 );if (err)else return err;static void arm_cmn_remove(struct platform_device *pdev)struct arm_cmn *cmn = platform_get_drvdata(pdev);0 , cmn->dtc[0 ].base + CMN_DT_DTC_CTL);#ifdef CONFIG_OFstatic const struct of_device_id arm_cmn_of_match[] = {"arm,cmn-600" , .data = (void *)PART_CMN600 },"arm,cmn-650" },"arm,cmn-700" },"arm,cmn-s3" },"arm,ci-700" },#endif #ifdef CONFIG_ACPIstatic const struct acpi_device_id arm_cmn_acpi_match[] = {"ARMHC600" , PART_CMN600 },"ARMHC650" },"ARMHC700" },"ARMHC003" },#endif static struct platform_driver arm_cmn_driver = {"arm-cmn" ,true ,static int __init arm_cmn_init(void )int ret;"perf/arm/cmn:online" ,if (ret < 0 )return ret;"arm-cmn" , NULL);if (ret) {return ret;static void __exit arm_cmn_exit(void )"Robin Murphy <robin.murphy@arm.com>" );"Arm CMN/CI interconnect PMU driver" );"GPL v2" );
Messung V0.5 in Prozent C=96 H=92 G=93
[Seitenstruktur0.50Druckenetwas mehr zur Ethik2026-06-08]
2026-08-25
