/** Copyright ( c ) 2016 , 2021 , Intel Corporation . All rights reserved . * * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER . * * This code is free software ; you can redistribute it and / or modify it * under the terms of the GNU General Public License version 2 only , as * published by the Free Software Foundation . * * This code is distributed in the hope that it will be useful , but WITHOUT * ANY WARRANTY ; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE . See the GNU General Public License * version 2 for more details ( a copy is included in the LICENSE file that * accompanied this code ) . * * You should have received a copy of the GNU General Public License version * 2 along with this work ; if not , write to the Free Software Foundation , * Inc . , 51 Franklin St , Fifth Floor , Boston , MA 02110 - 1301 USA . * * Please contact Oracle , 500 Oracle Parkway , Redwood Shores , CA 94065 USA * or visit www . oracle . com if you need additional information or have any * questions . * #include "precompiled.hpp" #include "asm/assembler.hpp" #include "asm/assembler.inline.hpp" #include "runtime/stubRoutines.hpp" #include "macroAssembler_x86.hpp" // ofs and limit are used for multi-block byte array. // int com.sun.security.provider.DigestBase.implCompressMultiBlock(byte[] b, int ofs, int limit) void MacroAssembler::fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block) {0 ));16 ), 3 );// 0xFFFFFFFF000000000000000000000000 0 x1B);//0x000102030405060708090a0b0c0d0e0f // Save hash values for addition after rounds 0 ), e0);16 ), abcd);// Rounds 0 - 3 0 ));0 );// Rounds 4 - 7 16 ));0 );// Rounds 8 - 11 32 ));0 );// Rounds 12 - 15 48 ));0 );// Rounds 16 - 19 0 );// Rounds 20 - 23 1 );// Rounds 24 - 27 1 );// Rounds 28 - 31 1 );// Rounds 32 - 35 1 );// Rounds 36 - 39 1 );// Rounds 40 - 43 2 );// Rounds 44 - 47 2 );// Rounds 48 - 51 2 );// Rounds 52 - 55 2 );// Rounds 56 - 59 2 );// Rounds 60 - 63 3 );// Rounds 64 - 67 3 );// Rounds 68 - 71 3 );// Rounds 72 - 75 3 );// Rounds 76 - 79 3 );// add current hash values with previously saved 0 ));16 ));if (multi_block) {// increment data pointer and loop if more to process 64 );64 );//return ofs // write hash values back in the correct order 0 x1b);0 ), abcd);16 ), e0, 3 );// xmm0 (msg) is used as an implicit argument to sh256rnds2 // and state0 and state1 can never use xmm0 register. // ofs and limit are used for multi-block byte array. // int com.sun.security.provider.DigestBase.implCompressMultiBlock(byte[] b, int ofs, int limit) #ifdef _LP64void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,Register buf, Register state, Register ofs, Register limit, Register rsp,bool multi_block, XMMRegister shuf_mask) {#else void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,Register buf, Register state, Register ofs, Register limit, Register rsp,bool multi_block) {#endif ;0 ));16 ));0 xB1);0 x1B);8 );0 xF0);#ifdef _LP64#endif 0 ), state0);16 ), state1);// Rounds 0-3 0 ));#ifdef _LP64#else #endif 0 ));0 x0E);// Rounds 4-7 16 ));#ifdef _LP64#else #endif 16 ));0 x0E);// Rounds 8-11 32 ));#ifdef _LP64#else #endif 32 ));0 x0E);// Rounds 12-15 48 ));#ifdef _LP64#else #endif 48 ));4 );0 x0E);// Rounds 16-19 64 ));4 );0 x0E);// Rounds 20-23 80 ));4 );0 x0E);// Rounds 24-27 96 ));4 );0 x0E);// Rounds 28-31 112 ));4 );0 x0E);// Rounds 32-35 128 ));4 );0 x0E);// Rounds 36-39 144 ));4 );0 x0E);// Rounds 40-43 160 ));4 );0 x0E);// Rounds 44-47 176 ));4 );0 x0E);// Rounds 48-51 192 ));4 );0 x0E);// Rounds 52-55 208 ));4 );0 x0E);// Rounds 56-59 224 ));4 );0 x0E);// Rounds 60-63 240 ));0 x0E);0 ));16 ));if (multi_block) {// increment data pointer and loop if more to process 64 );64 );//return ofs 0 x1B);0 xB1);0 xF0);8 );0 ), state0);16 ), state1);#ifdef _LP64/* The algorithm below is based on Intel publication : " Fast SHA - 256 Implementations on Intel ë Architecture Processors " by Jim Guilford , Kirk Yap and Vinodh Gopal . The assembly code was originally provided by Sean Gulley and in many places preserves the original assembly NAMES and comments to simplify matching Java assembly with its original . The Java version was substantially redesigned to replace 1200 assembly instruction with much shorter run - time generator of the same code in memory . void MacroAssembler::sha256_AVX2_one_round_compute(Register reg_old_h,Register reg_a,Register reg_b,Register reg_c,Register reg_d,Register reg_e,Register reg_f,Register reg_g,Register reg_h,int iter) {const Register & reg_y0 = r13;const Register & reg_y1 = r14;const Register & reg_y2 = r15;const Register & reg_y3 = rcx;const Register & reg_T1 = r12;//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; RND iter ;;;;;;;;;;;;;;;;;;;;;;;;;;; if (iter%4 > 0 ) {// reg_h = k + w + reg_h + S0 + S1 + CH = t1 + S0; -- // reg_y2 = reg_f ; CH 25 ); // reg_y0 = reg_e >> 25 ; S1A 11 ); // reg_y1 = reg_e >> 11 ; S1B // reg_y2 = reg_f^reg_g ; CH // reg_y0 = (reg_e>>25) ^ (reg_h>>11) ; S1 6 ); // reg_y1 = (reg_e >> 6) ; S1 // reg_y2 = (reg_f^reg_g)®_e ; CH if (iter%4 > 0 ) {// reg_h = t1 + S0 + MAJ ; -- // reg_y0 = (reg_e>>25) ^ (reg_e>>11) ^ (reg_e>>6) ; S1 13 ); // reg_T1 = reg_a >> 13 ; S0B // reg_y2 = CH = ((reg_f^reg_g)®_e)^reg_g ; CH 22 ); // reg_y1 = reg_a >> 22 ; S0A // reg_y3 = reg_a ; MAJA // reg_y1 = (reg_a>>22) ^ (reg_a>>13) ; S0 2 ); // reg_T1 = (reg_a >> 2) ; S0 4 *iter)); // reg_h = k + w + reg_h ; -- // reg_y3 = reg_a|reg_c ; MAJA // reg_y1 = (reg_a>>22) ^ (reg_a>>13) ^ (reg_a>>2) ; S0 // reg_T1 = reg_a ; MAJB // reg_y3 = (reg_a|reg_c)®_b ; MAJA // reg_T1 = reg_a®_c ; MAJB // reg_y2 = S1 + CH ; -- // reg_d = k + w + reg_h + reg_d ; -- // reg_y3 = MAJ = (reg_a|reg_c)®_b)|(reg_a®_c) ; MAJ // reg_h = k + w + reg_h + S0 ; -- // reg_d = k + w + reg_h + reg_d + S1 + CH = reg_d + t1 ; -- if (iter%4 == 3 ) {// reg_h = k + w + reg_h + S0 + S1 + CH = t1 + S0; -- // reg_h = t1 + S0 + MAJ ; -- void MacroAssembler::sha256_AVX2_four_rounds_compute_first(int start) {0 );1 );2 );3 );void MacroAssembler::sha256_AVX2_four_rounds_compute_last(int start) {0 );1 );2 );3 );void MacroAssembler::sha256_AVX2_one_round_and_sched(/* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */ /* ymm5 */ /* full cycle is 16 iterations */ /* ymm6 */ /* ymm7 */ Register reg_a, /* == rax on 0 iteration, then rotate 8 register right on each next iteration */ Register reg_b, /* rbx */ /* full cycle is 8 iterations */ Register reg_c, /* rdi */ Register reg_d, /* rsi */ Register reg_e, /* r8 */ Register reg_f, /* r9d */ Register reg_g, /* r10d */ Register reg_h, /* r11d */ int iter)// rcx = reg_a ; MAJA 25 ); // r13 = reg_e >> 25 ; S1A 11 ); // r14 = reg_e >> 11 ; S1B 4 *iter));// rcx = reg_a|reg_c ; MAJA // r15 = reg_f ; CH 13 ); // r12 = reg_a >> 13 ; S0B // r13 = (reg_e>>25) ^ (reg_e>>11) ; S1 // r15 = reg_f^reg_g ; CH 6 ); // r14 = (reg_e >> 6) ; S1 // r15 = (reg_f^reg_g)®_e ; CH // r13 = (reg_e>>25) ^ (reg_e>>11) ^ (reg_e>>6) ; S1 22 ); // r14 = reg_a >> 22 ; S0A // reg_d = k + w + reg_h + reg_d ; -- // rcx = (reg_a|reg_c)®_b ; MAJA // r14 = (reg_a>>22) ^ (reg_a>>13) ; S0 2 ); // r12 = (reg_a >> 2) ; S0 // r15 = CH = ((reg_f^reg_g)®_e)^reg_g ; CH // r14 = (reg_a>>22) ^ (reg_a>>13) ^ (reg_a>>2) ; S0 // r12 = reg_a ; MAJB // r12 = reg_a®_c ; MAJB // r15 = S1 + CH ; -- // rcx = MAJ = (reg_a|reg_c)®_b)|(reg_a®_c) ; MAJ // reg_h = k + w + reg_h + S0 ; -- // reg_d = k + w + reg_h + reg_d + S1 + CH = reg_d + t1 ; -- // reg_h = k + w + reg_h + S0 + S1 + CH = t1 + S0; -- // reg_h = t1 + S0 + MAJ ; -- if (iter%4 == 0 ) {4 , AVX_256bit); // ymm0 = W[-7] // ymm0 = W[-7] + W[-16]; y1 = (e >> 6) ; S1 4 , AVX_256bit); // ymm1 = W[-15] 7 , AVX_256bit);32 -7 , AVX_256bit);// ymm3 = W[-15] ror 7 18 , AVX_256bit);else if (iter%4 == 1 ) {3 , AVX_256bit); // ymm8 = W[-15] >> 3 32 -18 , AVX_256bit);// ymm3 = W[-15] ror 7 ^ W[-15] ror 18 // ymm1 = s0 0 xFA, AVX_256bit); // 11111010b ; ymm2 = W[-2] {BBAA} // ymm0 = W[-16] + W[-7] + s0 10 , AVX_256bit); // ymm8 = W[-2] >> 10 {BBAA} else if (iter%4 == 2 ) {19 , AVX_256bit); // ymm3 = W[-2] ror 19 {xBxA} 17 , AVX_256bit); // ymm2 = W[-2] ror 17 {xBxA} // ymm8 = s1 {xBxA} // ymm8 = s1 {00BA} // ymm0 = {..., ..., W[1], W[0]} 0 x50, AVX_256bit); // 01010000b ; ymm2 = W[-2] {DDCC} else if (iter%4 == 3 ) {10 , AVX_256bit); // ymm11 = W[-2] >> 10 {DDCC} 19 , AVX_256bit); // ymm3 = W[-2] ror 19 {xDxC} 17 , AVX_256bit); // ymm2 = W[-2] ror 17 {xDxC} // ymm11 = s1 {xDxC} // ymm11 = s1 {DC00} // xmm_0 = {W[3], W[2], W[1], W[0]} void MacroAssembler::addm(int disp, Register r1, Register r2) {void MacroAssembler::addmq(int disp, Register r1, Register r2) {void MacroAssembler::sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,Register buf, Register state, Register ofs, Register limit, Register rsp,bool multi_block, XMMRegister shuf_mask) {;0 ;const XMMRegister& SHUF_00BA = xmm10; // ymm10: shuffle xBxA -> 00BA const XMMRegister& SHUF_DC00 = xmm12; // ymm12: shuffle xDxC -> DC00 const XMMRegister& BYTE_FLIP_MASK = xmm13; // ymm13 const XMMRegister& X_BYTE_FLIP_MASK = xmm13; //XMM version of BYTE_FLIP_MASK const Register & NUM_BLKS = r8; // 3rd arg const Register & CTX = rdx; // 2nd arg const Register & INP = rcx; // 1st arg const Register & c = rdi;const Register & d = rsi;const Register & e = r8; // clobbers NUM_BLKS const Register & y3 = rcx; // clobbers INP const Register & TBL = rbp;const Register & SRND = CTX; // SRND is same register as CTX const Register & a = rax;const Register & b = rbx;const Register & f = r9;const Register & g = r10;const Register & h = r11;const Register & T1 = r12;const Register & y0 = r13;const Register & y1 = r14;const Register & y2 = r15;enum {2 *64 *4 , // 2 blocks, 64 rounds, 4 bytes/round 8 ,8 ,8 ,8 ,0 ,#ifndef _WIN64// linux: this is limit, need at the end // linux: this is ofs #else // win64: this is ofs // win64: this is limit, we need them again at the very and #endif #ifdef _WIN64#endif 32 );#ifndef _WIN64// copy linux params to win64 params, therefore the rest of code will be the same for both #endif // setting original assembly ABI /** message to encrypt in INP */ 0 )); // rcx == message (buf) ;; linux: INP = buf = rdi /** digest in CTX */ // rdx = digest (state) ;; linux: CTX = state = rsi /** NUM_BLK is the length of message, need to set it from ofs and limit */ if (multi_block) {// Win64: cannot directly update NUM_BLKS, since NUM_BLKS = ofs = r8 // on entry r8 = ofs // on exit r8 = NUM_BLKS // assume the original ofs <= limit ;; linux: cmp rcx, rdx 64 ); //;; linux: ofs = rdx 64 );// NUM_BLK (r8) ;; linux: NUM_BLK = rdx 0 );else {64 );//if (!multi_block) 64 )); // pointer to the last block // //cmp INP, NUM_BLKS //je only_one_block // load initial digest 4 *0 ));4 *1 ));4 *2 ));4 *3 ));4 *4 ));4 *5 ));// load g - r10 after it is used as scratch 4 *7 ));0 )); // [PSHUFFLE_BYTE_FLIP_MASK wrt rip] 32 )); // [_SHUF_00BA wrt rip] 64 )); // [_SHUF_DC00 wrt rip] 4 *6 ));// store // assume buffers not aligned // Load first 16 dwords from two blocks 0 *32 ));1 *32 ));2 *32 ));3 *32 ));// byte swap data // transpose data into high/low halves 0 x20);0 x31);0 x20);0 x31);64 );//;; schedule 48 input dwords, by doing 3 rounds of 12 each 16 );0 *32 ), AVX_256bit);0 *32 ), xmm9);1, 0 );0, 1 );9, 2 );8, 3 );1 *32 ), AVX_256bit);1 *32 ), xmm9);i, 8 +0 );i, 8 +1 );x, 8 +2 );x, 8 +3 );2 *32 ), AVX_256bit);2 *32 ), xmm9);1, 16 +0 );0, 16 +1 );9, 16 +2 );8, 16 +3 );3 *32 ), AVX_256bit);3 *32 ), xmm9);i, 24 +0 );i, 24 +1 );x, 24 +2 );x, 24 +3 );4 *32 );3 * 4 *32 );// Do last 16 rounds with no scheduling 0 *32 ), AVX_256bit);0 *32 ), xmm9);0 );1 *32 ), AVX_256bit);1 *32 ), xmm9);0 + 8 );2 *32 );4 * 4 *32 );4 *0 , CTX, a);4 *1 , CTX, b);4 *2 , CTX, c);4 *3 , CTX, d);4 *4 , CTX, e);4 *5 , CTX, f);4 *6 , CTX, g);4 *7 , CTX, h);//Do second block using previously scheduled results 16 );4 );4 +8 );2 *32 );4 * 4 *32 );64 );4 *0 , CTX, a);4 *1 , CTX, b);4 *2 , CTX, c);4 *3 , CTX, d);4 *4 , CTX, e);4 *5 , CTX, f);4 *6 , CTX, g);4 *7 , CTX, h);0 *16 ));1 *16 ));2 *16 ));3 *16 ));// load initial digest ;; table should be preloaded with following values 4 *0 )); // 0x6a09e667 4 *1 )); // 0xbb67ae85 4 *2 )); // 0x3c6ef372 4 *3 )); // 0xa54ff53a 4 *4 )); // 0x510e527f 4 *5 )); // 0x9b05688c // load g - r10 after use as scratch 4 *7 )); // 0x5be0cd19 0 )); // [PSHUFFLE_BYTE_FLIP_MASK wrt rip] 32 )); // [_SHUF_00BA wrt rip] 64 )); // [_SHUF_DC00 wrt rip] 4 *6 )); // 0x1f83d9ab #ifdef _WIN64#endif #ifdef _WIN64#else #endif if (multi_block) {#ifdef _WIN64const Register & limit_end = r9;const Register & ofs_end = r8;#else const Register & limit_end = rcx;const Register & ofs_end = rdx;#endif // assume the original ofs <= limit 64 );void MacroAssembler::sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c,Register d, Register e, Register f, Register g, Register h,int iteration)const Register & y0 = r13;const Register & y1 = r14;const Register & y2 = r15;#ifdef _WIN64const Register & y3 = rcx;#else const Register & y3 = rdi;#endif const Register & T1 = r12;if (iteration % 4 > 0 ) {//h = k + w + h + S0 + S1 + CH = t1 + S0; //y2 = f; CH 41 ); //y0 = e >> 41; S1A 18 ); //y1 = e >> 18; S1B //y2 = f^g; CH //y0 = (e >> 41) ^ (e >> 18); S1 14 ); //y1 = (e >> 14); S1 //y2 = (f^g)&e; CH if (iteration % 4 > 0 ) {//h = t1 + S0 + MAJ //y0 = (e >> 41) ^ (e >> 18) ^ (e >> 14); S1 34 ); //T1 = a >> 34; S0B //y2 = CH = ((f^g)&e) ^g; CH 39 ); //y1 = a >> 39; S0A //y3 = a; MAJA //y1 = (a >> 39) ^ (a >> 34); S0 28 ); //T1 = (a >> 28); S0 8 * iteration))); //h = k + w + h; -- //y3 = a | c; MAJA //y1 = (a >> 39) ^ (a >> 34) ^ (a >> 28); S0 //T1 = a; MAJB //y3 = (a | c)&b; MAJA //T1 = a&c; MAJB //y2 = S1 + CH; -- //d = k + w + h + d; -- //y3 = MAJ = (a | c)&b) | (a&c); MAJ //h = k + w + h + S0; -- //d = k + w + h + d + S1 + CH = d + t1; -- if (iteration % 4 == 3 ) {//h = k + w + h + S0 + S1 + CH = t1 + S0; -- //h = t1 + S0 + MAJ; -- void MacroAssembler::sha512_AVX2_one_round_and_schedule(// ymm4 // ymm5 // ymm6 // ymm7 Register a, //rax Register b, //rbx Register c, //rdi Register d, //rsi Register e, //r8 Register f, //r9 Register g, //r10 Register h, //r11 int iteration)const Register & y0 = r13;const Register & y1 = r14;const Register & y2 = r15;#ifdef _WIN64const Register & y3 = rcx;#else const Register & y3 = rdi;#endif const Register & T1 = r12;if (iteration % 4 == 0 ) {// Extract w[t - 7] // xmm0 = W[-7] 3 );8 , AVX_256bit);// Calculate w[t - 16] + w[t - 7] //xmm0 = W[-7] + W[-16] // Extract w[t - 15] //xmm1 = W[-15] 3 );8 , AVX_256bit);// Calculate sigma0 // Calculate w[t - 15] ror 1 1 , AVX_256bit);64 - 1 ), AVX_256bit);//xmm3 = W[-15] ror 1 // Calculate w[t - 15] shr 7 7 , AVX_256bit); //xmm8 = W[-15] >> 7 else if (iteration % 4 == 1 ) {//Calculate w[t - 15] ror 8 8 , AVX_256bit);64 - 8 ), AVX_256bit);//xmm1 = W[-15] ror 8 //XOR the three components //xmm3 = W[-15] ror 1 ^ W[-15] >> 7 //xmm1 = s0 //Add three components, w[t - 16], w[t - 7] and sigma0 //xmm0 = W[-16] + W[-7] + s0 // Move to appropriate lanes for calculating w[16] and w[17] 0 ); //xmm4 = W[-16] + W[-7] + s0{ BABA } //Move to appropriate lanes for calculating w[18] and w[19] //xmm0 = W[-16] + W[-7] + s0{ DC00 } //Calculate w[16] and w[17] in both 128 bit lanes //Calculate sigma1 for w[16] and w[17] on both 128 bit lanes 17 ); //xmm2 = W[-2] {BABA} 6 , AVX_256bit); //xmm8 = W[-2] >> 6 {BABA} else if (iteration % 4 == 2 ) {19 , AVX_256bit); //xmm3 = W[-2] >> 19 {BABA} 64 - 19 ), AVX_256bit); //xmm1 = W[-2] << 19 {BABA} //xmm3 = W[-2] ror 19 {BABA} // xmm8 = W[-2] ror 19 ^ W[-2] >> 6 {BABA} 61 , AVX_256bit); //xmm3 = W[-2] >> 61 {BABA} 64 - 61 ), AVX_256bit); //xmm1 = W[-2] << 61 {BABA} //xmm3 = W[-2] ror 61 {BABA} //xmm8 = s1 = (W[-2] ror 19) ^ (W[-2] ror 61) ^ (W[-2] >> 6) { BABA } //Add sigma1 to the other components to get w[16] and w[17] //xmm4 = { W[1], W[0], W[1], W[0] } //Calculate sigma1 for w[18] and w[19] for upper 128 bit lane 6 , AVX_256bit); //xmm8 = W[-2] >> 6 {DC--} else if (iteration % 4 == 3 ){19 , AVX_256bit); //xmm3 = W[-2] >> 19 {DC--} 64 - 19 ), AVX_256bit); //xmm1 = W[-2] << 19 {DC--} //xmm3 = W[-2] ror 19 {DC--} //xmm8 = W[-2] ror 19 ^ W[-2] >> 6 {DC--} 61 , AVX_256bit); //xmm3 = W[-2] >> 61 {DC--} 64 - 61 ), AVX_256bit); //xmm1 = W[-2] << 61 {DC--} //xmm3 = W[-2] ror 61 {DC--} //xmm8 = s1 = (W[-2] ror 19) ^ (W[-2] ror 61) ^ (W[-2] >> 6) { DC-- } //Add the sigma0 + w[t - 7] + w[t - 16] for w[18] and w[19] to newly calculated sigma1 to get w[18] and w[19] //xmm2 = { W[3], W[2], --, -- } //Form w[19, w[18], w17], w[16] 0 xF0, AVX_256bit); //xmm4 = { W[3], W[2], W[1], W[0] } //y3 = a; MAJA 41 ); // y0 = e >> 41; S1A 18 ); //y1 = e >> 18; S1B 8 ))); //h = k + w + h; -- //y3 = a | c; MAJA //y2 = f; CH //y2 = f^g; CH 34 ); //T1 = a >> 34; S0B //y0 = (e >> 41) ^ (e >> 18); S1 14 ); //y1 = (e >> 14); S1 //y2 = (f^g) & e; CH //d = k + w + h + d; -- //y3 = (a | c)&b; MAJA //y0 = (e >> 41) ^ (e >> 18) ^ (e >> 14); S1 39 ); //y1 = a >> 39; S0A //y1 = (a >> 39) ^ (a >> 34); S0 28 ); //T1 = (a >> 28); S0 //y2 = CH = ((f^g)&e) ^ g; CH //y1 = (a >> 39) ^ (a >> 34) ^ (a >> 28); S0 //T1 = a; MAJB //T1 = a&c; MAJB //y2 = S1 + CH; -- //y3 = MAJ = (a | c)&b) | (a&c); MAJ //h = k + w + h + S0; -- //d = k + w + h + d + S1 + CH = d + t1; -- //h = k + w + h + S0 + S1 + CH = t1 + S0; -- //h = t1 + S0 + MAJ; -- void MacroAssembler::sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,Register buf, Register state, Register ofs, Register limit, Register rsp,bool multi_block, XMMRegister shuf_mask)_addr_sha512();0 ;const XMMRegister& XFER = xmm0; // YTMP0 const XMMRegister& BYTE_FLIP_MASK = xmm9; // ymm9 const XMMRegister& YMM_MASK_LO = xmm10; // ymm10 #ifdef _WIN64const Register & INP = rcx; //1st arg const Register & CTX = rdx; //2nd arg const Register & NUM_BLKS = r8; //3rd arg const Register & c = rdi;const Register & d = rsi;const Register & e = r8;const Register & y3 = rcx;const Register & offset = r8;const Register & input_limit = r9;#else const Register & INP = rdi; //1st arg const Register & CTX = rsi; //2nd arg const Register & NUM_BLKS = rdx; //3rd arg const Register & c = rcx;const Register & d = r8;const Register & e = rdx;const Register & y3 = rdi;const Register & offset = rdx;const Register & input_limit = rcx;#endif const Register & TBL = rbp;const Register & a = rax;const Register & b = rbx;const Register & f = r9;const Register & g = r10;const Register & h = r11;//Local variables as defined in assembly file. enum 4 * 8 , // resq 4 => reserve 4 quadwords. Hence 4 * 8 8 , // resq 1 8 ,8 ,8 , // defined as resq 1 #ifdef _WIN648 * 8 , // defined as resq 8 #else 6 * 8 // resq 6 #endif enum 0 ,// 32 // 40 // 48 // 56 // 64 // 128 for windows and 112 for linux. //Saving offset and limit as it will help with blocksize calculation for multiblock SHA512. #ifdef _WIN64// win64: this is ofs // win64: this is limit, we need them again at the very end. #else // linux : this is ofs, need at the end for multiblock calculation // linux: This is the limit. #endif //Allocate Stack Space 32 );//Save GPRs 8 )), rbx);16 )), r12);24 )), r13);32 )), r14);40 )), r15);#ifdef _WIN6448 )), rsi);56 )), rdi);#endif 0 xF0, AVX_128bit);0 xF0, AVX_256bit);if (multi_block) {// Assuming that offset is less than limit. 128 );128 );0 );else {//If single block. 128 );//pointer to end of data //load initial digest 8 * 0 ));8 * 1 ));8 * 2 ));8 * 3 ));8 * 4 ));8 * 5 ));// load g - r10 after it is used as scratch 8 * 7 ));0 )); // PSHUFFLE_BYTE_FLIP_MASK wrt rip 32 ));8 * 6 ));//byte swap first 16 dwords 32 * 0 ));32 * 1 ));32 * 2 ));32 * 3 ));4 );16 );//Schedule 64 input dwords, by calling sha512_AVX2_one_round_and_schedule 0 * 32 ), AVX_256bit);//four rounds and schedule 0 );1 );2 );3 );1 * 32 ), AVX_256bit);//four rounds and schedule 0 );1 );2 );3 );2 * 32 ), AVX_256bit);//four rounds and schedule 0 );1 );2 );3 );3 * 32 ), AVX_256bit);4 * 32 );//four rounds and schedule 0 );1 );2 );3 );1 );2 );0 * 32 ), AVX_256bit);//four rounds and compute. 0 );1 );2 );3 );1 * 32 ), AVX_256bit);2 * 32 );// four rounds and compute. 0 );1 );2 );3 );1 );8 * 0 , CTX, a);8 * 1 , CTX, b);8 * 2 , CTX, c);8 * 3 , CTX, d);8 * 4 , CTX, e);8 * 5 , CTX, f);8 * 6 , CTX, g);8 * 7 , CTX, h);128 );//Restore GPRs 0 )));8 )));16 )));24 )));32 )));40 )));#ifdef _WIN6448 )));56 )));#endif //Restore Stack Pointer #ifdef _WIN64#else #endif if (multi_block) {#ifdef _WIN64const Register & limit_end = r9;const Register & ofs_end = r8;#else const Register & limit_end = rcx;const Register & ofs_end = rdx;#endif 128 );#endif //#ifdef _LP64
Messung V0.5 in Prozent C=85 H=97 G=91
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