/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*-
* vim: set ts=8 sts=2 et sw=2 tw=80: */
// Copyright 2011 the V8 project authors. All rights reserved.
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
// * Neither the name of Google Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include "jit/mips64/Simulator-mips64.h"
#include "mozilla/Casting.h"
#include "mozilla/FloatingPoint.h"
#include "mozilla/IntegerPrintfMacros.h"
#include "mozilla/Likely.h"
#include "mozilla/MathAlgorithms.h"
#include <
float.h>
#include <limits>
#include "jit/AtomicOperations.h"
#include "jit/mips64/Assembler-mips64.h"
#include "js/Conversions.h"
#include "js/UniquePtr.h"
#include "js/Utility.h"
#include "threading/LockGuard.h"
#include "vm/JSContext.h"
#include "vm/Runtime.h"
#include "wasm/WasmInstance.h"
#include "wasm/WasmSignalHandlers.h"
#define I8(v)
static_cast<int8_t>(v)
#define I16(v)
static_cast<int16_t>(v)
#define U16(v)
static_cast<uint16_t>(v)
#define I32(v)
static_cast<int32_t>(v)
#define U32(v)
static_cast<uint32_t>(v)
#define I64(v)
static_cast<int64_t>(v)
#define U64(v)
static_cast<uint64_t>(v)
#define I128(v)
static_cast<__int128_t>(v)
#define U128(v)
static_cast<__uint128_t>(v)
#define I32_CHECK(v) \
({ \
MOZ_ASSERT(I64(I32(v)) == I64(v)); \
I32((v)); \
})
namespace js {
namespace jit {
static const Instr kCallRedirInstr =
op_special | MAX_BREAK_CODE << FunctionBits | ff_break;
// Utils functions.
static uint32_t GetFCSRConditionBit(uint32_t cc) {
if (cc == 0) {
return 23;
}
return 24 + cc;
}
// -----------------------------------------------------------------------------
// MIPS assembly various constants.
class SimInstruction {
public:
enum {
kInstrSize = 4,
// On MIPS PC cannot actually be directly accessed. We behave as if PC was
// always the value of the current instruction being executed.
kPCReadOffset = 0
};
// Get the raw instruction bits.
inline Instr instructionBits()
const {
return *
reinterpret_cast<
const Instr*>(
this);
}
// Set the raw instruction bits to value.
inline void setInstructionBits(Instr value) {
*
reinterpret_cast<Instr*>(
this) = value;
}
// Read one particular bit out of the instruction bits.
inline int bit(
int nr)
const {
return (instructionBits() >> nr) & 1; }
// Read a bit field out of the instruction bits.
inline int bits(
int hi,
int lo)
const {
return (instructionBits() >> lo) & ((2 << (hi - lo)) - 1);
}
// Instruction type.
enum Type { kRegisterType, kImmediateType, kJumpType, kUnsupported = -1 };
// Get the encoding type of the instruction.
Type instructionType()
const;
// Accessors for the different named fields used in the MIPS encoding.
inline OpcodeField opcodeValue()
const {
return static_cast<OpcodeField>(
bits(OpcodeShift + OpcodeBits - 1, OpcodeShift));
}
inline int rsValue()
const {
MOZ_ASSERT(instructionType() == kRegisterType ||
instructionType() == kImmediateType);
return bits(RSShift + RSBits - 1, RSShift);
}
inline int rtValue()
const {
MOZ_ASSERT(instructionType() == kRegisterType ||
instructionType() == kImmediateType);
return bits(RTShift + RTBits - 1, RTShift);
}
inline int rdValue()
const {
MOZ_ASSERT(instructionType() == kRegisterType);
return bits(RDShift + RDBits - 1, RDShift);
}
inline int saValue()
const {
MOZ_ASSERT(instructionType() == kRegisterType);
return bits(SAShift + SABits - 1, SAShift);
}
inline int functionValue()
const {
MOZ_ASSERT(instructionType() == kRegisterType ||
instructionType() == kImmediateType);
return bits(FunctionShift + FunctionBits - 1, FunctionShift);
}
inline int fdValue()
const {
return bits(FDShift + FDBits - 1, FDShift); }
inline int fsValue()
const {
return bits(FSShift + FSBits - 1, FSShift); }
inline int ftValue()
const {
return bits(FTShift + FTBits - 1, FTShift); }
inline int frValue()
const {
return bits(FRShift + FRBits - 1, FRShift); }
// Float Compare condition code instruction bits.
inline int fcccValue()
const {
return bits(FCccShift + FCccBits - 1, FCccShift);
}
// Float Branch condition code instruction bits.
inline int fbccValue()
const {
return bits(FBccShift + FBccBits - 1, FBccShift);
}
// Float Branch true/false instruction bit.
inline int fbtrueValue()
const {
return bits(FBtrueShift + FBtrueBits - 1, FBtrueShift);
}
// Return the fields at their original place in the instruction encoding.
inline OpcodeField opcodeFieldRaw()
const {
return static_cast<OpcodeField>(instructionBits() & OpcodeMask);
}
inline int rsFieldRaw()
const {
MOZ_ASSERT(instructionType() == kRegisterType ||
instructionType() == kImmediateType);
return instructionBits() & RSMask;
}
// Same as above function, but safe to call within instructionType().
inline int rsFieldRawNoAssert()
const {
return instructionBits() & RSMask; }
inline int rtFieldRaw()
const {
MOZ_ASSERT(instructionType() == kRegisterType ||
instructionType() == kImmediateType);
return instructionBits() & RTMask;
}
inline int rdFieldRaw()
const {
MOZ_ASSERT(instructionType() == kRegisterType);
return instructionBits() & RDMask;
}
inline int saFieldRaw()
const {
MOZ_ASSERT(instructionType() == kRegisterType);
return instructionBits() & SAMask;
}
inline int functionFieldRaw()
const {
return instructionBits() & FunctionMask;
}
// Get the secondary field according to the opcode.
inline int secondaryValue()
const {
OpcodeField op = opcodeFieldRaw();
switch (op) {
case op_special:
case op_special2:
return functionValue();
case op_cop1:
return rsValue();
case op_regimm:
return rtValue();
default:
return ff_null;
}
}
inline int32_t imm16Value()
const {
MOZ_ASSERT(instructionType() == kImmediateType);
return bits(Imm16Shift + Imm16Bits - 1, Imm16Shift);
}
inline int32_t imm26Value()
const {
MOZ_ASSERT(instructionType() == kJumpType);
return bits(Imm26Shift + Imm26Bits - 1, Imm26Shift);
}
// Say if the instruction should not be used in a branch delay slot.
bool isForbiddenInBranchDelay()
const;
// Say if the instruction 'links'. e.g. jal, bal.
bool isLinkingInstruction()
const;
// Say if the instruction is a debugger break/trap.
bool isTrap()
const;
private:
SimInstruction() =
delete;
SimInstruction(
const SimInstruction& other) =
delete;
void operator=(
const SimInstruction& other) =
delete;
};
bool SimInstruction::isForbiddenInBranchDelay()
const {
const int op = opcodeFieldRaw();
switch (op) {
case op_j:
case op_jal:
case op_beq:
case op_bne:
case op_blez:
case op_bgtz:
case op_beql:
case op_bnel:
case op_blezl:
case op_bgtzl:
return true;
case op_regimm:
switch (rtFieldRaw()) {
case rt_bltz:
case rt_bgez:
case rt_bltzal:
case rt_bgezal:
return true;
default:
return false;
};
break;
case op_special:
switch (functionFieldRaw()) {
case ff_jr:
case ff_jalr:
return true;
default:
return false;
};
break;
default:
return false;
};
}
bool SimInstruction::isLinkingInstruction()
const {
const int op = opcodeFieldRaw();
switch (op) {
case op_jal:
return true;
case op_regimm:
switch (rtFieldRaw()) {
case rt_bgezal:
case rt_bltzal:
return true;
default:
return false;
};
case op_special:
switch (functionFieldRaw()) {
case ff_jalr:
return true;
default:
return false;
};
default:
return false;
};
}
bool SimInstruction::isTrap()
const {
if (opcodeFieldRaw() != op_special) {
return false;
}
else {
switch (functionFieldRaw()) {
case ff_break:
return instructionBits() != kCallRedirInstr;
case ff_tge:
case ff_tgeu:
case ff_tlt:
case ff_tltu:
case ff_teq:
case ff_tne:
return bits(15, 6) != kWasmTrapCode;
default:
return false;
};
}
}
SimInstruction::Type SimInstruction::instructionType()
const {
switch (opcodeFieldRaw()) {
case op_special:
switch (functionFieldRaw()) {
case ff_jr:
case ff_jalr:
case ff_sync:
case ff_break:
case ff_sll:
case ff_dsll:
case ff_dsll32:
case ff_srl:
case ff_dsrl:
case ff_dsrl32:
case ff_sra:
case ff_dsra:
case ff_dsra32:
case ff_sllv:
case ff_dsllv:
case ff_srlv:
case ff_dsrlv:
case ff_srav:
case ff_dsrav:
case ff_mfhi:
case ff_mflo:
case ff_mult:
case ff_dmult:
case ff_multu:
case ff_dmultu:
case ff_div:
case ff_ddiv:
case ff_divu:
case ff_ddivu:
case ff_add:
case ff_dadd:
case ff_addu:
case ff_daddu:
case ff_sub:
case ff_dsub:
case ff_subu:
case ff_dsubu:
case ff_and:
case ff_or:
case ff_xor:
case ff_nor:
case ff_slt:
case ff_sltu:
case ff_tge:
case ff_tgeu:
case ff_tlt:
case ff_tltu:
case ff_teq:
case ff_tne:
case ff_movz:
case ff_movn:
case ff_movci:
return kRegisterType;
default:
return kUnsupported;
};
break;
case op_special2:
switch (functionFieldRaw()) {
case ff_mul:
case ff_clz:
case ff_dclz:
return kRegisterType;
default:
return kUnsupported;
};
break;
case op_special3:
switch (functionFieldRaw()) {
case ff_ins:
case ff_dins:
case ff_dinsm:
case ff_dinsu:
case ff_ext:
case ff_dext:
case ff_dextm:
case ff_dextu:
case ff_bshfl:
case ff_dbshfl:
return kRegisterType;
default:
return kUnsupported;
};
break;
case op_cop1:
// Coprocessor instructions.
switch (rsFieldRawNoAssert()) {
case rs_bc1:
// Branch on coprocessor condition.
return kImmediateType;
default:
return kRegisterType;
};
break;
case op_cop1x:
return kRegisterType;
// 16 bits Immediate type instructions. e.g.: addi dest, src, imm16.
case op_regimm:
case op_beq:
case op_bne:
case op_blez:
case op_bgtz:
case op_addi:
case op_daddi:
case op_addiu:
case op_daddiu:
case op_slti:
case op_sltiu:
case op_andi:
case op_ori:
case op_xori:
case op_lui:
case op_beql:
case op_bnel:
case op_blezl:
case op_bgtzl:
case op_lb:
case op_lbu:
case op_lh:
case op_lhu:
case op_lw:
case op_lwu:
case op_lwl:
case op_lwr:
case op_ll:
case op_lld:
case op_ld:
case op_ldl:
case op_ldr:
case op_sb:
case op_sh:
case op_sw:
case op_swl:
case op_swr:
case op_sc:
case op_scd:
case op_sd:
case op_sdl:
case op_sdr:
case op_lwc1:
case op_ldc1:
case op_swc1:
case op_sdc1:
return kImmediateType;
// 26 bits immediate type instructions. e.g.: j imm26.
case op_j:
case op_jal:
return kJumpType;
default:
return kUnsupported;
};
return kUnsupported;
}
// C/C++ argument slots size.
const int kCArgSlotCount = 0;
const int kCArgsSlotsSize = kCArgSlotCount *
sizeof(uintptr_t);
const int kBranchReturnOffset = 2 * SimInstruction::kInstrSize;
class CachePage {
public:
static const int LINE_VALID = 0;
static const int LINE_INVALID = 1;
static const int kPageShift = 12;
static const int kPageSize = 1 << kPageShift;
static const int kPageMask = kPageSize - 1;
static const int kLineShift = 2;
// The cache line is only 4 bytes right now.
static const int kLineLength = 1 << kLineShift;
static const int kLineMask = kLineLength - 1;
CachePage() { memset(&validity_map_, LINE_INVALID,
sizeof(validity_map_)); }
char* validityByte(
int offset) {
return &validity_map_[offset >> kLineShift];
}
char* cachedData(
int offset) {
return &data_[offset]; }
private:
char data_[kPageSize];
// The cached data.
static const int kValidityMapSize = kPageSize >> kLineShift;
char validity_map_[kValidityMapSize];
// One byte per line.
};
// Protects the icache() and redirection() properties of the
// Simulator.
class AutoLockSimulatorCache :
public LockGuard<Mutex> {
using Base = LockGuard<Mutex>;
public:
explicit AutoLockSimulatorCache()
: Base(SimulatorProcess::singleton_->cacheLock_) {}
};
mozilla::Atomic<size_t, mozilla::ReleaseAcquire>
SimulatorProcess::ICacheCheckingDisableCount(
1);
// Checking is disabled by default.
SimulatorProcess* SimulatorProcess::singleton_ = nullptr;
int64_t Simulator::StopSimAt = -1;
Simulator* Simulator::Create() {
auto sim = MakeUnique<Simulator>();
if (!sim) {
return nullptr;
}
if (!sim->init()) {
return nullptr;
}
int64_t stopAt;
char* stopAtStr = getenv(
"MIPS_SIM_STOP_AT");
if (stopAtStr && sscanf(stopAtStr,
"%" PRIi64, &stopAt) == 1) {
fprintf(stderr,
"\nStopping simulation at icount %" PRIi64
"\n", stopAt);
Simulator::StopSimAt = stopAt;
}
return sim.release();
}
void Simulator::Destroy(Simulator* sim) { js_delete(sim); }
// The MipsDebugger class is used by the simulator while debugging simulated
// code.
class MipsDebugger {
public:
explicit MipsDebugger(Simulator* sim) : sim_(sim) {}
void stop(SimInstruction* instr);
void debug();
// Print all registers with a nice formatting.
void printAllRegs();
void printAllRegsIncludingFPU();
private:
// We set the breakpoint code to 0xfffff to easily recognize it.
static const Instr kBreakpointInstr = op_special | ff_break | 0xfffff << 6;
static const Instr kNopInstr = op_special | ff_sll;
Simulator* sim_;
int64_t getRegisterValue(
int regnum);
int64_t getFPURegisterValueLong(
int regnum);
float getFPURegisterValueFloat(
int regnum);
double getFPURegisterValueDouble(
int regnum);
bool getValue(
const char* desc, int64_t* value);
// Set or delete a breakpoint. Returns true if successful.
bool setBreakpoint(SimInstruction* breakpc);
bool deleteBreakpoint(SimInstruction* breakpc);
// Undo and redo all breakpoints. This is needed to bracket disassembly and
// execution to skip past breakpoints when run from the debugger.
void undoBreakpoints();
void redoBreakpoints();
};
static void UNSUPPORTED() {
printf(
"Unsupported instruction.\n");
MOZ_CRASH();
}
void MipsDebugger::stop(SimInstruction* instr) {
// Get the stop code.
uint32_t code = instr->bits(25, 6);
// Retrieve the encoded address, which comes just after this stop.
char* msg =
*
reinterpret_cast<
char**>(sim_->get_pc() + SimInstruction::kInstrSize);
// Update this stop description.
if (!sim_->watchedStops_[code].desc_) {
sim_->watchedStops_[code].desc_ = msg;
}
// Print the stop message and code if it is not the default code.
if (code != kMaxStopCode) {
printf(
"Simulator hit stop %u: %s\n", code, msg);
}
else {
printf(
"Simulator hit %s\n", msg);
}
sim_->set_pc(sim_->get_pc() + 2 * SimInstruction::kInstrSize);
debug();
}
int64_t MipsDebugger::getRegisterValue(
int regnum) {
if (regnum == kPCRegister) {
return sim_->get_pc();
}
return sim_->getRegister(regnum);
}
int64_t MipsDebugger::getFPURegisterValueLong(
int regnum) {
return sim_->getFpuRegister(regnum);
}
float MipsDebugger::getFPURegisterValueFloat(
int regnum) {
return sim_->getFpuRegisterFloat(regnum);
}
double MipsDebugger::getFPURegisterValueDouble(
int regnum) {
return sim_->getFpuRegisterDouble(regnum);
}
bool MipsDebugger::getValue(
const char* desc, int64_t* value) {
Register reg =
Register::FromName(desc);
if (reg != InvalidReg) {
*value = getRegisterValue(reg.code());
return true;
}
if (strncmp(desc,
"0x", 2) == 0) {
return sscanf(desc,
"%" PRIu64,
reinterpret_cast<uint64_t*>(value)) == 1;
}
return sscanf(desc,
"%" PRIi64, value) == 1;
}
bool MipsDebugger::setBreakpoint(SimInstruction* breakpc) {
// Check if a breakpoint can be set. If not return without any side-effects.
if (sim_->break_pc_ != nullptr) {
return false;
}
// Set the breakpoint.
sim_->break_pc_ = breakpc;
sim_->break_instr_ = breakpc->instructionBits();
// Not setting the breakpoint instruction in the code itself. It will be set
// when the debugger shell continues.
return true;
}
bool MipsDebugger::deleteBreakpoint(SimInstruction* breakpc) {
if (sim_->break_pc_ != nullptr) {
sim_->break_pc_->setInstructionBits(sim_->break_instr_);
}
sim_->break_pc_ = nullptr;
sim_->break_instr_ = 0;
return true;
}
void MipsDebugger::undoBreakpoints() {
if (sim_->break_pc_) {
sim_->break_pc_->setInstructionBits(sim_->break_instr_);
}
}
void MipsDebugger::redoBreakpoints() {
if (sim_->break_pc_) {
sim_->break_pc_->setInstructionBits(kBreakpointInstr);
}
}
void MipsDebugger::printAllRegs() {
int64_t value;
for (uint32_t i = 0; i < Registers::Total; i++) {
value = getRegisterValue(i);
printf(
"%3s: 0x%016" PRIx64
" %20" PRIi64
" ", Registers::GetName(i),
value, value);
if (i % 2) {
printf(
"\n");
}
}
printf(
"\n");
value = getRegisterValue(Simulator::LO);
printf(
" LO: 0x%016" PRIx64
" %20" PRIi64
" ", value, value);
value = getRegisterValue(Simulator::HI);
printf(
" HI: 0x%016" PRIx64
" %20" PRIi64
"\n", value, value);
value = getRegisterValue(Simulator::pc);
printf(
" pc: 0x%016" PRIx64
"\n", value);
}
void MipsDebugger::printAllRegsIncludingFPU() {
printAllRegs();
printf(
"\n\n");
// f0, f1, f2, ... f31.
for (uint32_t i = 0; i < FloatRegisters::TotalPhys; i++) {
printf(
"%3s: 0x%016" PRIi64
"\tflt: %-8.4g\tdbl: %-16.4g\n",
FloatRegisters::GetName(i), getFPURegisterValueLong(i),
getFPURegisterValueFloat(i), getFPURegisterValueDouble(i));
}
}
static char* ReadLine(
const char* prompt) {
UniqueChars result;
char lineBuf[256];
int offset = 0;
bool keepGoing =
true;
fprintf(stdout,
"%s", prompt);
fflush(stdout);
while (keepGoing) {
if (fgets(lineBuf,
sizeof(lineBuf), stdin) == nullptr) {
// fgets got an error. Just give up.
return nullptr;
}
int len = strlen(lineBuf);
if (len > 0 && lineBuf[len - 1] ==
'\n') {
// Since we read a new line we are done reading the line. This
// will exit the loop after copying this buffer into the result.
keepGoing =
false;
}
if (!result) {
// Allocate the initial result and make room for the terminating '\0'
result.reset(js_pod_malloc<
char>(len + 1));
if (!result) {
return nullptr;
}
}
else {
// Allocate a new result with enough room for the new addition.
int new_len = offset + len + 1;
char* new_result = js_pod_malloc<
char>(new_len);
if (!new_result) {
return nullptr;
}
// Copy the existing input into the new array and set the new
// array as the result.
memcpy(new_result, result.get(), offset *
sizeof(
char));
result.reset(new_result);
}
// Copy the newly read line into the result.
memcpy(result.get() + offset, lineBuf, len *
sizeof(
char));
offset += len;
}
MOZ_ASSERT(result);
result[offset] =
'\0';
return result.release();
}
static void DisassembleInstruction(uint64_t pc) {
uint8_t* bytes =
reinterpret_cast<uint8_t*>(pc);
char hexbytes[256];
sprintf(hexbytes,
"0x%x 0x%x 0x%x 0x%x", bytes[0], bytes[1], bytes[2],
bytes[3]);
char llvmcmd[1024];
sprintf(llvmcmd,
"bash -c \"echo -n
'%p'; echo
'%s' |
"
"llvm-mc -disassemble -arch=mips64el -mcpu=mips64r2 | "
"grep -v pure_instructions | grep -v .text\"",
static_cast<
void*>(bytes), hexbytes);
if (system(llvmcmd)) {
printf(
"Cannot disassemble instruction.\n");
}
}
void MipsDebugger::debug() {
intptr_t lastPC = -1;
bool done =
false;
#define COMMAND_SIZE 63
#define ARG_SIZE 255
#define STR(a)
#a
#define XSTR(a) STR(a)
char cmd[COMMAND_SIZE + 1];
char arg1[ARG_SIZE + 1];
char arg2[ARG_SIZE + 1];
char* argv[3] = {cmd, arg1, arg2};
// Make sure to have a proper terminating character if reaching the limit.
cmd[COMMAND_SIZE] = 0;
arg1[ARG_SIZE] = 0;
arg2[ARG_SIZE] = 0;
// Undo all set breakpoints while running in the debugger shell. This will
// make them invisible to all commands.
undoBreakpoints();
while (!done && (sim_->get_pc() != Simulator::end_sim_pc)) {
if (lastPC != sim_->get_pc()) {
DisassembleInstruction(sim_->get_pc());
lastPC = sim_->get_pc();
}
char* line = ReadLine(
"sim> ");
if (line == nullptr) {
break;
}
else {
char* last_input = sim_->lastDebuggerInput();
if (strcmp(line,
"\n") == 0 && last_input != nullptr) {
line = last_input;
}
else {
// Ownership is transferred to sim_;
sim_->setLastDebuggerInput(line);
}
// Use sscanf to parse the individual parts of the command line. At the
// moment no command expects more than two parameters.
int argc = sscanf(line,
"%" XSTR(COMMAND_SIZE)
"s "
"%" XSTR(ARG_SIZE)
"s "
"%" XSTR(ARG_SIZE)
"s",
cmd, arg1, arg2);
if ((strcmp(cmd,
"si") == 0) || (strcmp(cmd,
"stepi") == 0)) {
SimInstruction* instr =
reinterpret_cast<SimInstruction*>(sim_->get_pc());
if (!instr->isTrap()) {
sim_->instructionDecode(
reinterpret_cast<SimInstruction*>(sim_->get_pc()));
}
else {
// Allow si to jump over generated breakpoints.
printf(
"/!\\ Jumping over generated breakpoint.\n");
sim_->set_pc(sim_->get_pc() + SimInstruction::kInstrSize);
}
}
else if ((strcmp(cmd,
"c") == 0) || (strcmp(cmd,
"cont") == 0)) {
// Execute the one instruction we broke at with breakpoints disabled.
sim_->instructionDecode(
reinterpret_cast<SimInstruction*>(sim_->get_pc()));
// Leave the debugger shell.
done =
true;
}
else if ((strcmp(cmd,
"p") == 0) || (strcmp(cmd,
"print") == 0)) {
if (argc == 2) {
int64_t value;
if (strcmp(arg1,
"all") == 0) {
printAllRegs();
}
else if (strcmp(arg1,
"allf") == 0) {
printAllRegsIncludingFPU();
}
else {
Register reg =
Register::FromName(arg1);
FloatRegisters::Encoding fReg = FloatRegisters::FromName(arg1);
if (reg != InvalidReg) {
value = getRegisterValue(reg.code());
printf(
"%s: 0x%016" PRIi64
" %20" PRIi64
" \n", arg1, value,
value);
}
else if (fReg != FloatRegisters::Invalid) {
printf(
"%3s: 0x%016" PRIi64
"\tflt: %-8.4g\tdbl: %-16.4g\n",
FloatRegisters::GetName(fReg),
getFPURegisterValueLong(fReg),
getFPURegisterValueFloat(fReg),
getFPURegisterValueDouble(fReg));
}
else {
printf(
"%s unrecognized\n", arg1);
}
}
}
else {
printf(
"print or print single\n");
}
}
else if (strcmp(cmd,
"stack") == 0 || strcmp(cmd,
"mem") == 0) {
int64_t* cur = nullptr;
int64_t* end = nullptr;
int next_arg = 1;
if (strcmp(cmd,
"stack") == 0) {
cur =
reinterpret_cast<int64_t*>(sim_->getRegister(Simulator::sp));
}
else {
// Command "mem".
int64_t value;
if (!getValue(arg1, &value)) {
printf(
"%s unrecognized\n", arg1);
continue;
}
cur =
reinterpret_cast<int64_t*>(value);
next_arg++;
}
int64_t words;
if (argc == next_arg) {
words = 10;
}
else {
if (!getValue(argv[next_arg], &words)) {
words = 10;
}
}
end = cur + words;
while (cur < end) {
printf(
" %p: 0x%016" PRIx64
" %20" PRIi64, cur, *cur, *cur);
printf(
"\n");
cur++;
}
}
else if ((strcmp(cmd,
"disasm") == 0) || (strcmp(cmd,
"dpc") == 0) ||
(strcmp(cmd,
"di") == 0)) {
uint8_t* cur = nullptr;
uint8_t* end = nullptr;
if (argc == 1) {
cur =
reinterpret_cast<uint8_t*>(sim_->get_pc());
end = cur + (10 * SimInstruction::kInstrSize);
}
else if (argc == 2) {
Register reg =
Register::FromName(arg1);
if (reg != InvalidReg || strncmp(arg1,
"0x", 2) == 0) {
// The argument is an address or a register name.
int64_t value;
if (getValue(arg1, &value)) {
cur =
reinterpret_cast<uint8_t*>(value);
// Disassemble 10 instructions at <arg1>.
end = cur + (10 * SimInstruction::kInstrSize);
}
}
else {
// The argument is the number of instructions.
int64_t value;
if (getValue(arg1, &value)) {
cur =
reinterpret_cast<uint8_t*>(sim_->get_pc());
// Disassemble <arg1> instructions.
end = cur + (value * SimInstruction::kInstrSize);
}
}
}
else {
int64_t value1;
int64_t value2;
if (getValue(arg1, &value1) && getValue(arg2, &value2)) {
cur =
reinterpret_cast<uint8_t*>(value1);
end = cur + (value2 * SimInstruction::kInstrSize);
}
}
while (cur < end) {
DisassembleInstruction(uint64_t(cur));
cur += SimInstruction::kInstrSize;
}
}
else if (strcmp(cmd,
"gdb") == 0) {
printf(
"relinquishing control to gdb\n");
asm(
"int $3");
printf(
"regaining control from gdb\n");
}
else if (strcmp(cmd,
"break") == 0) {
if (argc == 2) {
int64_t value;
if (getValue(arg1, &value)) {
if (!setBreakpoint(
reinterpret_cast<SimInstruction*>(value))) {
printf(
"setting breakpoint failed\n");
}
}
else {
printf(
"%s unrecognized\n", arg1);
}
}
else {
printf(
"break \n");
}
}
else if (strcmp(cmd,
"del") == 0) {
if (!deleteBreakpoint(nullptr)) {
printf(
"deleting breakpoint failed\n");
}
}
else if (strcmp(cmd,
"flags") == 0) {
printf(
"No flags on MIPS !\n");
}
else if (strcmp(cmd,
"stop") == 0) {
int64_t value;
intptr_t stop_pc = sim_->get_pc() - 2 * SimInstruction::kInstrSize;
SimInstruction* stop_instr =
reinterpret_cast<SimInstruction*>(stop_pc);
SimInstruction* msg_address =
reinterpret_cast<SimInstruction*>(
stop_pc + SimInstruction::kInstrSize);
if ((argc == 2) && (strcmp(arg1,
"unstop") == 0)) {
// Remove the current stop.
if (sim_->isStopInstruction(stop_instr)) {
stop_instr->setInstructionBits(kNopInstr);
msg_address->setInstructionBits(kNopInstr);
}
else {
printf(
"Not at debugger stop.\n");
}
}
else if (argc == 3) {
// Print information about all/the specified breakpoint(s).
if (strcmp(arg1,
"info") == 0) {
if (strcmp(arg2,
"all") == 0) {
printf(
"Stop information:\n");
for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
i++) {
sim_->printStopInfo(i);
}
}
else if (getValue(arg2, &value)) {
sim_->printStopInfo(value);
}
else {
printf(
"Unrecognized argument.\n");
}
}
else if (strcmp(arg1,
"enable") == 0) {
// Enable all/the specified breakpoint(s).
if (strcmp(arg2,
"all") == 0) {
for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
i++) {
sim_->enableStop(i);
}
}
else if (getValue(arg2, &value)) {
sim_->enableStop(value);
}
else {
printf(
"Unrecognized argument.\n");
}
}
else if (strcmp(arg1,
"disable") == 0) {
// Disable all/the specified breakpoint(s).
if (strcmp(arg2,
"all") == 0) {
for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode;
i++) {
sim_->disableStop(i);
}
}
else if (getValue(arg2, &value)) {
sim_->disableStop(value);
}
else {
printf(
"Unrecognized argument.\n");
}
}
}
else {
printf(
"Wrong usage. Use help command for more information.\n");
}
}
else if ((strcmp(cmd,
"h") == 0) || (strcmp(cmd,
"help") == 0)) {
printf(
"cont\n");
printf(
" continue execution (alias 'c')\n");
printf(
"stepi\n");
printf(
" step one instruction (alias 'si')\n");
printf(
"print \n");
printf(
" print register content (alias 'p')\n");
printf(
" use register name 'all' to print all registers\n");
printf(
"printobject \n");
printf(
" print an object from a register (alias 'po')\n");
printf(
"stack []\n");
printf(
" dump stack content, default dump 10 words)\n");
printf(
"mem []\n");
printf(
" dump memory content, default dump 10 words)\n");
printf(
"flags\n");
printf(
" print flags\n");
printf(
"disasm []\n");
printf(
"disasm []\n");
printf(
"disasm [[] ]\n");
printf(
" disassemble code, default is 10 instructions\n");
printf(
" from pc (alias 'di')\n");
printf(
"gdb\n");
printf(
" enter gdb\n");
printf(
"break \n");
printf(
" set a break point on the address\n");
printf(
"del\n");
printf(
" delete the breakpoint\n");
printf(
"stop feature:\n");
printf(
" Description:\n");
printf(
" Stops are debug instructions inserted by\n");
printf(
" the Assembler::stop() function.\n");
printf(
" When hitting a stop, the Simulator will\n");
printf(
" stop and and give control to the Debugger.\n");
printf(
" All stop codes are watched:\n");
printf(
" - They can be enabled / disabled: the Simulator\n");
printf(
" will / won't stop when hitting them.\n");
printf(
" - The Simulator keeps track of how many times they \n");
printf(
" are met. (See the info command.) Going over a\n");
printf(
" disabled stop still increases its counter. \n");
printf(
" Commands:\n");
printf(
" stop info all/ : print infos about number \n");
printf(
" or all stop(s).\n");
printf(
" stop enable/disable all/ : enables / disables\n");
printf(
" all or number stop(s)\n");
printf(
" stop unstop\n");
printf(
" ignore the stop instruction at the current location\n");
printf(
" from now on\n");
}
else {
printf(
"Unknown command: %s\n", cmd);
}
}
}
// Add all the breakpoints back to stop execution and enter the debugger
// shell when hit.
redoBreakpoints();
#undef COMMAND_SIZE
#undef ARG_SIZE
#undef STR
#undef XSTR
}
static bool AllOnOnePage(uintptr_t start,
int size) {
intptr_t start_page = (start & ~CachePage::kPageMask);
intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
return start_page == end_page;
}
void Simulator::setLastDebuggerInput(
char* input) {
js_free(lastDebuggerInput_);
lastDebuggerInput_ = input;
}
static CachePage* GetCachePageLocked(SimulatorProcess::ICacheMap& i_cache,
void* page) {
SimulatorProcess::ICacheMap::AddPtr p = i_cache.lookupForAdd(page);
if (p) {
return p->value();
}
AutoEnterOOMUnsafeRegion oomUnsafe;
CachePage* new_page = js_new<CachePage>();
if (!new_page || !i_cache.add(p, page, new_page)) {
oomUnsafe.crash(
"Simulator CachePage");
}
return new_page;
}
// Flush from start up to and not including start + size.
static void FlushOnePageLocked(SimulatorProcess::ICacheMap& i_cache,
intptr_t start,
int size) {
MOZ_ASSERT(size <= CachePage::kPageSize);
MOZ_ASSERT(AllOnOnePage(start, size - 1));
MOZ_ASSERT((start & CachePage::kLineMask) == 0);
MOZ_ASSERT((size & CachePage::kLineMask) == 0);
void* page =
reinterpret_cast<
void*>(start & (~CachePage::kPageMask));
int offset = (start & CachePage::kPageMask);
CachePage* cache_page = GetCachePageLocked(i_cache, page);
char* valid_bytemap = cache_page->validityByte(offset);
memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
}
static void FlushICacheLocked(SimulatorProcess::ICacheMap& i_cache,
void* start_addr, size_t size) {
intptr_t start =
reinterpret_cast<intptr_t>(start_addr);
int intra_line = (start & CachePage::kLineMask);
start -= intra_line;
size += intra_line;
size = ((size - 1) | CachePage::kLineMask) + 1;
int offset = (start & CachePage::kPageMask);
while (!AllOnOnePage(start, size - 1)) {
int bytes_to_flush = CachePage::kPageSize - offset;
FlushOnePageLocked(i_cache, start, bytes_to_flush);
start += bytes_to_flush;
size -= bytes_to_flush;
MOZ_ASSERT((start & CachePage::kPageMask) == 0);
offset = 0;
}
if (size != 0) {
FlushOnePageLocked(i_cache, start, size);
}
}
/* static */
void SimulatorProcess::checkICacheLocked(SimInstruction* instr) {
intptr_t address =
reinterpret_cast<intptr_t>(instr);
void* page =
reinterpret_cast<
void*>(address & (~CachePage::kPageMask));
void* line =
reinterpret_cast<
void*>(address & (~CachePage::kLineMask));
int offset = (address & CachePage::kPageMask);
CachePage* cache_page = GetCachePageLocked(icache(), page);
char* cache_valid_byte = cache_page->validityByte(offset);
bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
char* cached_line = cache_page->cachedData(offset & ~CachePage::kLineMask);
if (cache_hit) {
// Check that the data in memory matches the contents of the I-cache.
int cmpret =
memcmp(
reinterpret_cast<
void*>(instr), cache_page->cachedData(offset),
SimInstruction::kInstrSize);
MOZ_ASSERT(cmpret == 0);
}
else {
// Cache miss. Load memory into the cache.
memcpy(cached_line, line, CachePage::kLineLength);
*cache_valid_byte = CachePage::LINE_VALID;
}
}
HashNumber SimulatorProcess::ICacheHasher::hash(
const Lookup& l) {
return U32(
reinterpret_cast<uintptr_t>(l)) >> 2;
}
bool SimulatorProcess::ICacheHasher::match(
const Key& k,
const Lookup& l) {
MOZ_ASSERT((
reinterpret_cast<intptr_t>(k) & CachePage::kPageMask) == 0);
MOZ_ASSERT((
reinterpret_cast<intptr_t>(l) & CachePage::kPageMask) == 0);
return k == l;
}
/* static */
void SimulatorProcess::FlushICache(
void* start_addr, size_t size) {
if (!ICacheCheckingDisableCount) {
AutoLockSimulatorCache als;
js::jit::FlushICacheLocked(icache(), start_addr, size);
}
}
Simulator::Simulator() {
// Set up simulator support first. Some of this information is needed to
// setup the architecture state.
// Note, allocation and anything that depends on allocated memory is
// deferred until init(), in order to handle OOM properly.
stack_ = nullptr;
stackLimit_ = 0;
pc_modified_ =
false;
icount_ = 0;
break_count_ = 0;
break_pc_ = nullptr;
break_instr_ = 0;
single_stepping_ =
false;
single_step_callback_ = nullptr;
single_step_callback_arg_ = nullptr;
// Set up architecture state.
// All registers are initialized to zero to start with.
for (
int i = 0; i <
Register::kNumSimuRegisters; i++) {
registers_[i] = 0;
}
for (
int i = 0; i < Simulator::FPURegister::kNumFPURegisters; i++) {
FPUregisters_[i] = 0;
}
FCSR_ = 0;
LLBit_ =
false;
LLAddr_ = 0;
lastLLValue_ = 0;
// The ra and pc are initialized to a known bad value that will cause an
// access violation if the simulator ever tries to execute it.
registers_[pc] = bad_ra;
registers_[ra] = bad_ra;
for (
int i = 0; i < kNumExceptions; i++) {
exceptions[i] = 0;
}
lastDebuggerInput_ = nullptr;
}
bool Simulator::init() {
// Allocate 2MB for the stack. Note that we will only use 1MB, see below.
static const size_t stackSize = 2 * 1024 * 1024;
stack_ = js_pod_malloc<
char>(stackSize);
if (!stack_) {
return false;
}
// Leave a safety margin of 1MB to prevent overrunning the stack when
// pushing values (total stack size is 2MB).
stackLimit_ =
reinterpret_cast<uintptr_t>(stack_) + 1024 * 1024;
// The sp is initialized to point to the bottom (high address) of the
// allocated stack area. To be safe in potential stack underflows we leave
// some buffer below.
registers_[sp] =
reinterpret_cast<int64_t>(stack_) + stackSize - 64;
return true;
}
// When the generated code calls an external reference we need to catch that in
// the simulator. The external reference will be a function compiled for the
// host architecture. We need to call that function instead of trying to
// execute it with the simulator. We do that by redirecting the external
// reference to a swi (software-interrupt) instruction that is handled by
// the simulator. We write the original destination of the jump just at a known
// offset from the swi instruction so the simulator knows what to call.
class Redirection {
friend class SimulatorProcess;
// sim's lock must already be held.
Redirection(
void* nativeFunction, ABIFunctionType type)
: nativeFunction_(nativeFunction),
swiInstruction_(kCallRedirInstr),
type_(type),
next_(nullptr) {
next_ = SimulatorProcess::redirection();
if (!SimulatorProcess::ICacheCheckingDisableCount) {
FlushICacheLocked(SimulatorProcess::icache(), addressOfSwiInstruction(),
SimInstruction::kInstrSize);
}
SimulatorProcess::setRedirection(
this);
}
public:
void* addressOfSwiInstruction() {
return &swiInstruction_; }
void* nativeFunction()
const {
return nativeFunction_; }
ABIFunctionType type()
const {
return type_; }
static Redirection* Get(
void* nativeFunction, ABIFunctionType type) {
AutoLockSimulatorCache als;
Redirection* current = SimulatorProcess::redirection();
for (; current != nullptr; current = current->next_) {
if (current->nativeFunction_ == nativeFunction) {
MOZ_ASSERT(current->type() == type);
return current;
}
}
// Note: we can't use js_new here because the constructor is private.
AutoEnterOOMUnsafeRegion oomUnsafe;
Redirection* redir = js_pod_malloc<Redirection>(1);
if (!redir) {
oomUnsafe.crash(
"Simulator redirection");
}
new (redir) Redirection(nativeFunction, type);
return redir;
}
static Redirection* FromSwiInstruction(SimInstruction* swiInstruction) {
uint8_t* addrOfSwi =
reinterpret_cast<uint8_t*>(swiInstruction);
uint8_t* addrOfRedirection =
addrOfSwi - offsetof(Redirection, swiInstruction_);
return reinterpret_cast<Redirection*>(addrOfRedirection);
}
private:
void* nativeFunction_;
uint32_t swiInstruction_;
ABIFunctionType type_;
Redirection* next_;
};
Simulator::~Simulator() { js_free(stack_); }
SimulatorProcess::SimulatorProcess()
: cacheLock_(mutexid::SimulatorCacheLock), redirection_(nullptr) {
if (getenv(
"MIPS_SIM_ICACHE_CHECKS")) {
ICacheCheckingDisableCount = 0;
}
}
SimulatorProcess::~SimulatorProcess() {
Redirection* r = redirection_;
while (r) {
Redirection* next = r->next_;
js_delete(r);
r = next;
}
}
/* static */
void* Simulator::RedirectNativeFunction(
void* nativeFunction,
ABIFunctionType type) {
Redirection* redirection = Redirection::Get(nativeFunction, type);
return redirection->addressOfSwiInstruction();
}
// Get the active Simulator for the current thread.
Simulator* Simulator::Current() {
JSContext* cx = TlsContext.get();
MOZ_ASSERT(CurrentThreadCanAccessRuntime(cx->runtime()));
return cx->simulator();
}
// Sets the register in the architecture state. It will also deal with updating
// Simulator internal state for special registers such as PC.
void Simulator::setRegister(
int reg, int64_t value) {
MOZ_ASSERT((reg >= 0) && (reg <
Register::kNumSimuRegisters));
if (reg == pc) {
pc_modified_ =
true;
}
// Zero register always holds 0.
registers_[reg] = (reg == 0) ? 0 : value;
}
void Simulator::setFpuRegister(
int fpureg, int64_t value) {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
FPUregisters_[fpureg] = value;
}
void Simulator::setFpuRegisterLo(
int fpureg, int32_t value) {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
*mozilla::BitwiseCast<int32_t*>(&FPUregisters_[fpureg]) = value;
}
void Simulator::setFpuRegisterHi(
int fpureg, int32_t value) {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
*((mozilla::BitwiseCast<int32_t*>(&FPUregisters_[fpureg])) + 1) = value;
}
void Simulator::setFpuRegisterFloat(
int fpureg,
float value) {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
*mozilla::BitwiseCast<
float*>(&FPUregisters_[fpureg]) = value;
}
void Simulator::setFpuRegisterDouble(
int fpureg,
double value) {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
*mozilla::BitwiseCast<
double*>(&FPUregisters_[fpureg]) = value;
}
// Get the register from the architecture state. This function does handle
// the special case of accessing the PC register.
int64_t Simulator::getRegister(
int reg)
const {
MOZ_ASSERT((reg >= 0) && (reg <
Register::kNumSimuRegisters));
if (reg == 0) {
return 0;
}
return registers_[reg] + ((reg == pc) ? SimInstruction::kPCReadOffset : 0);
}
int64_t Simulator::getFpuRegister(
int fpureg)
const {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
return FPUregisters_[fpureg];
}
int32_t Simulator::getFpuRegisterLo(
int fpureg)
const {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
return *mozilla::BitwiseCast<int32_t*>(&FPUregisters_[fpureg]);
}
int32_t Simulator::getFpuRegisterHi(
int fpureg)
const {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
return *((mozilla::BitwiseCast<int32_t*>(&FPUregisters_[fpureg])) + 1);
}
float Simulator::getFpuRegisterFloat(
int fpureg)
const {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
return *mozilla::BitwiseCast<
float*>(&FPUregisters_[fpureg]);
}
double Simulator::getFpuRegisterDouble(
int fpureg)
const {
MOZ_ASSERT((fpureg >= 0) &&
(fpureg < Simulator::FPURegister::kNumFPURegisters));
return *mozilla::BitwiseCast<
double*>(&FPUregisters_[fpureg]);
}
void Simulator::setCallResultDouble(
double result) {
setFpuRegisterDouble(f0, result);
}
void Simulator::setCallResultFloat(
float result) {
setFpuRegisterFloat(f0, result);
}
void Simulator::setCallResult(int64_t res) { setRegister(v0, res); }
void Simulator::setCallResult(__int128_t res) {
setRegister(v0, I64(res));
setRegister(v1, I64(res >> 64));
}
// Helper functions for setting and testing the FCSR register's bits.
void Simulator::setFCSRBit(uint32_t cc,
bool value) {
if (value) {
FCSR_ |= (1 << cc);
}
else {
FCSR_ &= ~(1 << cc);
}
}
bool Simulator::testFCSRBit(uint32_t cc) {
return FCSR_ & (1 << cc); }
// Sets the rounding error codes in FCSR based on the result of the rounding.
// Returns true if the operation was invalid.
template <
typename T>
bool Simulator::setFCSRRoundError(
double original,
double rounded) {
bool ret =
false;
setFCSRBit(kFCSRInexactCauseBit,
false);
setFCSRBit(kFCSRUnderflowCauseBit,
false);
setFCSRBit(kFCSROverflowCauseBit,
false);
setFCSRBit(kFCSRInvalidOpCauseBit,
false);
if (!std::isfinite(original) || !std::isfinite(rounded)) {
setFCSRBit(kFCSRInvalidOpFlagBit,
true);
setFCSRBit(kFCSRInvalidOpCauseBit,
true);
ret =
true;
}
if (original != rounded) {
setFCSRBit(kFCSRInexactFlagBit,
true);
setFCSRBit(kFCSRInexactCauseBit,
true);
}
if (rounded < DBL_MIN && rounded > -DBL_MIN && rounded != 0) {
setFCSRBit(kFCSRUnderflowFlagBit,
true);
setFCSRBit(kFCSRUnderflowCauseBit,
true);
ret =
true;
}
if ((
long double)rounded > (
long double)std::numeric_limits<T>::max() ||
(
long double)rounded < (
long double)std::numeric_limits<T>::min()) {
setFCSRBit(kFCSROverflowFlagBit,
true);
setFCSRBit(kFCSROverflowCauseBit,
true);
// The reference is not really clear but it seems this is required:
setFCSRBit(kFCSRInvalidOpFlagBit,
true);
setFCSRBit(kFCSRInvalidOpCauseBit,
true);
ret =
true;
}
return ret;
}
// Raw access to the PC register.
void Simulator::set_pc(int64_t value) {
pc_modified_ =
true;
registers_[pc] = value;
}
bool Simulator::has_bad_pc()
const {
return ((registers_[pc] == bad_ra) || (registers_[pc] == end_sim_pc));
}
// Raw access to the PC register without the special adjustment when reading.
int64_t Simulator::get_pc()
const {
return registers_[pc]; }
JS::ProfilingFrameIterator::RegisterState Simulator::registerState() {
wasm::RegisterState state;
state.pc = (
void*)get_pc();
state.fp = (
void*)getRegister(fp);
state.sp = (
void*)getRegister(sp);
state.lr = (
void*)getRegister(ra);
return state;
}
static bool AllowUnaligned() {
static bool hasReadFlag =
false;
static bool unalignedAllowedFlag =
false;
if (!hasReadFlag) {
unalignedAllowedFlag = !!getenv(
"MIPS_UNALIGNED");
hasReadFlag =
true;
}
return unalignedAllowedFlag;
}
// MIPS memory instructions (except lw(d)l/r , sw(d)l/r) trap on unaligned
// memory access enabling the OS to handle them via trap-and-emulate. Note that
// simulator runs have the runtime system running directly on the host system
// and only generated code is executed in the simulator. Since the host is
// typically IA32 it will not trap on unaligned memory access. We assume that
// that executing correct generated code will not produce unaligned memory
// access, so we explicitly check for address alignment and trap. Note that
// trapping does not occur when executing wasm code, which requires that
// unaligned memory access provides correct result.
uint8_t Simulator::readBU(uint64_t addr, SimInstruction* instr) {
if (handleWasmSegFault(addr, 1)) {
return 0xff;
}
uint8_t* ptr =
reinterpret_cast<uint8_t*>(addr);
return *ptr;
}
int8_t Simulator::readB(uint64_t addr, SimInstruction* instr) {
if (handleWasmSegFault(addr, 1)) {
return -1;
}
int8_t* ptr =
reinterpret_cast<int8_t*>(addr);
return *ptr;
}
void Simulator::writeB(uint64_t addr, uint8_t value, SimInstruction* instr) {
if (handleWasmSegFault(addr, 1)) {
return;
}
uint8_t* ptr =
reinterpret_cast<uint8_t*>(addr);
*ptr = value;
}
void Simulator::writeB(uint64_t addr, int8_t value, SimInstruction* instr) {
if (handleWasmSegFault(addr, 1)) {
return;
}
int8_t* ptr =
reinterpret_cast<int8_t*>(addr);
*ptr = value;
}
uint16_t Simulator::readHU(uint64_t addr, SimInstruction* instr) {
if (handleWasmSegFault(addr, 2)) {
return 0xffff;
}
if (AllowUnaligned() || (addr & 1) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
uint16_t* ptr =
reinterpret_cast<uint16_t*>(addr);
return *ptr;
}
printf(
"Unaligned unsigned halfword read at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n",
addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
int16_t Simulator::readH(uint64_t addr, SimInstruction* instr) {
if (handleWasmSegFault(addr, 2)) {
return -1;
}
if (AllowUnaligned() || (addr & 1) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
int16_t* ptr =
reinterpret_cast<int16_t*>(addr);
return *ptr;
}
printf(
"Unaligned signed halfword read at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n",
addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
void Simulator::writeH(uint64_t addr, uint16_t value, SimInstruction* instr) {
if (handleWasmSegFault(addr, 2)) {
return;
}
if (AllowUnaligned() || (addr & 1) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
uint16_t* ptr =
reinterpret_cast<uint16_t*>(addr);
LLBit_ =
false;
*ptr = value;
return;
}
printf(
"Unaligned unsigned halfword write at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n",
addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
}
void Simulator::writeH(uint64_t addr, int16_t value, SimInstruction* instr) {
if (handleWasmSegFault(addr, 2)) {
return;
}
if (AllowUnaligned() || (addr & 1) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
int16_t* ptr =
reinterpret_cast<int16_t*>(addr);
LLBit_ =
false;
*ptr = value;
return;
}
printf(
"Unaligned halfword write at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n",
addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
}
uint32_t Simulator::readWU(uint64_t addr, SimInstruction* instr) {
if (handleWasmSegFault(addr, 4)) {
return -1;
}
if (AllowUnaligned() || (addr & 3) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
uint32_t* ptr =
reinterpret_cast<uint32_t*>(addr);
return *ptr;
}
printf(
"Unaligned read at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
int32_t Simulator::readW(uint64_t addr, SimInstruction* instr) {
if (handleWasmSegFault(addr, 4)) {
return -1;
}
if (AllowUnaligned() || (addr & 3) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
int32_t* ptr =
reinterpret_cast<int32_t*>(addr);
return *ptr;
}
printf(
"Unaligned read at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
void Simulator::writeW(uint64_t addr, uint32_t value, SimInstruction* instr) {
if (handleWasmSegFault(addr, 4)) {
return;
}
if (AllowUnaligned() || (addr & 3) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
uint32_t* ptr =
reinterpret_cast<uint32_t*>(addr);
LLBit_ =
false;
*ptr = value;
return;
}
printf(
"Unaligned write at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
}
void Simulator::writeW(uint64_t addr, int32_t value, SimInstruction* instr) {
if (handleWasmSegFault(addr, 4)) {
return;
}
if (AllowUnaligned() || (addr & 3) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
int32_t* ptr =
reinterpret_cast<int32_t*>(addr);
LLBit_ =
false;
*ptr = value;
return;
}
printf(
"Unaligned write at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
}
int64_t Simulator::readDW(uint64_t addr, SimInstruction* instr) {
if (handleWasmSegFault(addr, 8)) {
return -1;
}
if (AllowUnaligned() || (addr & kPointerAlignmentMask) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
intptr_t* ptr =
reinterpret_cast<intptr_t*>(addr);
return *ptr;
}
printf(
"Unaligned read at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
void Simulator::writeDW(uint64_t addr, int64_t value, SimInstruction* instr) {
if (handleWasmSegFault(addr, 8)) {
return;
}
if (AllowUnaligned() || (addr & kPointerAlignmentMask) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
int64_t* ptr =
reinterpret_cast<int64_t*>(addr);
LLBit_ =
false;
*ptr = value;
return;
}
printf(
"Unaligned write at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
}
double Simulator::readD(uint64_t addr, SimInstruction* instr) {
if (handleWasmSegFault(addr, 8)) {
return NAN;
}
if (AllowUnaligned() || (addr & kDoubleAlignmentMask) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
double* ptr =
reinterpret_cast<
double*>(addr);
return *ptr;
}
printf(
"Unaligned (double) read at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n",
addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
void Simulator::writeD(uint64_t addr,
double value, SimInstruction* instr) {
if (handleWasmSegFault(addr, 8)) {
return;
}
if (AllowUnaligned() || (addr & kDoubleAlignmentMask) == 0 ||
wasm::InCompiledCode(
reinterpret_cast<
void*>(get_pc()))) {
double* ptr =
reinterpret_cast<
double*>(addr);
LLBit_ =
false;
*ptr = value;
return;
}
printf(
"Unaligned (double) write at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n",
addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
}
int Simulator::loadLinkedW(uint64_t addr, SimInstruction* instr) {
if ((addr & 3) == 0) {
if (handleWasmSegFault(addr, 4)) {
return -1;
}
volatile int32_t* ptr =
reinterpret_cast<
volatile int32_t*>(addr);
int32_t value = *ptr;
lastLLValue_ = value;
LLAddr_ = addr;
// Note that any memory write or "external" interrupt should reset this
// value to false.
LLBit_ =
true;
return value;
}
printf(
"Unaligned write at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
int Simulator::storeConditionalW(uint64_t addr,
int value,
SimInstruction* instr) {
// Correct behavior in this case, as defined by architecture, is to just
// return 0, but there is no point at allowing that. It is certainly an
// indicator of a bug.
if (addr != LLAddr_) {
printf(
"SC to bad address: 0x%016" PRIx64
", pc=0x%016" PRIx64
", expected: 0x%016" PRIx64
"\n",
addr,
reinterpret_cast<intptr_t>(instr), LLAddr_);
MOZ_CRASH();
}
if ((addr & 3) == 0) {
SharedMem<int32_t*> ptr =
SharedMem<int32_t*>::shared(
reinterpret_cast<int32_t*>(addr));
if (!LLBit_) {
return 0;
}
LLBit_ =
false;
LLAddr_ = 0;
int32_t expected = int32_t(lastLLValue_);
int32_t old =
AtomicOperations::compareExchangeSeqCst(ptr, expected, int32_t(value));
return (old == expected) ? 1 : 0;
}
printf(
"Unaligned SC at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
int64_t Simulator::loadLinkedD(uint64_t addr, SimInstruction* instr) {
if ((addr & kPointerAlignmentMask) == 0) {
if (handleWasmSegFault(addr, 8)) {
return -1;
}
volatile int64_t* ptr =
reinterpret_cast<
volatile int64_t*>(addr);
int64_t value = *ptr;
lastLLValue_ = value;
LLAddr_ = addr;
// Note that any memory write or "external" interrupt should reset this
// value to false.
LLBit_ =
true;
return value;
}
printf(
"Unaligned write at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
int Simulator::storeConditionalD(uint64_t addr, int64_t value,
SimInstruction* instr) {
// Correct behavior in this case, as defined by architecture, is to just
// return 0, but there is no point at allowing that. It is certainly an
// indicator of a bug.
if (addr != LLAddr_) {
printf(
"SC to bad address: 0x%016" PRIx64
", pc=0x%016" PRIx64
", expected: 0x%016" PRIx64
"\n",
addr,
reinterpret_cast<intptr_t>(instr), LLAddr_);
MOZ_CRASH();
}
if ((addr & kPointerAlignmentMask) == 0) {
SharedMem<int64_t*> ptr =
SharedMem<int64_t*>::shared(
reinterpret_cast<int64_t*>(addr));
if (!LLBit_) {
return 0;
}
LLBit_ =
false;
LLAddr_ = 0;
int64_t expected = lastLLValue_;
int64_t old =
AtomicOperations::compareExchangeSeqCst(ptr, expected, int64_t(value));
return (old == expected) ? 1 : 0;
}
printf(
"Unaligned SC at 0x%016" PRIx64
", pc=0x%016" PRIxPTR
"\n", addr,
reinterpret_cast<intptr_t>(instr));
MOZ_CRASH();
return 0;
}
uintptr_t Simulator::stackLimit()
const {
return stackLimit_; }
uintptr_t* Simulator::addressOfStackLimit() {
return &stackLimit_; }
bool Simulator::overRecursed(uintptr_t newsp)
const {
if (newsp == 0) {
newsp = getRegister(sp);
}
return newsp <= stackLimit();
}
bool Simulator::overRecursedWithExtra(uint32_t extra)
const {
uintptr_t newsp = getRegister(sp) - extra;
return newsp <= stackLimit();
}
// Unsupported instructions use format to print an error and stop execution.
void Simulator::format(SimInstruction* instr,
const char* format) {
printf(
"Simulator found unsupported instruction:\n 0x%016lx: %s\n",
reinterpret_cast<intptr_t>(instr), format);
MOZ_CRASH();
}
// Note: With the code below we assume that all runtime calls return a 64 bits
// result. If they don't, the v1 result register contains a bogus value, which
// is fine because it is caller-saved.
ABI_FUNCTION_TYPE_SIM_PROTOTYPES
// Software interrupt instructions are used by the simulator to call into C++.
void Simulator::softwareInterrupt(SimInstruction* instr) {
int32_t func = instr->functionFieldRaw();
uint32_t code = (func == ff_break) ? instr->bits(25, 6) : -1;
// We first check if we met a call_rt_redirected.
if (instr->instructionBits() == kCallRedirInstr) {
#if !
defined(USES_N64_ABI)
MOZ_CRASH(
"Only N64 ABI supported.");
#else
Redirection* redirection = Redirection::FromSwiInstruction(instr);
uintptr_t nativeFn =
reinterpret_cast<uintptr_t>(redirection->nativeFunction());
// Get the SP for reading stack arguments
int64_t* sp_ =
reinterpret_cast<int64_t*>(getRegister(sp));
// Store argument register values in local variables for ease of use below.
int64_t a0_ = getRegister(a0);
int64_t a1_ = getRegister(a1);
int64_t a2_ = getRegister(a2);
int64_t a3_ = getRegister(a3);
int64_t a4_ = getRegister(a4);
int64_t a5_ = getRegister(a5);
int64_t a6_ = getRegister(a6);
int64_t a7_ = getRegister(a7);
float f12_s = getFpuRegisterFloat(f12);
float f13_s = getFpuRegisterFloat(f13);
float f14_s = getFpuRegisterFloat(f14);
float f15_s = getFpuRegisterFloat(f15);
float f16_s = getFpuRegisterFloat(f16);
float f17_s = getFpuRegisterFloat(f17);
float f18_s = getFpuRegisterFloat(f18);
double f12_d = getFpuRegisterDouble(f12);
double f13_d = getFpuRegisterDouble(f13);
double f14_d = getFpuRegisterDouble(f14);
double f15_d = getFpuRegisterDouble(f15);
// This is dodgy but it works because the C entry stubs are never moved.
// See comment in codegen-arm.cc and bug 1242173.
int64_t saved_ra = getRegister(ra);
bool stack_aligned = (getRegister(sp) & (ABIStackAlignment - 1)) == 0;
if (!stack_aligned) {
fprintf(stderr,
"Runtime call with unaligned stack!\n");
MOZ_CRASH();
}
if (single_stepping_) {
single_step_callback_(single_step_callback_arg_,
this, nullptr);
}
switch (redirection->type()) {
ABI_FUNCTION_TYPE_MIPS64_SIM_DISPATCH
default:
MOZ_CRASH(
"Unknown function type.");
}
if (single_stepping_) {
single_step_callback_(single_step_callback_arg_,
this, nullptr);
}
setRegister(ra, saved_ra);
set_pc(getRegister(ra));
#endif
}
else if (func == ff_break && code <= kMaxStopCode) {
if (isWatchpoint(code)) {
printWatchpoint(code);
}
else {
increaseStopCounter(code);
handleStop(code, instr);
}
}
else {
switch (func) {
case ff_tge:
case ff_tgeu:
case ff_tlt:
case ff_tltu:
case ff_teq:
case ff_tne:
if (instr->bits(15, 6) == kWasmTrapCode) {
uint8_t* newPC;
if (wasm::HandleIllegalInstruction(registerState(), &newPC)) {
set_pc(int64_t(newPC));
return;
}
}
};
// All remaining break_ codes, and all traps are handled here.
MipsDebugger dbg(
this);
dbg.debug();
}
}
// Stop helper functions.
bool Simulator::isWatchpoint(uint32_t code) {
return (code <= kMaxWatchpointCode);
}
void Simulator::printWatchpoint(uint32_t code) {
MipsDebugger dbg(
this);
++break_count_;
printf(
"\n---- break %d marker: %20" PRIi64
" (instr count: %20" PRIi64
") ----\n",
code, break_count_, icount_);
dbg.printAllRegs();
// Print registers and continue running.
}
void Simulator::handleStop(uint32_t code, SimInstruction* instr) {
// Stop if it is enabled, otherwise go on jumping over the stop
// and the message address.
if (isEnabledStop(code)) {
MipsDebugger dbg(
this);
dbg.stop(instr);
}
else {
set_pc(get_pc() + 2 * SimInstruction::kInstrSize);
}
}
bool Simulator::isStopInstruction(SimInstruction* instr) {
int32_t func = instr->functionFieldRaw();
uint32_t code = U32(instr->bits(25, 6));
return (func == ff_break) && code > kMaxWatchpointCode &&
code <= kMaxStopCode;
}
bool Simulator::isEnabledStop(uint32_t code) {
MOZ_ASSERT(code <= kMaxStopCode);
MOZ_ASSERT(code > kMaxWatchpointCode);
return !(watchedStops_[code].count_ & kStopDisabledBit);
}
void Simulator::enableStop(uint32_t code) {
if (!isEnabledStop(code)) {
watchedStops_[code].count_ &= ~kStopDisabledBit;
}
}
void Simulator::disableStop(uint32_t code) {
if (isEnabledStop(code)) {
watchedStops_[code].count_ |= kStopDisabledBit;
}
}
void Simulator::increaseStopCounter(uint32_t code) {
MOZ_ASSERT(code <= kMaxStopCode);
if ((watchedStops_[code].count_ & ~(1 << 31)) == 0x7fffffff) {
printf(
"Stop counter for code %i has overflowed.\n"
"Enabling this code and reseting the counter to 0.\n",
code);
watchedStops_[code].count_ = 0;
enableStop(code);
}
else {
watchedStops_[code].count_++;
}
}
// Print a stop status.
void Simulator::printStopInfo(uint32_t code) {
if (code <= kMaxWatchpointCode) {
printf(
"That is a watchpoint, not a stop.\n");
return;
}
else if (code > kMaxStopCode) {
printf(
"Code too large, only %u stops can be used\n", kMaxStopCode + 1);
return;
}
const char* state = isEnabledStop(code) ?
"Enabled" :
"Disabled";
int32_t count = watchedStops_[code].count_ & ~kStopDisabledBit;
// Don't print the state of unused breakpoints.
if (count != 0) {
if (watchedStops_[code].desc_) {
--> --------------------
--> maximum size reached
--> --------------------
