# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id:
http://devicetree.org/schemas/sram/sram.yaml#
$schema:
http://devicetree.org/meta-schemas/core.yaml#
title: Generic on-chip SRAM
maintainers:
- Rob Herring <robh@kernel.org>
description: |+
Simple IO memory regions to be managed by the genalloc API.
Each child of the sram node specifies a region of reserved memory. Each
child node should use a 'reg' property to specify a specific range of
reserved memory.
Following the generic-names recommended practice, node names should
reflect the purpose of the node. Unit address (@<address>) should be
appended to the name.
properties:
$nodename:
pattern: "^sram(@.*)?"
compatible:
contains:
enum:
- mmio-sram
- amlogic,meson-gxbb-sram
- arm,juno-sram-ns
- atmel,sama5d2-securam
- nvidia,tegra186-sysram
- nvidia,tegra194-sysram
- nvidia,tegra234-sysram
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram
reg:
maxItems: 1
clocks:
maxItems: 1
description:
A list of phandle and clock specifier pair that controls the single
SRAM clock.
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
maxItems: 1
description:
Should translate from local addresses within the sram to bus addresses.
no-memory-wc:
description:
The flag indicating, that SRAM memory region has not to be remapped
as write combining. WC is used by default.
type: boolean
patternProperties:
"^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$":
type: object
description:
Each child of the sram node specifies a region of reserved memory.
properties:
compatible:
description:
Should contain a vendor specific string in the form
<vendor>,[<device>-]<usage>
contains:
enum:
- allwinner,sun4i-a10-sram-a3-a4
- allwinner,sun4i-a10-sram-c1
- allwinner,sun4i-a10-sram-d
- allwinner,sun9i-a80-smp-sram
- allwinner,sun50i-a64-sram-c
- amlogic,meson8-ao-arc-sram
- amlogic,meson8b-ao-arc-sram
- amlogic,meson8-smp-sram
- amlogic,meson8b-smp-sram
- amlogic,meson-gxbb-scp-shmem
- amlogic,meson-axg-scp-shmem
- arm,juno-scp-shmem
- arm,scmi-shmem
- arm,scp-shmem
- renesas,smp-sram
- rockchip,rk3066-smp-sram
- samsung,exynos4210-sysram
- samsung,exynos4210-sysram-ns
- socionext,milbeaut-smp-sram
- stericsson,u8500-esram
reg:
description:
IO mem address range, relative to the SRAM range.
maxItems: 1
reg-io-width:
description:
The size (in bytes) of the IO accesses that should be performed on the
SRAM.
enum: [1, 2, 4, 8]
pool:
description:
Indicates that the particular reserved SRAM area is addressable
and in use by another device or devices.
type: boolean
export:
description:
Indicates that the reserved SRAM area may be accessed outside
of the kernel, e.g. by bootloader or userspace.
type: boolean
protect-exec:
description: |
Same as 'pool' above but with the additional constraint that code
will be run from the region and that the memory is maintained as
read-only, executable during code execution. NOTE: This region must
be page aligned on start and end in order to properly allow
manipulation of the page attributes.
type: boolean
label:
description:
The name for the reserved partition, if omitted, the label is taken
from the node name excluding the unit address.
required:
- reg
additionalProperties: false
required:
- compatible
- reg
if:
not:
properties:
compatible:
contains:
enum:
- qcom,rpm-msg-ram
- rockchip,rk3288-pmu-sram
then:
required:
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
sram@5c000000 {
compatible = "mmio-sram";
reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5c000000 0x40000>;
smp-sram@100 {
reg = <0x100 0x50>;
};
device-sram@1000 {
reg = <0x1000 0x1000>;
pool;
};
exported-sram@20000 {
reg = <0x20000 0x20000>;
export;
};
};
- |
// Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
// of the secondary cores. Once the core gets powered up it executes the
// code that is residing at some specific location of the SYSRAM.
//
// Therefore reserved section sub-nodes have to be added to the mmio-sram
// declaration. These nodes are of two types depending upon secure or
// non-secure execution environment.
sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x54000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x54000>;
smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sram@53000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x53000 0x1000>;
};
};
- |
// Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
// Once the core gets powered up it executes the code that is residing at a
// specific location.
//
// Therefore a reserved section sub-node has to be added to the mmio-sram
// declaration.
sram@d9000000 {
compatible = "mmio-sram";
reg = <0xd9000000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xd9000000 0x20000>;
smp-sram@1ff80 {
compatible = "amlogic,meson8b-smp-sram";
reg = <0x1ff80 0x8>;
};
};
- |
sram@e63c0000 {
compatible = "mmio-sram";
reg = <0xe63c0000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe63c0000 0x1000>;
smp-sram@0 {
compatible = "renesas,smp-sram";
reg = <0 0x10>;
};
};
- |
sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
smp-sram@10080000 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x10080000 0x50>;
};
};
- |
// Rockchip's rk3288 SoC uses the sram of pmu to store the function of
// resume from maskrom(the 1st level loader). This is a common use of
// the "pmu-sram" because it keeps power even in low power states
// in the system.
sram@ff720000 {
compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
reg = <0xff720000 0x1000>;
};
- |
// Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
// primary core (cpu0). Once the core gets powered up it checks if a magic
// value is set at a specific location. If it is then the BROM will jump
// to the software entry address, instead of executing a standard boot.
//
// Also there are no "secure-only" properties. The implementation should
// check if this SRAM is usable first.
sram@20000 {
// 256 KiB secure SRAM at 0x20000
compatible = "mmio-sram";
reg = <0x00020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00020000 0x40000>;
smp-sram@1000 {
// This is checked by BROM to determine if
// cpu0 should jump to SMP entry vector
compatible = "allwinner,sun9i-a80-smp-sram";
reg = <0x1000 0x8>;
};
};
- |
sram@0 {
compatible = "mmio-sram";
reg = <0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x10000>;
smp-sram@f100 {
compatible = "socionext,milbeaut-smp-sram";
reg = <0xf100 0x20>;
};
};
