Quelle  cdns,usb3.yaml   Sprache: unbekannt

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence USBSS-DRD controller

maintainers:
  - Pawel Laszczak <pawell@cadence.com>

properties:
  compatible:
    const: cdns,usb3

  reg:
    items:
      - description: OTG controller registers
      - description: XHCI Host controller registers
      - description: DEVICE controller registers

  reg-names:
    items:
      - const: otg
      - const: xhci
      - const: dev

  interrupts:
    minItems: 3
    items:
      - description: XHCI host controller interrupt
      - description: Device controller interrupt
      - description: OTG/DRD controller interrupt
      - description: interrupt used to wake up core, e.g when usbcmd.rs is
                     cleared by xhci core, this interrupt is optional

  interrupt-names:
    minItems: 3
    items:
      - const: host
      - const: peripheral
      - const: otg
      - const: wakeup

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      This port is used with the 'usb-role-switch' property to connect the
      cdns3 to type C connector.

  maximum-speed:
    enum: [super-speed, high-speed, full-speed]

  phys:
    minItems: 1
    maxItems: 2

  phy-names:
    minItems: 1
    maxItems: 2
    items:
      anyOf:
        - const: cdns3,usb2-phy
        - const: cdns3,usb3-phy

  cdns,on-chip-buff-size:
    description:
      size of memory intended as internal memory for endpoints
      buffers expressed in KB
    $ref: /schemas/types.yaml#/definitions/uint16

  cdns,phyrst-a-enable:
    description: Enable resetting of PHY if Rx fail is detected
    type: boolean

dependencies:
  port: [ usb-role-switch ]

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names

allOf:
  - $ref: usb-drd.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        usb@6000000 {
            compatible = "cdns,usb3";
            reg = <0x00 0x6000000 0x00 0x10000>,
                  <0x00 0x6010000 0x00 0x10000>,
                  <0x00 0x6020000 0x00 0x10000>;
            reg-names = "otg", "xhci", "dev";
            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "host", "peripheral", "otg";
            maximum-speed = "super-speed";
            dr_mode = "otg";
        };
    };