/* * This is the logout header that should be common to all platforms * (assuming they are running OSF/1 PALcode, I guess).
*/ struct el_common { unsignedint size; /* size in bytes of logout area */ unsignedint sbz1 : 30; /* should be zero */ unsignedint err2 : 1; /* second error */ unsignedint retry : 1; /* retry flag */ unsignedint proc_offset; /* processor-specific offset */ unsignedint sys_offset; /* system-specific offset */ unsignedint code; /* machine check code */ unsignedint frame_rev; /* frame revision */
};
/* Machine Check Frame for uncorrectable errors (Large format) * --- This is used to log uncorrectable errors such as * double bit ECC errors. * --- These errors are detected by both processor and systems.
*/ struct el_common_EV5_uncorrectable_mcheck { unsignedlong shadow[8]; /* Shadow reg. 8-14, 25 */ unsignedlong paltemp[24]; /* PAL TEMP REGS. */ unsignedlong exc_addr; /* Address of excepting instruction*/ unsignedlong exc_sum; /* Summary of arithmetic traps. */ unsignedlong exc_mask; /* Exception mask (from exc_sum). */ unsignedlong pal_base; /* Base address for PALcode. */ unsignedlong isr; /* Interrupt Status Reg. */ unsignedlong icsr; /* CURRENT SETUP OF EV5 IBOX */ unsignedlong ic_perr_stat; /* I-CACHE Reg. <11> set Data parity
<12> set TAG parity*/ unsignedlong dc_perr_stat; /* D-CACHE error Reg. Bits set to 1: <2> Data error in bank 0 <3> Data error in bank 1 <4> Tag error in bank 0
<5> Tag error in bank 1 */ unsignedlong va; /* Effective VA of fault or miss. */ unsignedlong mm_stat; /* Holds the reason for D-stream
fault or D-cache parity errors */ unsignedlong sc_addr; /* Address that was being accessed when EV5 detected Secondary cache
failure. */ unsignedlong sc_stat; /* Helps determine if the error was
TAG/Data parity(Secondary Cache)*/ unsignedlong bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */ unsignedlong ei_addr; /* Physical address of any transfer
that is logged in EV5 EI_STAT */ unsignedlong fill_syndrome; /* For correcting ECC errors. */ unsignedlong ei_stat; /* Helps identify reason of any processor uncorrectable error
at its external interface. */ unsignedlong ld_lock; /* Contents of EV5 LD_LOCK register*/
};
struct el_common_EV6_mcheck { unsignedint FrameSize; /* Bytes, including this field */ unsignedint FrameFlags; /* <31> = Retry, <30> = Second Error */ unsignedint CpuOffset; /* Offset to CPU-specific info */ unsignedint SystemOffset; /* Offset to system-specific info */ unsignedint MCHK_Code; unsignedint MCHK_Frame_Rev; unsignedlong I_STAT; /* EV6 Internal Processor Registers */ unsignedlong DC_STAT; /* (See the 21264 Spec) */ unsignedlong C_ADDR; unsignedlong DC1_SYNDROME; unsignedlong DC0_SYNDROME; unsignedlong C_STAT; unsignedlong C_STS; unsignedlong MM_STAT; unsignedlong EXC_ADDR; unsignedlong IER_CM; unsignedlong ISUM; unsignedlong RESERVED0; unsignedlong PAL_BASE; unsignedlong I_CTL; unsignedlong PCTX;
};
#endif/* __ALPHA_MCE_H */
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