Quelle  hi3519.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
 */

#include <dt-bindings/clock/hi3519-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
 #address-cells = <1>;
 #size-cells = <1>;
 chosen { };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a7";
   reg = <0>;
  };
 };

 gic: interrupt-controller@10300000 {
  compatible = "arm,cortex-a7-gic";
  #interrupt-cells = <3>;
  interrupt-controller;
  reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
 };

 clk_3m: clk_3m {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  clock-frequency = <3000000>;
 };

 crg: clock-reset-controller@12010000 {
  compatible = "hisilicon,hi3519-crg";
  #clock-cells = <1>;
  #reset-cells = <2>;
  reg = <0x12010000 0x10000>;
 };

 soc {
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "simple-bus";
  interrupt-parent = <&gic>;
  ranges;

  uart0: serial@12100000 {
   compatible = "arm,pl011", "arm,primecell";
   reg = <0x12100000 0x1000>;
   interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>;
   clock-names = "uartclk", "apb_pclk";
   status = "disabled";
  };

  uart1: serial@12101000 {
   compatible = "arm,pl011", "arm,primecell";
   reg = <0x12101000 0x1000>;
   interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>;
   clock-names = "uartclk", "apb_pclk";
   status = "disabled";
  };

  uart2: serial@12102000 {
   compatible = "arm,pl011", "arm,primecell";
   reg = <0x12102000 0x1000>;
   interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>;
   clock-names = "uartclk", "apb_pclk";
   status = "disabled";
  };

  uart3: serial@12103000 {
   compatible = "arm,pl011", "arm,primecell";
   reg = <0x12103000 0x1000>;
   interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>;
   clock-names = "uartclk", "apb_pclk";
   status = "disabled";
  };

  uart4: serial@12104000 {
   compatible = "arm,pl011", "arm,primecell";
   reg = <0x12104000 0x1000>;
   interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>;
   clock-names = "uartclk", "apb_pclk";
   status = "disabled";
  };

  dual_timer0: timer@12000000 {
   compatible = "arm,sp804", "arm,primecell";
   interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
   reg = <0x12000000 0x1000>;
   clocks = <&clk_3m>;
   clock-names = "apb_pclk";
   status = "disabled";
  };

  dual_timer1: timer@12001000 {
   compatible = "arm,sp804", "arm,primecell";
   interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
   reg = <0x12001000 0x1000>;
   clocks = <&clk_3m>;
   clock-names = "apb_pclk";
   status = "disabled";
  };

  dual_timer2: timer@12002000 {
   compatible = "arm,sp804", "arm,primecell";
   interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
   reg = <0x12002000 0x1000>;
   clocks = <&clk_3m>;
   clock-names = "apb_pclk";
   status = "disabled";
  };

  spi_bus0: spi@12120000 {
   compatible = "arm,pl022", "arm,primecell";
   reg = <0x12120000 0x1000>;
   interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>;
   clock-names = "sspclk", "apb_pclk";
   num-cs = <1>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  spi_bus1: spi@12121000 {
   compatible = "arm,pl022", "arm,primecell";
   reg = <0x12121000 0x1000>;
   interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>;
   clock-names = "sspclk", "apb_pclk";
   num-cs = <1>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  spi_bus2: spi@12122000 {
   compatible = "arm,pl022", "arm,primecell";
   reg = <0x12122000 0x1000>;
   interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>;
   clock-names = "sspclk", "apb_pclk";
   num-cs = <1>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  sysctrl: system-controller@12020000 {
   compatible = "hisilicon,hi3519-sysctrl", "syscon";
   reg = <0x12020000 0x1000>;
  };

  reboot {
   compatible = "syscon-reboot";
   regmap = <&sysctrl>;
   offset = <0x4>;
   mask = <0xdeadbeef>;
  };
 };
};