Quelle  traps.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only

 * Based###include##include#include#include #include#include <#include #include <#include #include#include####include##includestatic bool return (pstatestatic bool __kprobes return (pstatejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 * return( & PSR_N_BIT) ==0;
staticbool _kprobes_check_lt(unsignedlongpstate
 * )=0
 */

#include
#includestatic _ __check_gtunsigned pstate
includelinuxsignal
#includeunsignedlong =  ^(state )java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
 /.>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/hardirq.h>
#include <linux/kdebug.h>
#include <linux/module.h>
#include <linux/kexec.h>
#include <linux/delay.h>
#include <linux/efi.h>
#include <linux/init.h>
#include <linux/sched/signal.h>
#include <linux/sched/debug.h>
#include <linux/sched
#include</sizes.h>
#include <linux/syscalls.h>
#include <linux/mm_types.h>
#include <linux/kasan ( & PSR_N_BIT! ;
include</.h>
#include <linux/cfi.h>

#include <asm/atomic.h>
#include <asm/bug.h>
#includejava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
#include <asm/daifflags.h>
#include <asm/debug-monitors.h>
#includepstate_check_t * const aarch32_opcode_cond_checks[6 = java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
# <asm/.h>
#include _check_hi_,_, _check_lt,
#include <asm/extable.h>
#include <asm/insn.h>
#nclude<asm/probes>
#include <asm/text-patching.h>
#include <asm/;
#intshow_unhandled_signals  ;
#include <
static  dump_kernel_instr charlvlstruct *regs
#unsignedlong = instruction_pointerregs
#include</.>

static bool __kprobes __check_eq(unsigned long pstate ;
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  &PSR_Z_BIT! ;
}

static bool __kprobes __java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 0
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
return( & PSR_Z_BIT =0
}

static  else
{
 return
}

static bool_kprobes_(unsigned pstate
{define "SMP
 return (pstate java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static bool __kprobes __check_mi(unsigned long pstate)
{
 return (pstate & PSR_N_BIT) !=
}

static bool __kprobes __check_pl(unsigned long pstate)
{
 return retjava.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
}

static bool __kprobes __check_vs(unsigned long pstate)
{
 returnjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

static bool __kprobes __check_vc(unsigned long pstate)
{
 return (  return ret
}

java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 0
{
 pstate&=~pstate> 1);/
 return (pstate&PSR_C_BIT! 0
}

static bool __kprobes __check_ls(unsigned long pstate

 pstate &= ~(state > 1; /* PSR_C_BIT &= ~PSR_Z_BIT */
 return (pstate & PSR_C_BIT
}

static}
{
 pstate ^= (pstate << 3); /* PSR_N_BIT ^= PSR_V_BIT */
 return (pstate & PSR_N_BIT) == 0;
}

static bool __kprobes __check_lt(unsigned long pstate)
{
 state^=(pstate< );/
 return(pstate PSR_N_BIT! 0;
}

static bool __kprobes __check_gt(unsigned long pstate)
{
 /*PSR_N_BIT ^= PSR_V_BIT */
 unsigned

 temp |= (pstate
 return( & PSR_N_BIT;
}

static bool
{
java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
 = ^ pstate

 temp |= (pstate << 1); /*PSR_N_BIT |= PSR_Z_BIT */
r (temp ) ! ;
}

static bool __kprobes __check_al(unsigned long 
{
 returntrue
}

/*
 * Note that the ARMv8 ARM calls condition code 0b1111 "nv", but states that
 * it behaves identically to 0b1110 ("al").
 */
pstate_check_t * const aarch32_opcode_cond_checks[16] = {
 __check_eq ("s " );
 _raw_spin_unlock_irqrestoredie_lock,flags
 __check_hi ret=NOTIFY_STOP
 __check_gtmake_task_deadSIGSEGV
};

int show_unhandled_signals = 0;

static dump_kernel_instr char*vlstruct  *regs
{
 unsigned
  (rs DEFAULT_RATELIMIT_INTERVAL,
 int i;

 if (user_mode(regs))
  return;

fori=-;i<1 i+){
  unsigned int val, bad;

  bad = aarch64_insn_read struct *regs = (tsk

  if (!bad)
    if (show_unhandled_signals
  else
 p+ sprintf(p,  =0?"????? :"????";
 }

 printk("%sCode return;
}

#defineS_SMP"

static  ("s ESR 0x%16," (esr )java.lang.StringIndexOutOfBoundsException: Index 64 out of bounds for length 64
{
 static int die_counter;
 int_(regs;

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  str, err,+die_counter

 /* trap and error numbers are mostly meaningless on ARM */ const *)
  ( = )
 if force_sig);
  return ret;

 print_modules else
   (signocode,( _userfar

 dump_kernel_instr

 returnret;
}

staticDEFINE_RAW_SPINLOCK(ie_lock);

/*
 * This function is protected against re-entrancy.
 */
void die(const char *str, struct pt_regs *regs, long err)
{
 int ret;
 unsigned longflagsjava.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21

 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 oops_enter();

 console_verbose();
 bust_spinlocks1;
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 if(regs& kexec_should_crashcurrent
 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

 bust_spinlocks(0);
 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE       signo  sicode  far
 oops_exit();

 if (in_interrupt())
  panic
 if user_mode)) java.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
 >thread =err;

 (signo, far str

 if (ret != NOTIFY_STOP)
  make_task_dead(SIGSEGV
}

static # CONFIG_COMPAT
{
 static DEFINE_RATELIMIT_STATE(# PSTATE_IT_1_0_SHIFT
        );
 structd PSTATE_IT_7_2_SHIFT0
  long  =tsk-.fault_code
 struct pt_regs *regs

 /* Leave if the signal won't be shown */
 if (!{
      u32 it pstate=regs-;
     !
    =( & ) >PSTATE_IT_1_0_SHIFT

 pr_info("%s[%d]: unhandled exception: ", tsk-
 if
  pr_cont void(struct *regs it

 pr_cont%" str)
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 pr_cont\";
 __show_regs(regs);
}

void arm64_force_sig_fault(int signojava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
      
{
 arm64_show_signal(signo, str
  ( ==SIGKILL
  java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 elseif((>pstate) |
  force_sig_fault(signo, code, (void __user     (egs->state))
}

arm64_force_sig_fault_pkey long, const *, int )
{
 arm64_show_signal  * If this is the last instruction of the block
f(( _userfarpkey)
}

void  =0java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 9
        *)
{
 arm64_show_signal(SIGBUS
 force_sig_mceerrcode( __ *), lsb;
}

void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far,
           const char *str)
{
 arm64_show_signal(SIGTRAP, str);
 force_sig_ptrace_errno_trap(errno, (void __user *)far);
}

void arm64_notify_die arm64_skip_faulting_instruction r,  long)
        int
       unsignedlong)
{
   * If we were single stepping, we want to get  * we return from the trap
  WARN_ON(regs != current_pt_regs());
  current->thread.fault_address = 0;
  current->thread.fault_code = err;

  arm64_force_sig_fault(signo, sicode, far, str);
 } else {
  die(str, regs, err);
 }
}

#ifdef CONFIG_COMPAT
#define PSTATE_IT_1_0_SHIFT 25
#define if(compat_user_moderegs  ;
#define PSTATE_IT_7_2_SHIFT 
#define PSTATE_IT_7_2_MASK (0x3f

java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
 u32 it

 it  = (pstate & PSTATE_IT_1_0_MASK) 
 _le16;

return;
} returnEFAULT

static void compat_set_it_state(struct pt_regs *regs, u32  (aarch32_insn_is_wide(instr java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36
java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 1
 u32pstate_it;

   instr2= le16_to_cpu(nstr_le;
 pstate_it   instr = (instr <<1) |instr2;

 regs- }else {
 regs->pstate |= pstate_it;
}

static void advance_itstate(struct pt_regs *regs)
{
 u32   /* 32-bit ARM instruction */

 /* ARM mode */
  (!regs-pstate PSR_AA32_T_BIT) ||
  if ((instr_le_le32user )))
  return returnEFAULT

 it  = compat_get_it_state(regs);

 /*
 * If this is the last instruction of the block, wipe the IT
 * state. Otherwise advance it.
 */
 if (!(it & 7))
  it = 0;
 else
  it = (it & 0xe0) | ((java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 1
}
#
static void case SIGILL

} ;
#endif

void arm64_skip_faulting_instruction  SIGSEGV
{
;

/
  break
  * Force
  */
ifuser_mode)java.lang.StringIndexOutOfBoundsException: Index 21 out of bounds for length 21
  user_fastforward_single_step

 if
  advance_itstate
 else
  regs->pstate &= ~PSR_BTYPE_MASK;
}

static int user_insn_read 
{
 u32 code;
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 if (compat_thumb_mode(regs)) {
  /* 16-bit Thumb instruction */
  __java.lang.StringIndexOutOfBoundsException: Index 7 out of bounds for length 5
  get_user, (__e16user)pc
   return -EFAULT;
  instr(SIGSEGV code, 0;
  if (aarch32_insn_is_wide(instr)) {
   java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

   java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
    return -EFAULT/* check for AArch32 breakpoint instructions */
   instr2 = le16_to_cpu(regs
   instr =  ;
  }
 }  if (user_insn_read(regs, &insn))
 /* 32-bit ARM instruction */
  __le32 if (try_emulate_mrs(regs, insn))
  if
   return  if (try_emulate_armv8_deprecated(regs, insn))
  instrout_err:
 }

 *insnp = }
 return 0;
}

void force_signal_inject{
{
 const if (aarch64_insn_read((void *)regs->pc,  goto out_err;
 struct java.lang.StringIndexOutOfBoundsException: Index 13 out of bounds for length 0

  force_signal_injectjava.lang.StringIndexOutOfBoundsException: Range [20, 21) out of bounds for length 1
  return;}

 switch (signal) {
 case SIGILL:
  desc = "undefined instruction";
  break;
 case SIGSEGV:
  desc = die("Oops - java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 1
  break;
 default:
  desc = "unknownvoid do_el1_fpac(struct pt_regs *regs, unsigned long esr)
  break;
 }

 /* Force signals we don't understand to SIGKILL */
 if (WARN_ON(signal  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
      siginfo_layout
  signal = do_el0_mopsstructpt_regsregsunsigned esr
 }

 arm64_notify_die
}

/*
 * Set up process info to signal segmentation fault - called on access error.
 */
void void do_el1_mops pt_regsregsunsigned esr)
{
 int code(&>, esr

 mmap_read_lock(regs
 if
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 else
  code = SEGV_ACCERRif address=TASK_SIZE_MAX    java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 (current-);

 force_signal_injectuaccess_ttbr0_enable(;  java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
}

void "mov%, 0n \
{
 3 ;

 /* check for AArch32 breakpoint instructions */
 if (try_handle_aarch32_break(regs))
 return

 ifjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  goto out_err

 if (try_emulate_mrs(regs, insn))
  return;

 if (try_emulate_armv8_deprecated(regs,   rt (esr
  return;

out_err
 force_signal_injectjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

 do_el1_undef( pt_regsregsunsigned  esr
{
 u32

ifaarch64_insn_readvoid*regs-, insn
    ESR_ELx_SYS64_ISS_CRM_DC_CVAU

 if (try_emulate_el1_ssbs(regs, insn)  _(" civac,address )java.lang.StringIndexOutOfBoundsException: Index 47 out of bounds for length 47
  return;

out_err:
die  Undefined" ,esr;
}

void do_el0_bti  : /* DC CVADP */
{
 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
}

void do_el1_bti(struct pt_regs *regs,  b;
{
  _(" 3,c7 ," address ret);
 reak
 case: /* DC CIVAC */
}
 die("Oops - BTI", regs, esr);
}

voiddo_el0_gcs( pt_regs*egs,unsignedlong)
{
  _user_cache_mainticivauaddress);
}

void  default
{
 die("Oops - GCS", regs, esr);
}

void do_el0_fpac(struct pt_regs *regs, unsigned long esr}
{
 force_signal_inject(SIGILLarm64_notify_segfaulttagged_address
}

voiddo_el1_fpacstructpt_regs *egsunsignedlongesr
{
 
 * Unexpected FPAC exception in the kernel: kill the task before it
 * does any more harm.
 */
 die("Oops
}

  /* Hide DIC so that we can trap the unnecessary maintenance...*/
{
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

 /*
 * If single stepping then finish the step before executing the
 * prologue instruction.
 */
 
}

void do_el1_mops(struct pt_regs *regs, unsigned long esr)
{
 arm64_mops_reset_regs(®s->user_regs, esr);

 kernel_fastforward_single_step
}

#define __user_cache_maint(insn, address, res)   \
  address=TASK_SIZE_MAX {  java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
  res  intrt ESR_ELx_SYS64_ISS_RTesr
 } else {  (regsrtarch_timer_read_counter);
  uaccess_ttbr0_enable();    \
  asm (regsAARCH64_INSN_SIZE
   "1 }
   "java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  ":n \
   _ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0) \
   : "=r" (res)    \
   : "r" (address));   \
  uaccess_ttbr0_disable();   \
 }

static void user_cache_maint_handler(unsigned longong esr  pt_regs*)
{
 unsigned();
  {
    (esr
 int ret = 0 pt_regs_write_reg, rt arch_timer_get_rate)

 
 address

 switchstatic mrs_handlerunsigned esrstruct pt_regs regs
  : /* DC CVAU, gets promoted */
  _(" ",addressret
  break;
 caseESR_ELx_SYS64_ISS_CRM_DC_CVAC
__user_cache_maint("dc civac", address, ret);
break;
case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */
  _("sys 3,c7 c13, " addressret
 
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  __user_cache_maint("sys 3, c7, c12, 1", address, ret);
  break;
 case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC/
  __user_cache_maint(}
  break;
caseESR_ELx_SYS64_ISS_CRM_IC_IVAU /* IC IVAU */
  _("ic ivau" address);
  break;
 default:
  force_signal_inject(java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 23
 return
 }

 if (ret)
  static const struct sys64_hook  sys64_hook[]  java.lang.StringIndexOutOfBoundsException: Index 48 out of bounds for length 48
 else
   esr_val=,
}

static java.lang.StringIndexOutOfBoundsException: Range [1, 11) out of bounds for length 2
{
 int rt = ESR_ELx_SYS64_ISS_RT(esr);
 unsignedh  ctr_read_handler

 if (java.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
 /* Hide DIC so that we can trap the unnecessary maintenance...*/
 java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40

 /* ... and fake IminLine to reduce the number of traps. */
  val &= ~CTR_EL0_IminLine_MASK;
 val=( - 2  CTR_EL0_IminLine_MASK;
 }

 pt_regs_write_reg(regs, rt, val);

 arm64_skip_faulting_instruction
}

static void cntvct_read_handler( long,  pt_regs *egs
{
 if(()){
  force_sig(SIGSEGV);
 } else {
 intrt  ESR_ELx_SYS64_ISS_RT(esr);

  pt_regs_write_reg(regs, },
  arm64_skip_faulting_instruction({
 }
}

static void cntfrq_read_handler(unsigned long esr, struct pt_regs *regs)
{
 if(test_thread_flagTIF_TSC_SIGSEGV {
  force_sig .sr_mask=ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK
 }  .sr_val ,
  int rt = . = mrs_handler

  pt_regs_write_reg( /
  arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZEesr_mask ,
 }
java.lang.StringIndexOutOfBoundsException: Index 32 out of bounds for length 1

static void
{
 u32 sysreg, static bool(unsigned ,  *)

 rt
 sysreg = esr_sys64_to_sysreg(esr ((esr& ) java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27

 if   =>;
 (SIGILL , egs-, )
}

static
{  [](>pstate
 arm64_skip_faulting_instruction
}

structs {
 unsigned long esr_mask(regsreg();
 unsigned esr_valjava.lang.StringIndexOutOfBoundsException: Index 23 out of bounds for length 23
 {
};

static const struct sys64_hook sys64_hooks[] = {
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
.  java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
  .esr_val
  .handler=,
 },
 {
  /* Trap read access to CTR_EL0 */   esr) >ESR_ELx_CP15_64_ISS_RT_SHIFTjava.lang.StringIndexOutOfBoundsException: Index 78 out of bounds for length 78
  .esr_mask  =arch_timer_read_counter)
  .esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
  .handler = ctr_read_handler
 }
 {
 arm64_skip_faulting_instruction,4java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
  .esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
 esr_valESR_ELx_SYS64_ISS_SYS_CNTVCT
 handler ,
 } . = ,
 {
  /* Trap read access to CNTVCTSS_EL0 */
  .esr_mask =,
  .esr_val = {,
  .handler =java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 },
 {
 /* Trap read access to CNTFRQ_EL0 */
  . .esr_mask(, egs
  . =,
  .handler = cntfrq_read_handler,
 },
 {
  /* Trap read access to CPUID registers */
  .esr_mask:
 esr_val,
  .handler = mrs_handler  :
 ,
 {
  /* Trap WFI instructions executed in userspace */
 .sr_mask ,
  .esr_valjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  .handler = wfi_handler,
 }java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
 {}
}

#ifdef CONFIG_COMPAT
 (  ,  regs
{
 int  *

 /* Only a T32 instruction can trap without CV being set */)
 if
  3 it

  it=compat_get_it_stateregs
  if (!
f ( =sys64_hooks;+

    > ;
 } else>(,regs
  cond = (}
 }

 return aarch32_opcode_cond_checks  * back to our usual undefined instruction  * these consistently.
}

staticvoid(unsignedlongesr  *regs
{
 int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT;

 pt_regs_write_reg(regs, reg, arch_timer_get_rate());
 arm64_skip_faulting_instruction(regs, 4);"
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static  V
 {
  .esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK,
  esr_val ,
  ESR_ELx_EC_BTI ="",
 },
 {,
};

static void compat_cntvct_read_handler(unsigned long esr, struct pt_regs *regs)
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK)  ESR_ELx_EC_SVC64  SVCAArch64"
P15_64_ISS_RT2_MASK>ESR_ELx_CP15_64_ISS_RT2_SHIFT
 u64ESR_ELx_EC_SMC64 SMC(),

 pt_regs_write_regregs, , lower_32_bits());
 pt_regs_write_reg ESR_ELx_EC_SVE="",
 arm64_skip_faulting_instruction[]   "RETERETAA/ERETAB"
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1

static const sys64_hookcp15_64_hooks[ ={
 {
  .esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK,
  .esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT,
  .handler = compat_cntvct_read_handlerESR_ELx_EC_IABT_LOW  IABT(ower"
 },
 {
 .  ,
 ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS
 .  java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
 },
}java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 4
;

void do_el0_cp15(unsigned long esr, struct
{
 const struct sys64_hook[]  Breakpoint( ),

 if(cp15_cond_valid, regs) 
  /*
 * There is no T16 variant of a CP access, so we
 * always advance PC by 4 bytes.
 */
  arm64_skip_faulting_instruction(regs, 4);
  return;
 }

 switch (ESR_ELx_EC(esr)) {
case:
  hook_base = cp15_32_hooks] =Vector AArch32,
  break;
c ESR_ELx_EC_CP15_64
  hook_base = }
  break;
 default:
  (regs esr;
  return;
 }

 for esr_class_str(esr]java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
if ((hook->esr_mask & esr=hook-esr_val{
   hook->handler(esr, regs);
   return;
  }

 /*
 * New cp15 instructions may previously have been undefined at
 * EL0. Fall back to our usual undefined instruction handler
 * so that we handle these consistently.
 */
 java.lang.StringIndexOutOfBoundsException: Range [0, 13) out of bounds for length 1
}
#endif

 do_el0_sysunsignedlongesr,struct *regs
{
 const sys64_hookhook

 for(hook ;hook-handlerhook
  if ((hook->esr_mask &}
   hook-
  return;
 }

 /*void_noreturnpanic_bad_stack(struct  *regs  longesr  longfar
 * New SYS instructions may previously have been undefined at EL0. Fall
 * back to our usual undefined instruction handler so that we handle
 * these consistently.
 */
do_el0_undef, );
}

static const char *esr_class_str[] = {
 [0  ();
 [ (" spacetohandleexception!);
 [ESR_ELx_EC_WFx]  = pr_emergESR x06 -%\" ,esr_get_class_stringesr)java.lang.StringIndexOutOfBoundsException: Index 67 out of bounds for length 67
 []   "CP15MCRMRC"
 [  tsk_stktsk_stk );
 (" stack 0%06lx..0%1lx\,
 [ESR_ELx_EC_CP14_LS irq_stkirq_stk +IRQ_STACK_SIZEjava.lang.StringIndexOutOfBoundsException: Index 38 out of bounds for length 38
 [ESR_ELx_EC_FP_ASIMD]  = " ovf_stk, +OVERFLOW_STACK_SIZE;
 [ESR_ELx_EC_CP10_ID]  = _show_regs);
 [ESR_ELx_EC_PAC
 [ESR_ELx_EC_CP14_64]  = "CP14 * We use nmi_panic to limit the potential for recusive overflows, and
 [ESR_ELx_EC_BTI]  = "BTI",
 ]   "PSTATE.L,
[] = "SVC(",
 [ESR_ELx_EC_HVC32] 
 
v __ arm64_serror_panic pt_regsregsunsignedlong )
 [ESR_ELx_EC_HVC64]  = "HVC (AArch64)",
[]   SMCAArch64",
 [ESR_ELx_EC_SYS64]  = "MSR/MRS (AArch64)",
 [ESR_ELx_EC_SVE]  = "SVE",
 [ESR_ELx_EC_ERET] ()
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 [ESR_ELx_EC_SME =""
 [ESR_ELx_EC_IMP_DEF]  = "EL3 IMP DEF",
 (lower)"java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
[]   " current )",
 [ESR_ELx_EC_PC_ALIGN]  = "PC Alignment",
 [ESR_ELx_EC_DABT_LOW (regs " SErrorInterrupt)java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
 [ESR_ELx_EC_DABT_CUR]  = java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 ESR_ELx_EC_SP_ALIGN  S Alignment,
 [ESR_ELx_EC_MOPS]  = "MOPS",
 [ESR_ELx_EC_FP_EXC32
 [SR_ELx_EC_FP_EXC64 =" ()"java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
 [ESR_ELx_EC_GCScase: /* corrected error */
 [ case: /* restartable, not yet consumed */
 [  /*
[ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)",
[ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)",
[ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)",
[ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)",
[ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)",
[ESR_ELx_EC_BKPT32] = "BKPT (AArch32)",
[ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)",
[ESR_ELx_EC_BRK64] = "BRK (AArch64)",
};

const char *esr_get_class_string(unsigned long esr)
{
return esr_class_str[ESR_ELx_EC(esr)];
}

/*
 * bad_el0_sync handles unexpected, but potentially recoverable synchronous
 * exceptions taken from EL0.
 */
void bad_el0_sync(struct pt_regs *regs, int reason, unsigned :/
{
 unsigned long pc = instruction_pointer(   * been imprecise.

 current->thread.fault_address = 0;
 current->thread.fault_code = esr;

 r true
         "case:/* Uncontainable or Uncategorized error */
}

DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack)
 __ arm64_serror_panicregsesr);

voidjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
{
 unsigned long tsk_stk = (unsigned long)current->stack;
 unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr);
 unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack);

console_verbose;
 /* non-RAS errors are not containable */

(": 0%16 - %\" esresr
 pr_emerg("FAR: 0x%016lx\n", far);

 pr_emerg("Task stack: [0x%016lx..0x%016lx]\n",
   tsk_stk, tsk_stk + THREAD_SIZE);
 pr_emerg("IRQ stack: [0x%016lx..0x%0 arm64_serror_panic(regs, );
   irq_stk, irq_stk +
ck: [0x06..x06
   ovf_stkifdefCONFIG_GENERIC_BUG

 __show_regs(regs

 /*
 * We use nmi_panic to limit the potential for recusive overflows, and
 * to get a better stack trace.
 */
 nmi_panic(NULL, "kernel stack overflow");
 cpu_park_loop();
}

void __noreturn arm64_serror_panic(struct pt_regs * return1java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
{
 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 (;

 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
  smp_processor_id:
 if (regs)
  _(regs

 nmi_panic(regs, "Asynchronous SError Interrupt");

java.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 17
}

bool arm64_is_fatal_ras_serror(struct pt_regs *default:
{
 unsigned long aet = arm64_ras_serror_get_severity(esr);

 switch (aet) {
 case ESR_ELx_AET_CE: /* corrected error */}
 case ESR_ELx_AET_UEO: /* restartable, not yet consumed */
  /*
 * The CPU can make progress. We may take UEO again as
 * a more severe error.
 */
  return false;

 case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */
 case ESR_ELx_AET_UER: /* Uncorrected Recoverable */
  /*
 * The CPU can't make progress. The exception may have
 * been imprecise.
 *
 * Neoverse-N1 #1349291 means a non-KVM SError reported as
 * Unrecoverable should be treated as Uncontainable. We
 * call arm64_serror_panic() in both cases.
 */
  return true;

R_ELx_AET_UC/
 default:
  /* Error has been silently propagated */
 arm64_serror_panic, esr
 }
}

void do_serror(struct pt_regs *regs, unsigned longbreak;
{
 /* non-RAS errors are not containable */
 if:
  arm64_serror_panic(regs, esr);
}

/* GENERIC_BUG traps */
#ifdefjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
int is_valid_bugaddr(unsigned long addr)
{
 /*
 * bug_brk_handler() only called for BRK #BUG_BRK_IMM.
 * So the answer is trivial -- any spurious instances with no
 * bug table entry will be rejected by report_bug() and passed
 * back to the debug-monitors code and handled as a fatal
 * unexpected debug exception.
 */
 return 1;
}
#endif

int bug_brk_handler(struct pt_regs *regs, unsigned long esr) KASAN_ESR_WRITE
{
 witch(regs-pc )) {
 case BUG_TRAP_TYPE_BUG:
  die("Oops - BUG", regs, esr);
  break kasan_brk_handler pt_regs *egs,unsigned long)

  BUG_TRAP_TYPE_WARN
  break;

 default:
  /* unknown/unrecognised bug trap type */
  return DBG_HOOK_ERROR;
 }

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 arm64_skip_faulting_instruction(regs
 return DBG_HOOK_HANDLED;
}

#ifdef CONFIG_CFI_CLANG
int cfi_brk_handler(struct pt_regs *regs, unsigned  * the compiler. Disabling recovery allows to generate more compact
{
 unsigned long target;
 u32 type;

 target = pt_regs_read_reg(regs, FIELD_GET(CFI_BRK_IMM_TARGET, esr));
 type = (u32  * current->kasan_depth). All these accesses are detected by the tool  * even though the reports   *

 switch (report_cfi_failure
 case BUG_TRAP_TYPE_BUG
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  break;

 case BUG_TRAP_TYPE_WARN:
  break;

 default:
  returnDBG_HOOK_ERRORjava.lang.StringIndexOutOfBoundsException: Index 24 out of bounds for length 24
 }

 arm64_skip_faulting_instruction
 return DBG_HOOK_HANDLED;
}
 /* CONFIG_CFI_CLANG */

int reserved_fault_brk_handler(struct pt_regs *regs, unsigned long (report_ubsan_failureesr&UBSAN_BRK_MASK,regs);
{
 pr_err("%s generated an invalid instruction at %pS!\n",
  "Kernel text patching",
  (void *)instruction_pointer(regs));

 /* We cannot handle this */
 return DBG_HOOK_ERROR;
}

#ifdef CONFIG_KASAN_SW_TAGS

#define KASAN_ESR_RECOVER 0x20
#define KASAN_ESR_WRITE 0x10
#define KASAN_ESR_SIZE_MASK 0x0f
#define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK))

int kasan_brk_handler(struct pt_regs *regs, unsigned long esr)
{
 bool recover = esr & KASAN_ESR_RECOVER;
 bool write = esr & KASAN_ESR_WRITE;
 size_t size = KASAN_ESR_SIZE(esr);
 void *addr = (void *)regs->regs[0];
 u64 pc = regs->pc;

 kasan_report(addr, size, write, pc);

 /*
 * The instrumentation allows to control whether we can proceed after
 * a crash was detected. This is done by passing the -recover flag to
 * the compiler. Disabling recovery allows to generate more compact
 * code.
 *
 * Unfortunately disabling recovery doesn't work for the kernel right
 * now. KASAN reporting is disabled in some contexts (for example when
 * the allocator accesses slab object metadata; this is controlled by
 * current->kasan_depth). All these accesses are detected by the tool,
 * even though the reports for them are not printed.
 *
 * This is something that might be fixed at some point in the future.
 */
 if (!recover)
  die("Oops - KASAN", regs, esr);

 /* If thread survives, skip over the brk instruction and continue: */
 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
 return DBG_HOOK_HANDLED;
}
#endif

#ifdef CONFIG_UBSAN_TRAP
int ubsan_brk_handler(struct pt_regs *regs, unsigned long esr)
{
 die(report_ubsan_failure(esr & UBSAN_BRK_MASK), regs, esr);
 return DBG_HOOK_HANDLED;
}
#endif