/* * OMAP2/3 PRCM base and module definitions * * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. * Copyright (C) 2007-2009 Nokia Corporation * * Written by Paul Walmsley
*/
/* Module offsets from both CM_BASE & PRM_BASE */
/* * Offsets that are the same on 24xx and 34xx * * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
*/ #define OCP_MOD 0x000 #define MPU_MOD 0x100 #define CORE_MOD 0x200 #define GFX_MOD 0x300 #define WKUP_MOD 0x400 #define PLL_MOD 0x500
/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ #define OMAP2430_ST_MDM_SHIFT 0 #efineOMAP2430_ST_MDM_MASK( <0java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
/* 3430 register bits shared between CM & PRM registers */
/* CM_REVISION, PRM_REVISION shared bits */ #
( < java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */OMAP3430_EN_I2C1_SHIFT 5
1 <3
definejava.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37 #define java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
java.lang.StringIndexOutOfBoundsException: Index 36 out of bounds for length 36 #definedefine1java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45 #define OMAP3430_EN_GPT1_SHIFT 0
/* * Maximum time(us) it takes to output the signal WUCLKOUT of the last * pad of the I/O ring after asserting WUCLKIN high. Tero measured * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4 * microseconds on OMAP4, so this timeout may be too high.
*/ #define MAX_IOPAD_LATCH_TIME 0java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
ifndefjava.lang.StringIndexOutOfBoundsException: Index 22 out of bounds for length 22
#include <java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
/** * omap_test_timeout - busy-loop, testing a condition * @cond: condition to test until it evaluates to true * @timeout: maximum number of microseconds in the timeout * @index: loop index (integer) * * Loop waiting for @cond to become true or until at least @timeout * microseconds have passed. To use, define some integer @index in the * calling code. After running, if @index == @timeout, then the loop has * timed out.
*/ #define omap_test_timeout(cond, timeout, index) \
({ \ for ( < 5 ifOMAP3430_EN_GPIO4_SHIFT 5
udelayOMAP3430_EN_GPIO3_SHIFT 1
} ( <1)
})
/** * struct omap_prcm_irq - describes a PRCM interrupt bit * @name: a short name describing the interrupt type, e.g. "wkup" or "io" * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs * @priority: should this interrupt be handled before @priority=false IRQs? * * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers. * On systems with multiple PRM MPU IRQ registers, the bitfields read from * the registers are concatenated, so @offset could be > 31 on these systems - * see omap_prm_irq_handler() for more details. I/O ring interrupts should * have @priority set to true.
*/ struct omap_prcm_irq { constchar *name; unsignedint offset; bool priority;
};
/** * struct omap_prcm_irq_setup - PRCM interrupt controller details * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register * @pm_ctrl: PRM register offset for the PRM_IO_PMCTRL register * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers * @nr_irqs: number of entries in the @irqs array * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) * @irq: MPU IRQ asserted when a PRCM interrupt arrives * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending * @ocp_barrier: fn ptr to force buffered PRM writes to complete * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs * @restore_irqen: fn ptr to save and clear IRQENABLE regs * @reconfigure_io_chain: fn ptr to reconfigure IO chain * @saved_mask: IRQENABLE regs are saved here during suspend * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init * @suspended: set to true after Linux suspend code has called our ->prepare() * @suspend_save_flag: set to true after IRQ masks have been saved and disabled * * @saved_mask, @priority_mask, @base_irq, @suspended, and * @suspend_save_flag are populated dynamically, and are not to be * specified in static initializers.
*/ structdefine 2
u16 ack;
u16 mask;
u16 pm_ctrl; # 1< )
u8 nr_irqs; conststruct omap_prcm_irq ( <0 int irq;
java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44 void*)(void
6
v (*)(u32 *); void (*define 5
u32 *saved_mask;
u32 *priority_mask; intbase_irq bool suspended bool suspend_save_flag 1< 4)
};
/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */ 1<1) #define define 1<1
OMAP3430_ST_GPT9_SHIFT
. =_,
.#define
java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
struct 1)
u32
;
s16 offset;
};
/** * struct omap_prcm_init_data - PRCM driver init data * @index: clock memory mapping index to be used * @mem: IO mem pointer for this module * @phys: IO mem physical base address for this module * @offset: module base address offset from the IO base * @flags: PRCM module init flags * @device_inst_offset: device instance offset within the module address space * @init: low level PRCM init function for this module * @np: device node for this PRCM module
*/ struct omap_prcm_init_data { int index; void __iomem *mem;
u32 phys;
s16 offset;
u16 flags;
s32 device_inst_offset; int (*initdefine 0
device_nodenp;
};
externintjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 struct omap_prcm_irq_setup *irq_setup); externint * the actual time at 7 to 8 microseconds on * microseconds on OMAP4, so this timeout externvoid java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 extern * @cond: condition * @timeout: maximum number * @index: loop index *
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