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Quelle mt8188.dtsi
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2023 MediaTek Inc.
*
*/
/dts-v1/;
#include <dt-bindings/clock/mediatek,mt8188-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
#include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
#include <dt-bindings/power/mediatek,mt8188-power.h>
#include <dt-bindings/reset/mt8188-resets.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
/ {
compatible = "mediatek,mt8188";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
dp-intf0 = &dp_intf0;
dp-intf1 = &dp_intf1;
dsc0 = &dsc0;
ethdr0 = ðdr0;
gce0 = &gce0;
gce1 = &gce1;
merge0 = &merge0;
merge1 = &merge1;
merge2 = &merge2;
merge3 = &merge3;
merge4 = &merge4;
merge5 = &merge5;
mutex0 = &mutex0;
mutex1 = &mutex1;
padding0 = &padding0;
padding1 = &padding1;
padding2 = &padding2;
padding3 = &padding3;
padding4 = &padding4;
padding5 = &padding5;
padding6 = &padding6;
padding7 = &padding7;
vdo1-rdma0 = &vdo1_rdma0;
vdo1-rdma1 = &vdo1_rdma1;
vdo1-rdma2 = &vdo1_rdma2;
vdo1-rdma3 = &vdo1_rdma3;
vdo1-rdma4 = &vdo1_rdma4;
vdo1-rdma5 = &vdo1_rdma5;
vdo1-rdma6 = &vdo1_rdma6;
vdo1-rdma7 = &vdo1_rdma7;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x000>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <282>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <282>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <282>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <282>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x400>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <282>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x500>;
enable-method = "psci";
clock-frequency = <2000000000>;
capacity-dmips-mhz = <282>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
performance-domains = <&performance 0>;
#cooling-cells = <2>;
};
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x600>;
enable-method = "psci";
clock-frequency = <2600000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
#cooling-cells = <2>;
};
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x700>;
enable-method = "psci";
clock-frequency = <2600000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
performance-domains = <&performance 1>;
#cooling-cells = <2>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
core6 {
cpu = <&cpu6>;
};
core7 {
cpu = <&cpu7>;
};
};
};
idle-states {
entry-method = "psci";
cpu_off_l: cpu-off-l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010000>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <95>;
min-residency-us = <580>;
};
cpu_off_b: cpu-off-b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010000>;
local-timer-stop;
entry-latency-us = <45>;
exit-latency-us = <140>;
min-residency-us = <740>;
};
cluster_off_l: cluster-off-l {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010010>;
local-timer-stop;
entry-latency-us = <55>;
exit-latency-us = <155>;
min-residency-us = <840>;
};
cluster_off_b: cluster-off-b {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010010>;
local-timer-stop;
entry-latency-us = <50>;
exit-latency-us = <200>;
min-residency-us = <1000>;
};
};
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_0>;
cache-unified;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_0>;
cache-unified;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
cache-unified;
};
};
clk13m: oscillator-13m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <13000000>;
clock-output-names = "clk13m";
};
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
clk32k: oscillator-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "clk32k";
};
gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-shared;
opp-390000000 {
opp-hz = /bits/ 64 <390000000>;
opp-microvolt = <575000>;
opp-supported-hw = <0xff>;
};
opp-431000000 {
opp-hz = /bits/ 64 <431000000>;
opp-microvolt = <587500>;
opp-supported-hw = <0xff>;
};
opp-473000000 {
opp-hz = /bits/ 64 <473000000>;
opp-microvolt = <600000>;
opp-supported-hw = <0xff>;
};
opp-515000000 {
opp-hz = /bits/ 64 <515000000>;
opp-microvolt = <612500>;
opp-supported-hw = <0xff>;
};
opp-556000000 {
opp-hz = /bits/ 64 <556000000>;
opp-microvolt = <625000>;
opp-supported-hw = <0xff>;
};
opp-598000000 {
opp-hz = /bits/ 64 <598000000>;
opp-microvolt = <637500>;
opp-supported-hw = <0xff>;
};
opp-640000000 {
opp-hz = /bits/ 64 <640000000>;
opp-microvolt = <650000>;
opp-supported-hw = <0xff>;
};
opp-670000000 {
opp-hz = /bits/ 64 <670000000>;
opp-microvolt = <662500>;
opp-supported-hw = <0xff>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <675000>;
opp-supported-hw = <0xff>;
};
opp-730000000 {
opp-hz = /bits/ 64 <730000000>;
opp-microvolt = <687500>;
opp-supported-hw = <0xff>;
};
opp-760000000 {
opp-hz = /bits/ 64 <760000000>;
opp-microvolt = <700000>;
opp-supported-hw = <0xff>;
};
opp-790000000 {
opp-hz = /bits/ 64 <790000000>;
opp-microvolt = <712500>;
opp-supported-hw = <0xff>;
};
opp-835000000 {
opp-hz = /bits/ 64 <835000000>;
opp-microvolt = <731250>;
opp-supported-hw = <0xff>;
};
opp-880000000 {
opp-hz = /bits/ 64 <880000000>;
opp-microvolt = <750000>;
opp-supported-hw = <0xff>;
};
opp-915000000 {
opp-hz = /bits/ 64 <915000000>;
opp-microvolt = <775000>;
opp-supported-hw = <0x8f>;
};
opp-915000000-5 {
opp-hz = /bits/ 64 <915000000>;
opp-microvolt = <762500>;
opp-supported-hw = <0x30>;
};
opp-915000000-6 {
opp-hz = /bits/ 64 <915000000>;
opp-microvolt = <750000>;
opp-supported-hw = <0x70>;
};
opp-950000000 {
opp-hz = /bits/ 64 <950000000>;
opp-microvolt = <800000>;
opp-supported-hw = <0x8f>;
};
opp-950000000-5 {
opp-hz = /bits/ 64 <950000000>;
opp-microvolt = <775000>;
opp-supported-hw = <0x30>;
};
opp-950000000-6 {
opp-hz = /bits/ 64 <950000000>;
opp-microvolt = <750000>;
opp-supported-hw = <0x70>;
};
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
};
pmu-a78 {
compatible = "arm,cortex-a78-pmu";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
sound: sound {
mediatek,platform = <&afe>;
status = "disabled";
};
thermal_zones: thermal-zones {
cpu-little0-thermal {
polling-delay = <1000>;
polling-delay-passive = <150>;
thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU0>;
trips {
cpu_little0_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_little0_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu_little0_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
cpu_little0_cooling_map0: map0 {
trip = <&cpu_little0_alert0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu-little1-thermal {
polling-delay = <1000>;
polling-delay-passive = <150>;
thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU1>;
trips {
cpu_little1_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_little1_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu_little1_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
cpu_little1_cooling_map0: map0 {
trip = <&cpu_little1_alert0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu-little2-thermal {
polling-delay = <1000>;
polling-delay-passive = <150>;
thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU2>;
trips {
cpu_little2_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_little2_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu_little2_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
cpu_little2_cooling_map0: map0 {
trip = <&cpu_little2_alert0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu-little3-thermal {
polling-delay = <1000>;
polling-delay-passive = <150>;
thermal-sensors = <&lvts_mcu MT8188_MCU_LITTLE_CPU3>;
trips {
cpu_little3_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_little3_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu_little3_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
cpu_little3_cooling_map0: map0 {
trip = <&cpu_little3_alert0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu-big0-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU0>;
trips {
cpu_big0_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_big0_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu_big0_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_big0_alert0>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu-big1-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
thermal-sensors = <&lvts_mcu MT8188_MCU_BIG_CPU1>;
trips {
cpu_big1_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cpu_big1_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cpu_big1_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_big1_alert0>;
cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
apu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8188_AP_APU>;
trips {
apu_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
apu_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
apu_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
};
gpu-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8188_AP_GPU0>;
trips {
gpu_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
gpu_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
gpu_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu1-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8188_AP_GPU1>;
trips {
gpu1_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
gpu1_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
gpu1_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&gpu1_alert0>;
cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
adsp-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8188_AP_ADSP>;
trips {
soc_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
soc_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
};
vdo-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8188_AP_VDO>;
trips {
soc1_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc1_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
soc1_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
};
infra-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8188_AP_INFRA>;
trips {
soc2_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc2_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
soc2_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
};
cam1-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8188_AP_CAM1>;
trips {
cam1_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cam1_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cam1_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
};
cam2-thermal {
polling-delay = <1000>;
polling-delay-passive = <250>;
thermal-sensors = <&lvts_ap MT8188_AP_CAM2>;
trips {
cam2_alert0: trip-alert0 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
cam2_alert1: trip-alert1 {
temperature = <95000>;
hysteresis = <2000>;
type = "hot";
};
cam2_crit: trip-crit {
temperature = <100000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clock-frequency = <13000000>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
ranges;
performance: performance-controller@11bc10 {
compatible = "mediatek,cpufreq-hw";
reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
#performance-domain-cells = <1>;
};
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
#redistributor-regions = <1>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>,
<0 0x0c040000 0 0x200000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu6 &cpu7>;
};
};
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8188-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg_ao: syscon@10001000 {
compatible = "mediatek,mt8188-infracfg-ao", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt8188-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@10005000 {
compatible = "mediatek,mt8188-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11c00000 0 0x1000>,
<0 0x11e10000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11ea0000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg_rm", "iocfg_lt",
"iocfg_lm", "iocfg_rt", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 176>;
interrupt-controller;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
};
scpsys: syscon@10006000 {
compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8188-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domain of the SoC */
mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 {
reg = <MT8188_POWER_DOMAIN_MFG0>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 {
reg = <MT8188_POWER_DOMAIN_MFG1>;
clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
<&topckgen CLK_TOP_MFG_CORE_TMP>;
clock-names = "mfg", "alt";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_MFG2 {
reg = <MT8188_POWER_DOMAIN_MFG2>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_MFG3 {
reg = <MT8188_POWER_DOMAIN_MFG3>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_MFG4 {
reg = <MT8188_POWER_DOMAIN_MFG4>;
#power-domain-cells = <0>;
};
};
};
power-domain@MT8188_POWER_DOMAIN_VPPSYS0 {
reg = <MT8188_POWER_DOMAIN_VPPSYS0>;
clocks = <&topckgen CLK_TOP_VPP>,
<&topckgen CLK_TOP_CAM>,
<&topckgen CLK_TOP_CCU>,
<&topckgen CLK_TOP_IMG>,
<&topckgen CLK_TOP_VENC>,
<&topckgen CLK_TOP_VDEC>,
<&topckgen CLK_TOP_WPE_VPP>,
<&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>,
<&topckgen CLK_TOP_CFGREG_F26M_VPP0>,
<&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>,
<&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>,
<&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>,
<&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>,
<&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>,
<&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>,
<&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>,
<&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>,
<&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>,
<&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>,
<&vppsys0 CLK_VPP0_SMI_IOMMU>,
<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
<&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
<&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
<&vppsys0 CLK_VPP0_SMI_RSI>,
<&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
<&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
<&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>,
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
clock-names = "top", "cam", "ccu", "img", "venc",
"vdec", "wpe", "cfgck", "cfgxo",
"ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1",
"ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa",
"ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6",
"ss-sram-rdr", "ss-iommu", "ss-imgcam",
"ss-emi", "ss-subcmn-rdr", "ss-rsi",
"ss-cmn-l4", "ss-vdec1", "ss-wpe",
"ss-cvdo-ve1";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_VDOSYS0 {
reg = <MT8188_POWER_DOMAIN_VDOSYS0>;
clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>,
<&topckgen CLK_TOP_CFGREG_F26M_VDO0>,
<&vdosys0 CLK_VDO0_SMI_GALS>,
<&vdosys0 CLK_VDO0_SMI_COMMON>,
<&vdosys0 CLK_VDO0_SMI_EMI>,
<&vdosys0 CLK_VDO0_SMI_IOMMU>,
<&vdosys0 CLK_VDO0_SMI_LARB>,
<&vdosys0 CLK_VDO0_SMI_RSI>,
<&vdosys0 CLK_VDO0_APB_BUS>;
clock-names = "cfgck", "cfgxo", "ss-gals",
"ss-cmn", "ss-emi", "ss-iommu",
"ss-larb", "ss-rsi", "ss-bus";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_VPPSYS1 {
reg = <MT8188_POWER_DOMAIN_VPPSYS1>;
clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>,
<&topckgen CLK_TOP_CFGREG_F26M_VPP1>,
<&vppsys1 CLK_VPP1_GALS5>,
<&vppsys1 CLK_VPP1_GALS6>,
<&vppsys1 CLK_VPP1_LARB5>,
<&vppsys1 CLK_VPP1_LARB6>;
clock-names = "cfgck", "cfgxo",
"ss-vpp1-g5", "ss-vpp1-g6",
"ss-vpp1-l5", "ss-vpp1-l6";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_VDEC0 {
reg = <MT8188_POWER_DOMAIN_VDEC0>;
clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>;
clock-names = "ss-vdec1-soc-l1";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_VDEC1 {
reg = <MT8188_POWER_DOMAIN_VDEC1>;
clocks = <&vdecsys CLK_VDEC2_LARB1>;
clock-names = "ss-vdec2-l1";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE {
reg = <MT8188_POWER_DOMAIN_CAM_VCORE>;
clocks = <&topckgen CLK_TOP_CAM>,
<&topckgen CLK_TOP_CCU>,
<&topckgen CLK_TOP_CCU_AHB>,
<&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>;
clock-names = "cam", "ccu", "bus", "cfgck";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_CAM_MAIN {
reg = <MT8188_POWER_DOMAIN_CAM_MAIN>;
clocks = <&camsys CLK_CAM_MAIN_LARB13>,
<&camsys CLK_CAM_MAIN_LARB14>,
<&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
<&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
<&camsys CLK_CAM_MAIN_CAM2SYS_GALS>;
clock-names= "ss-cam-l13", "ss-cam-l14",
"ss-cam-mm0", "ss-cam-mm1",
"ss-camsys";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_CAM_SUBB {
reg = <MT8188_POWER_DOMAIN_CAM_SUBB>;
clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>,
<&camsys_rawb CLK_CAM_RAWB_LARBX>,
<&camsys_yuvb CLK_CAM_YUVB_LARBX>;
clock-names = "ss-camb-sub",
"ss-camb-raw",
"ss-camb-yuv";
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_CAM_SUBA {
reg =<MT8188_POWER_DOMAIN_CAM_SUBA>;
clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>,
<&camsys_rawa CLK_CAM_RAWA_LARBX>,
<&camsys_yuva CLK_CAM_YUVA_LARBX>;
clock-names = "ss-cama-sub",
"ss-cama-raw",
"ss-cama-yuv";
#power-domain-cells = <0>;
};
};
};
power-domain@MT8188_POWER_DOMAIN_VDOSYS1 {
reg = <MT8188_POWER_DOMAIN_VDOSYS1>;
clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>,
<&topckgen CLK_TOP_CFGREG_F26M_VDO1>,
<&vdosys1 CLK_VDO1_SMI_LARB2>,
<&vdosys1 CLK_VDO1_SMI_LARB3>,
<&vdosys1 CLK_VDO1_GALS>;
clock-names = "cfgck", "cfgxo", "ss-larb2",
"ss-larb3", "ss-gals";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_HDMI_TX {
reg = <MT8188_POWER_DOMAIN_HDMI_TX>;
clocks = <&topckgen CLK_TOP_HDMI_APB>,
<&topckgen CLK_TOP_HDCP_24M>;
clock-names = "bus", "hdcp";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_DP_TX {
reg = <MT8188_POWER_DOMAIN_DP_TX>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_EDP_TX {
reg = <MT8188_POWER_DOMAIN_EDP_TX>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
power-domain@MT8188_POWER_DOMAIN_VENC {
reg = <MT8188_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC1_LARB>,
<&vencsys CLK_VENC1_VENC>,
<&vencsys CLK_VENC1_GALS>,
<&vencsys CLK_VENC1_GALS_SRAM>;
clock-names = "ss-ve1-larb", "ss-ve1-core",
"ss-ve1-gals", "ss-ve1-sram";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_WPE {
reg = <MT8188_POWER_DOMAIN_WPE>;
clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>,
<&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>;
clock-names = "ss-wpe-l7", "ss-wpe-l7pce";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
};
power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 {
reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
mediatek,infracfg = <&infracfg_ao>;
clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
clock-names = "ss-pextp-fmem";
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP {
reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>;
clocks = <&topckgen CLK_TOP_SENINF>,
<&topckgen CLK_TOP_SENINF1>;
clock-names = "seninf0", "seninf1";
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP {
reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_ADSP_AO {
reg = <MT8188_POWER_DOMAIN_ADSP_AO>;
clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
<&topckgen CLK_TOP_ADSP>;
clock-names = "bus", "main";
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA {
reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>;
mediatek,infracfg = <&infracfg_ao>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC {
reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>;
clocks = <&topckgen CLK_TOP_ASM_H>;
clock-names = "asm";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_AUDIO {
reg = <MT8188_POWER_DOMAIN_AUDIO>;
clocks = <&topckgen CLK_TOP_A1SYS_HP>,
<&topckgen CLK_TOP_AUD_INTBUS>,
<&adsp_audio26m CLK_AUDIODSP_AUDIO26M>;
clock-names = "a1sys", "intbus", "adspck";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
power-domain@MT8188_POWER_DOMAIN_ADSP {
reg = <MT8188_POWER_DOMAIN_ADSP>;
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
};
power-domain@MT8188_POWER_DOMAIN_ETHER {
reg = <MT8188_POWER_DOMAIN_ETHER>;
clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
clock-names = "ethermac";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
};
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8188-wdt";
reg = <0 0x10007000 0 0x100>;
mediatek,disable-extrst;
#reset-cells = <1>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8188-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
systimer: timer@10017000 {
compatible = "mediatek,mt8188-timer", "mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk13m>;
};
pwrap: pwrap@10024000 {
compatible = "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap", "syscon";
reg = <0 0x10024000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
clock-names = "spi", "wrap";
};
spmi: spmi@10027000 {
compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi";
reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>;
reg-names = "pmif", "spmimst";
assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>;
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
<&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
<&topckgen CLK_TOP_SPMI_M_MST>;
clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
};
infra_iommu: iommu@10315000 {
compatible = "mediatek,mt8188-iommu-infra";
reg = <0 0x10315000 0 0x1000>;
interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>;
#iommu-cells = <1>;
};
gce0: mailbox@10320000 {
compatible = "mediatek,mt8188-gce";
reg = <0 0x10320000 0 0x4000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <2>;
clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
};
gce1: mailbox@10330000 {
compatible = "mediatek,mt8188-gce";
reg = <0 0x10330000 0 0x4000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <2>;
clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
};
scp_cluster: scp@10720000 {
compatible = "mediatek,mt8188-scp-dual";
reg = <0 0x10720000 0 0xe0000>;
reg-names = "cfg";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x10500000 0x100000>;
status = "disabled";
scp_c0: scp@0 {
compatible = "mediatek,scp-core";
reg = <0x0 0xd0000>;
reg-names = "sram";
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
scp_c1: scp@d0000 {
compatible = "mediatek,scp-core";
reg = <0xd0000 0x2f000>;
reg-names = "sram";
interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
status = "disabled";
};
};
afe: audio-controller@10b10000 {
compatible = "mediatek,mt8188-afe";
reg = <0 0x10b10000 0 0x10000>;
assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>;
assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>;
clocks = <&clk26m>,
<&apmixedsys CLK_APMIXED_APLL1>,
<&apmixedsys CLK_APMIXED_APLL2>,
<&topckgen CLK_TOP_APLL12_CK_DIV0>,
<&topckgen CLK_TOP_APLL12_CK_DIV1>,
<&topckgen CLK_TOP_APLL12_CK_DIV2>,
<&topckgen CLK_TOP_APLL12_CK_DIV3>,
<&topckgen CLK_TOP_APLL12_CK_DIV9>,
<&topckgen CLK_TOP_A1SYS_HP>,
<&topckgen CLK_TOP_AUD_INTBUS>,
<&topckgen CLK_TOP_AUDIO_H>,
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
<&topckgen CLK_TOP_DPTX>,
<&topckgen CLK_TOP_I2SO1>,
<&topckgen CLK_TOP_I2SO2>,
<&topckgen CLK_TOP_I2SI1>,
<&topckgen CLK_TOP_I2SI2>,
<&adsp_audio26m CLK_AUDIODSP_AUDIO26M>,
<&topckgen CLK_TOP_APLL1_D4>,
<&topckgen CLK_TOP_APLL2_D4>,
<&topckgen CLK_TOP_APLL12_CK_DIV4>,
<&topckgen CLK_TOP_A2SYS>,
<&topckgen CLK_TOP_AUD_IEC>;
clock-names = "clk26m",
"apll1",
"apll2",
"apll12_div0",
"apll12_div1",
"apll12_div2",
"apll12_div3",
"apll12_div9",
"top_a1sys_hp",
"top_aud_intbus",
"top_audio_h",
"top_audio_local_bus",
"top_dptx",
"top_i2so1",
"top_i2so2",
"top_i2si1",
"top_i2si2",
"adsp_audio_26m",
"apll1_d4",
"apll2_d4",
"apll12_div4",
"top_a2sys",
"top_aud_iec";
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>;
resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>;
reset-names = "audiosys";
mediatek,infracfg = <&infracfg_ao>;
mediatek,topckgen = <&topckgen>;
status = "disabled";
};
adsp: adsp@10b80000 {
compatible = "mediatek,mt8188-dsp";
reg = <0 0x10b80000 0 0x2000>,
<0 0x10d00000 0 0x80000>,
<0 0x10b8b000 0 0x100>,
<0 0x10b8f000 0 0x1000>;
reg-names = "cfg", "sram", "sec", "bus";
assigned-clocks = <&topckgen CLK_TOP_ADSP>;
clocks = <&topckgen CLK_TOP_ADSP>,
<&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
clock-names = "audiodsp", "adsp_bus";
mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
mbox-names = "rx", "tx";
power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>;
status = "disabled";
};
adsp_mailbox0: mailbox@10b86100 {
compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
reg = <0 0x10b86100 0 0x1000>;
interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <0>;
};
adsp_mailbox1: mailbox@10b87100 {
compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox";
reg = <0 0x10b87100 0 0x1000>;
interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>;
#mbox-cells = <0>;
};
adsp_audio26m: clock-controller@10b91100 {
compatible = "mediatek,mt8188-adsp-audio26m";
reg = <0 0x10b91100 0 0x100>;
#clock-cells = <1>;
};
uart0: serial@11001100 {
compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
reg = <0 0x11001100 0 0x100>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11001200 {
compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
reg = <0 0x11001200 0 0x100>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11001300 {
compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
reg = <0 0x11001300 0 0x100>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
clock-names = "baud", "bus";
status = "disabled";
};
uart3: serial@11001400 {
compatible = "mediatek,mt8188-uart", "mediatek,mt6577-uart";
reg = <0 0x11001400 0 0x100>;
interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
clock-names = "baud", "bus";
status = "disabled";
};
auxadc: adc@11002000 {
compatible = "mediatek,mt8188-auxadc", "mediatek,mt8173-auxadc";
reg = <0 0x11002000 0 0x1000>;
clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
clock-names = "main";
#io-channel-cells = <1>;
status = "disabled";
};
pericfg_ao: syscon@11003000 {
compatible = "mediatek,mt8188-pericfg-ao", "syscon";
reg = <0 0x11003000 0 0x1000>;
#clock-cells = <1>;
};
spi0: spi@1100a000 {
compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
lvts_ap: thermal-sensor@1100b000 {
compatible = "mediatek,mt8188-lvts-ap";
reg = <0 0x1100b000 0 0xc00>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>;
nvmem-cells = <&lvts_efuse_data1>;
nvmem-cell-names = "lvts-calib-data-1";
#thermal-sensor-cells = <1>;
};
disp_pwm0: pwm@1100e000 {
compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
clocks = <&topckgen CLK_TOP_DISP_PWM0>,
<&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
clock-names = "main", "mm";
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
#pwm-cells = <2>;
status = "disabled";
};
disp_pwm1: pwm@1100f000 {
compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm";
reg = <0 0x1100f000 0 0x1000>;
clocks = <&topckgen CLK_TOP_DISP_PWM1>,
<&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
clock-names = "main", "mm";
interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
#pwm-cells = <2>;
status = "disabled";
};
spi1: spi@11010000 {
compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11010000 0 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi2: spi@11012000 {
compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11012000 0 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi3: spi@11013000 {
compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11013000 0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi4: spi@11018000 {
compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11018000 0 0x1000>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI4>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
spi5: spi@11019000 {
compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm";
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0x11019000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
<&topckgen CLK_TOP_SPI>,
<&infracfg_ao CLK_INFRA_AO_SPI5>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
ssusb1: usb@11201000 {
compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
ranges = <0 0 0 0x11200000 0 0x3f00>;
#address-cells = <2>;
#size-cells = <2>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&topckgen CLK_TOP_USB_TOP>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
<&topckgen CLK_TOP_SSUSB_TOP_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x468 2>;
status = "disabled";
xhci1: usb@0 {
compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
reg = <0 0 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
clock-names = "sys_ck";
status = "disabled";
};
};
eth: ethernet@11021000 {
compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
"snps,dwmac-5.10a";
reg = <0 0x11021000 0 0x4000>;
interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "macirq";
clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
<&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
<&topckgen CLK_TOP_SNPS_ETH_250M>,
<&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
<&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
<&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
clock-names = "axi", "apb", "mac_main", "ptp_ref",
"rmii_internal", "mac_cg";
assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
<&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
<&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
<&topckgen CLK_TOP_ETHPLL_D8>,
<&topckgen CLK_TOP_ETHPLL_D10>;
power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>;
mediatek,pericfg = <&infracfg_ao>;
snps,axi-config = <&stmmac_axi_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,txpbl = <16>;
snps,rxpbl = <16>;
snps,clk-csr = <0>;
status = "disabled";
eth_mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <0x7>;
snps,wr_osr_lmt = <0x7>;
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <4>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
};
queue2 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
};
queue3 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0x0>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
snps,tx-sched-wrr;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x0>;
snps,weight = <0x10>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,weight = <0x11>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,weight = <0x12>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x3>;
snps,weight = <0x13>;
};
};
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x10000>,
<0 0x11f50000 0 0x1000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC50_0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
<&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>;
clock-names = "source", "hclk", "source_cg", "crypto_clk";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11eb0000 0 0x1000>;
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
clock-names = "source", "hclk", "source_cg";
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
status = "disabled";
};
mmc2: mmc@11250000 {
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11250000 0 0x1000>,
<0 0x11e60000 0 0x1000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_2>,
<&infracfg_ao CLK_INFRA_AO_MSDC2>,
<&infracfg_ao CLK_INFRA_AO_MSDC30_2>;
clock-names = "source", "hclk", "source_cg";
assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
status = "disabled";
};
lvts_mcu: thermal-sensor@11278000 {
compatible = "mediatek,mt8188-lvts-mcu";
reg = <0 0x11278000 0 0x1000>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>;
nvmem-cells = <&lvts_efuse_data1>;
nvmem-cell-names = "lvts-calib-data-1";
#thermal-sensor-cells = <1>;
};
i2c0: i2c@11280000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11280000 0 0x1000>,
<0 0x10220080 0 0x80>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0>,
<&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11281000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11281000 0 0x1000>,
<0 0x10220180 0 0x80>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2>,
<&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@11282000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11282000 0 0x1000>,
<0 0x10220280 0 0x80>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_c CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3>,
<&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
imp_iic_wrap_c: clock-controller@11283000 {
compatible = "mediatek,mt8188-imp-iic-wrap-c";
reg = <0 0x11283000 0 0x1000>;
#clock-cells = <1>;
};
ssusb2: usb@112a1000 {
compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
reg-names = "mac", "ippc";
ranges = <0 0 0 0x112a0000 0 0x3f00>;
#address-cells = <2>;
#size-cells = <2>;
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
<&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
phys = <&u2port2 PHY_TYPE_USB2>;
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x470 2>;
status = "disabled";
xhci2: usb@0 {
compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
reg = <0 0 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
clock-names = "sys_ck";
status = "disabled";
};
};
ssusb0: usb@112b1000 {
compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
reg-names = "mac", "ippc";
ranges = <0 0 0 0x112b0000 0 0x3f00>;
#address-cells = <2>;
#size-cells = <2>;
interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
<&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
phys = <&u2port0 PHY_TYPE_USB2>;
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x460 2>;
status = "disabled";
xhci0: usb@0 {
compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
reg = <0 0 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
clock-names = "sys_ck";
status = "disabled";
};
};
pcie: pcie@112f0000 {
compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";
reg = <0 0x112f0000 0 0x2000>;
reg-names = "pcie-mac";
ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>;
bus-range = <0 0xff>;
device_type = "pci";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
<&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
<&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
<&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",
"peri_26m", "peri_mem";
#interrupt-cells = <1>;
interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-map = <0 0 0 1 &pcie_intc 0>,
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
interrupt-map-mask = <0 0 0 7>;
iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>;
iommu-map-mask = <0>;
phys = <&pcieport PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>;
reset-names = "mac";
status = "disabled";
pcie_intc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
nor_flash: spi@1132c000 {
compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
reg = <0 0x1132c000 0 0x1000>;
clocks = <&topckgen CLK_TOP_SPINOR>,
<&pericfg_ao CLK_PERI_AO_FLASHIFLASHCK>,
<&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
clock-names = "spi", "sf", "axi";
assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pciephy: t-phy@11c20700 {
compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
ranges = <0 0 0x11c20700 0x700>;
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
status = "disabled";
pcieport: pcie-phy@0 {
reg = <0 0x700>;
clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>;
clock-names = "ref";
#phy-cells = <1>;
};
};
mipi_tx_config0: dsi-phy@11c80000 {
compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
reg = <0 0x11c80000 0 0x1000>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
mipi_tx_config1: dsi-phy@11c90000 {
compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx";
reg = <0 0x11c90000 0 0x1000>;
clocks = <&clk26m>;
clock-output-names = "mipi_tx0_pll";
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
i2c1: i2c@11e00000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11e00000 0 0x1000>,
<0 0x10220100 0 0x80>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1>,
<&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@11e01000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11e01000 0 0x1000>,
<0 0x10220380 0 0x80>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4>,
<&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
imp_iic_wrap_w: clock-controller@11e02000 {
compatible = "mediatek,mt8188-imp-iic-wrap-w";
reg = <0 0x11e02000 0 0x1000>;
#clock-cells = <1>;
};
u3phy0: t-phy@11e30000 {
compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x11e30000 0x1000>;
status = "disabled";
u2port0: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>,
<&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
u3phy1: t-phy@11e40000 {
compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x11e40000 0x1000>;
status = "disabled";
u2port1: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
<&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
u3port1: usb-phy@700 {
reg = <0x700 0x700>;
clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>,
<&clk26m>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
u3phy2: t-phy@11e80000 {
compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x11e80000 0x1000>;
status = "disabled";
u2port2: usb-phy@0 {
reg = <0x0 0x700>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>,
<&apmixedsys CLK_APMIXED_PLL_SSUSB26M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
i2c5: i2c@11ec0000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11ec0000 0 0x1000>,
<0 0x10220480 0 0x80>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5>,
<&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@11ec1000 {
compatible = "mediatek,mt8188-i2c";
reg = <0 0x11ec1000 0 0x1000>,
<0 0x10220600 0 0x80>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
clock-div = <1>;
clocks = <&imp_iic_wrap_en CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6>,
<&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
imp_iic_wrap_en: clock-controller@11ec2000 {
compatible = "mediatek,mt8188-imp-iic-wrap-en";
reg = <0 0x11ec2000 0 0x1000>;
#clock-cells = <1>;
};
efuse: efuse@11f20000 {
compatible = "mediatek,mt8188-efuse", "mediatek,mt8186-efuse";
reg = <0 0x11f20000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
dp_calib_data: dp-calib@1a0 {
reg = <0x1a0 0xc>;
};
lvts_efuse_data1: lvts1-calib@1ac {
reg = <0x1ac 0x40>;
};
gpu_speedbin: gpu-speedbin@581 {
reg = <0x581 0x1>;
bits = <0 3>;
};
socinfo-data1@7a0 {
reg = <0x7a0 0x4>;
};
socinfo-data2@7e0 {
reg = <0x7e0 0x4>;
};
};
gpu: gpu@13000000 {
compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm";
reg = <0 0x13000000 0 0x4000>;
clocks = <&mfgcfg CLK_MFGCFG_BG3D>;
interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
nvmem-cells = <&gpu_speedbin>;
nvmem-cell-names = "speed-bin";
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
<&spm MT8188_POWER_DOMAIN_MFG3>,
<&spm MT8188_POWER_DOMAIN_MFG4>;
power-domain-names = "core0", "core1", "core2";
#cooling-cells = <2>;
status = "disabled";
};
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8188-mfgcfg";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
vppsys0: syscon@14000000 {
compatible = "mediatek,mt8188-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
dma-controller@14001000 {
compatible = "mediatek,mt8188-mdp3-rdma";
reg = <0 0x14001000 0 0x1000>;
#dma-cells = <1>;
clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
mboxes = <&gce0 13 CMDQ_THR_PRIO_1>,
<&gce0 14 CMDQ_THR_PRIO_1>,
<&gce0 16 CMDQ_THR_PRIO_1>,
<&gce0 21 CMDQ_THR_PRIO_1>,
<&gce0 22 CMDQ_THR_PRIO_1>;
iommus = <&vpp_iommu M4U_PORT_L4_MDP_RDMA>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
<CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>;
mediatek,scp = <&scp_c0>;
};
display@14002000 {
compatible = "mediatek,mt8188-mdp3-fg", "mediatek,mt8195-mdp3-fg";
reg = <0 0x14002000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>;
};
display@14004000 {
compatible = "mediatek,mt8188-mdp3-hdr", "mediatek,mt8195-mdp3-hdr";
reg = <0 0x14004000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
};
display@14005000 {
compatible = "mediatek,mt8188-mdp3-aal", "mediatek,mt8195-mdp3-aal";
reg = <0 0x14005000 0 0x1000>;
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>;
};
display@14006000 {
compatible = "mediatek,mt8188-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
reg = <0 0x14006000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>,
<CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>;
};
display@14007000 {
compatible = "mediatek,mt8188-mdp3-tdshp", "mediatek,mt8195-mdp3-tdshp";
reg = <0 0x14007000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
};
display@14008000 {
compatible = "mediatek,mt8188-mdp3-color", "mediatek,mt8195-mdp3-color";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>;
};
display@14009000 {
compatible = "mediatek,mt8188-mdp3-ovl", "mediatek,mt8195-mdp3-ovl";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>;
iommus = <&vpp_iommu M4U_PORT_L4_MDP_OVL>;
};
display@1400a000 {
compatible = "mediatek,mt8188-mdp3-padding", "mediatek,mt8195-mdp3-padding";
reg = <0 0x1400a000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_PADDING>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>;
};
display@1400b000 {
compatible = "mediatek,mt8188-mdp3-tcc", "mediatek,mt8195-mdp3-tcc";
reg = <0 0x1400b000 0 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
};
display@1400c000 {
compatible = "mediatek,mt8188-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
reg = <0 0x1400c000 0 0x1000>;
#dma-cells = <1>;
clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
iommus = <&vpp_iommu M4U_PORT_L4_MDP_WROT>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
<CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>;
};
mutex@1400f000 {
compatible = "mediatek,mt8188-vpp-mutex";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&vppsys0 CLK_VPP0_MUTEX>;
power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>;
--> --------------------
--> maximum size reached
--> --------------------
[ Dauer der Verarbeitung: 0.26 Sekunden
(vorverarbeitet)
]
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2026-04-07
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