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Quelle qcs615.dtsi
Sprache: unbekannt
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_100>;
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_200>;
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_300>;
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x400>;
enable-method = "psci";
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_400>;
l2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x500>;
enable-method = "psci";
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&l2_500>;
l2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0 0x600>;
enable-method = "psci";
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
next-level-cache = <&l2_600>;
#cooling-cells = <2>;
l2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a76";
reg = <0x0 0x700>;
enable-method = "psci";
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
capacity-dmips-mhz = <1740>;
dynamic-power-coefficient = <404>;
next-level-cache = <&l2_700>;
l2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
core6 {
cpu = <&cpu6>;
};
core7 {
cpu = <&cpu7>;
};
};
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
dummy_eud: dummy-sink {
compatible = "arm,coresight-dummy-sink";
in-ports {
port {
eud_in: endpoint {
remote-endpoint = <&replicator_swao_out1>;
};
};
};
};
idle-states {
entry-method = "psci";
little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <549>;
exit-latency-us = <901>;
min-residency-us = <1774>;
local-timer-stop;
};
little_cpu_sleep_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <702>;
exit-latency-us = <915>;
min-residency-us = <4001>;
local-timer-stop;
};
big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <523>;
exit-latency-us = <1244>;
min-residency-us = <2207>;
local-timer-stop;
};
big_cpu_sleep_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <526>;
exit-latency-us = <1854>;
min-residency-us = <5555>;
local-timer-stop;
};
};
domain-idle-states {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <2752>;
exit-latency-us = <3048>;
min-residency-us = <6118>;
};
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x41001344>;
entry-latency-us = <3263>;
exit-latency-us = <4562>;
min-residency-us = <8467>;
};
cluster_sleep_2: cluster-sleep-2 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x4100b344>;
entry-latency-us = <3638>;
exit-latency-us = <6562>;
min-residency-us = <9826>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
firmware {
scm {
compatible = "qcom,scm-qcs615", "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
camnoc_virt: interconnect-0 {
compatible = "qcom,qcs615-camnoc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
ipa_virt: interconnect-1 {
compatible = "qcom,qcs615-ipa-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-2 {
compatible = "qcom,qcs615-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
/* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */
mboxes = <&apss_shared 26>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 6>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qup_opp_table: opp-table-qup {
compatible = "operating-points-v2";
opp-shared;
opp-75000000 {
opp-hz = /bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-128000000 {
opp-hz = /bits/ 64 <128000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
};
cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
domain-idle-states = <&cluster_sleep_0
&cluster_sleep_1
&cluster_sleep_2>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
aop_cmd_db_mem: aop-cmd-db@85f20000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x85f20000 0x0 0x20000>;
no-map;
};
smem_region: smem@86000000 {
compatible = "qcom,smem";
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
rproc_cdsp_mem: rproc-cdsp@93b00000 {
reg = <0x0 0x93b00000 0x0 0x1e00000>;
no-map;
};
rproc_adsp_mem: rproc-adsp@95900000 {
reg = <0x0 0x95900000 0x0 0x1e00000>;
no-map;
};
};
soc: soc@0 {
compatible = "simple-bus";
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
#address-cells = <2>;
#size-cells = <2>;
gcc: clock-controller@100000 {
compatible = "qcom,qcs615-gcc";
reg = <0 0x00100000 0 0x1f0000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
qfprom: efuse@780000 {
compatible = "qcom,qcs615-qfprom", "qcom,qfprom";
reg = <0x0 0x00780000 0x0 0x7000>;
#address-cells = <1>;
#size-cells = <1>;
qusb2_hstx_trim: hstx-trim@1f8 {
reg = <0x1fb 0x1>;
bits = <1 4>;
};
};
rng@793000 {
compatible = "qcom,qcs615-trng", "qcom,trng";
reg = <0x0 0x00793000 0x0 0x1000>;
};
sdhc_1: mmc@7c4000 {
compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0 0x007c4000 0x0 0x1000>,
<0x0 0x007c5000 0x0 0x1000>,
<0x0 0x007c8000 0x0 0x8000>;
reg-names = "hc",
"cqhci",
"ice";
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq",
"pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface",
"core",
"xo",
"ice";
resets = <&gcc GCC_SDCC1_BCR>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc1_opp_table>;
iommus = <&apps_smmu 0x02c0 0x0>;
interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "sdhc-ddr",
"cpu-sdhc";
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
supports-cqe;
dma-coherent;
status = "disabled";
sdhc1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-50000000 {
opp-hz = /bits/ 64 <50000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
gpi_dma0: dma-controller@800000 {
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0x0 0x800000 0x0 0x60000>;
#dma-cells = <3>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <8>;
dma-channel-mask = <0xf>;
iommus = <&apps_smmu 0xd6 0x0>;
status = "disabled";
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
ranges;
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0xc3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
uart0: serial@880000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00880000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
pinctrl-names = "default";
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
i2c1: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x884000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c1_data_clk>;
pinctrl-names = "default";
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
i2c2: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x888000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c2_data_clk>;
pinctrl-names = "default";
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
spi2: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
pinctrl-names = "default";
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart2: serial@888000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
<&qup_uart2_tx>, <&qup_uart2_rx>;
pinctrl-names = "default";
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
i2c3: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x88c000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c3_data_clk>;
pinctrl-names = "default";
interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
};
gpi_dma1: dma-controller@a00000 {
compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
reg = <0x0 0xa00000 0x0 0x60000>;
#dma-cells = <3>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <8>;
dma-channel-mask = <0xf>;
iommus = <&apps_smmu 0x376 0x0>;
status = "disabled";
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0xac0000 0x0 0x2000>;
ranges;
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
clock-names = "m-ahb",
"s-ahb";
iommus = <&apps_smmu 0x363 0x0>;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
i2c4: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0xa80000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c4_data_clk>;
pinctrl-names = "default";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
spi4: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0x0 0xa80000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
pinctrl-names = "default";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
uart4: serial@a80000 {
compatible = "qcom,geni-uart";
reg = <0x0 0xa80000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
<&qup_uart4_tx>, <&qup_uart4_rx>;
pinctrl-names = "default";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
i2c5: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0xa84000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c5_data_clk>;
pinctrl-names = "default";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
i2c6: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0xa88000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c6_data_clk>;
pinctrl-names = "default";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
spi6: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0x0 0xa88000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
pinctrl-names = "default";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
uart6: serial@a88000 {
compatible = "qcom,geni-uart";
reg = <0x0 0xa88000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
<&qup_uart6_tx>, <&qup_uart6_rx>;
pinctrl-names = "default";
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
i2c7: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0xa8c000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_i2c7_data_clk>;
pinctrl-names = "default";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
<&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd RPMHPD_CX>;
required-opps = <&rpmhpd_opp_low_svs>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx",
"rx";
status = "disabled";
};
spi7: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0x0 0xa8c000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
pinctrl-names = "default";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx",
"rx";
status = "disabled";
};
uart7: serial@a8c000 {
compatible = "qcom,geni-uart";
reg = <0x0 0xa8c000 0x0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
<&qup_uart7_tx>, <&qup_uart7_rx>;
pinctrl-names = "default";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&qup_opp_table>;
status = "disabled";
};
};
config_noc: interconnect@1500000 {
reg = <0x0 0x01500000 0x0 0x5080>;
compatible = "qcom,qcs615-config-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1620000 {
reg = <0x0 0x01620000 0x0 0x1f300>;
compatible = "qcom,qcs615-system-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@1700000 {
reg = <0x0 0x01700000 0x0 0x3f200>;
compatible = "qcom,qcs615-aggre1-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@1740000 {
reg = <0x0 0x01740000 0x0 0x1c100>;
compatible = "qcom,qcs615-mmss-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x0 0x01d84000 0x0 0x3000>,
<0x0 0x01d90000 0x0 0x8000>;
reg-names = "std",
"ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
clock-names = "core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"ice_core_clk";
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
operating-points-v2 = <&ufs_opp_table>;
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "ufs-ddr",
"cpu-ufs";
power-domains = <&gcc UFS_PHY_GDSC>;
iommus = <&apps_smmu 0x300 0x0>;
dma-coherent;
lanes-per-direction = <1>;
phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
#reset-cells = <1>;
status = "disabled";
ufs_opp_table: opp-table {
compatible = "operating-points-v2";
opp-50000000 {
opp-hz = /bits/ 64 <50000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <37500000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <75000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-100000000 {
opp-hz = /bits/ 64 <100000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <75000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <150000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <150000000>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <0>,
/bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
reg = <0x0 0x01d87000 0x0 0xe00>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
<&gcc GCC_UFS_MEM_CLKREF_CLK>;
clock-names = "ref",
"ref_aux",
"qref";
power-domains = <&gcc UFS_PHY_GDSC>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x24000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely;
num-channels = <16>;
qcom,num-ees = <4>;
iommus = <&apps_smmu 0x0104 0x0011>;
};
crypto: crypto@1dfa000 {
compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce";
reg = <0x0 0x01dfa000 0x0 0x6000>;
dmas = <&cryptobam 4>, <&cryptobam 5>;
dma-names = "rx", "tx";
iommus = <&apps_smmu 0x0104 0x0011>;
interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "memory";
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "qcom,qcs615-tcsr", "syscon";
reg = <0x0 0x01fc0000 0x0 0x30000>;
};
tlmm: pinctrl@3100000 {
compatible = "qcom,qcs615-tlmm";
reg = <0x0 0x03100000 0x0 0x300000>,
<0x0 0x03500000 0x0 0x300000>,
<0x0 0x03d00000 0x0 0x300000>;
reg-names = "east",
"west",
"south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 124>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
qup_i2c1_data_clk: qup-i2c1-data-clk-state {
pins = "gpio4", "gpio5";
function = "qup0";
};
qup_i2c2_data_clk: qup-i2c2-data-clk-state {
pins = "gpio0", "gpio1";
function = "qup0";
};
qup_i2c3_data_clk: qup-i2c3-data-clk-state {
pins = "gpio18", "gpio19";
function = "qup0";
};
qup_i2c4_data_clk: qup-i2c4-data-clk-state {
pins = "gpio20", "gpio21";
function = "qup1";
};
qup_i2c5_data_clk: qup-i2c5-data-clk-state {
pins = "gpio14", "gpio15";
function = "qup1";
};
qup_i2c6_data_clk: qup-i2c6-data-clk-state {
pins = "gpio6", "gpio7";
function = "qup1";
};
qup_i2c7_data_clk: qup-i2c7-data-clk-state {
pins = "gpio10", "gpio11";
function = "qup1";
};
qup_spi2_data_clk: qup-spi2-data-clk-state {
pins = "gpio0", "gpio1", "gpio2";
function = "qup0";
};
qup_spi2_cs: qup-spi2-cs-state {
pins = "gpio3";
function = "qup0";
};
qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
pins = "gpio3";
function = "gpio";
};
qup_spi4_data_clk: qup-spi4-data-clk-state {
pins = "gpio20", "gpio21", "gpio22";
function = "qup1";
};
qup_spi4_cs: qup-spi4-cs-state {
pins = "gpio23";
function = "qup1";
};
qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
pins = "gpio23";
function = "gpio";
};
qup_spi6_data_clk: qup-spi6-data-clk-state {
pins = "gpio6", "gpio7", "gpio8";
function = "qup1";
};
qup_spi6_cs: qup-spi6-cs-state {
pins = "gpio9";
function = "qup1";
};
qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
pins = "gpio9";
function = "gpio";
};
qup_spi7_data_clk: qup-spi7-data-clk-state {
pins = "gpio10", "gpio11", "gpio12";
function = "qup1";
};
qup_spi7_cs: qup-spi7-cs-state {
pins = "gpio13";
function = "qup1";
};
qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
pins = "gpio13";
function = "gpio";
};
qup_uart0_tx: qup-uart0-tx-state {
pins = "gpio16";
function = "qup0";
};
qup_uart0_rx: qup-uart0-rx-state {
pins = "gpio17";
function = "qup0";
};
qup_uart2_cts: qup-uart2-cts-state {
pins = "gpio0";
function = "qup0";
};
qup_uart2_rts: qup-uart2-rts-state {
pins = "gpio1";
function = "qup0";
};
qup_uart2_tx: qup-uart2-tx-state {
pins = "gpio2";
function = "qup0";
};
qup_uart2_rx: qup-uart2-rx-state {
pins = "gpio3";
function = "qup0";
};
qup_uart4_cts: qup-uart4-cts-state {
pins = "gpio20";
function = "qup1";
};
qup_uart4_rts: qup-uart4-rts-state {
pins = "gpio21";
function = "qup1";
};
qup_uart4_tx: qup-uart4-tx-state {
pins = "gpio22";
function = "qup1";
};
qup_uart4_rx: qup-uart4-rx-state {
pins = "gpio23";
function = "qup1";
};
qup_uart6_cts: qup-uart6-cts-state {
pins = "gpio6";
function = "qup1";
};
qup_uart6_rts: qup-uart6-rts-state {
pins = "gpio7";
function = "qup1";
};
qup_uart6_tx: qup-uart6-tx-state {
pins = "gpio8";
function = "qup1";
};
qup_uart6_rx: qup-uart6-rx-state {
pins = "gpio9";
function = "qup1";
};
qup_uart7_cts: qup-uart7-cts-state {
pins = "gpio10";
function = "qup1";
};
qup_uart7_rts: qup-uart7-rts-state {
pins = "gpio11";
function = "qup1";
};
qup_uart7_tx: qup-uart7-tx-state {
pins = "gpio12";
function = "qup1";
};
qup_uart7_rx: qup-uart7-rx-state {
pins = "gpio13";
function = "qup1";
};
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_state_off: sdc1-off-state {
clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc2_state_on: sdc2-on-state {
clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
};
sdc2_state_off: sdc2-off-state {
clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
};
};
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x06002000 0x0 0x1000>,
<0x0 0x16280000 0x0 0x180000>;
reg-names = "stm-base",
"stm-stimulus-base";
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint = <&funnel_in0_in7>;
};
};
};
};
tpda@6004000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x06004000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpda_qdss_in0: endpoint {
remote-endpoint = <&tpdm_center_out>;
};
};
port@4 {
reg = <4>;
tpda_qdss_in4: endpoint {
remote-endpoint = <&funnel_monaq_out>;
};
};
port@5 {
reg = <5>;
tpda_qdss_in5: endpoint {
remote-endpoint = <&funnel_ddr_0_out>;
};
};
port@6 {
reg = <6>;
tpda_qdss_in6: endpoint {
remote-endpoint = <&funnel_turing_out>;
};
};
port@7 {
reg = <7>;
tpda_qdss_in7: endpoint {
remote-endpoint = <&tpdm_vsense_out>;
};
};
port@8 {
reg = <8>;
tpda_qdss_in8: endpoint {
remote-endpoint = <&tpdm_dcc_out>;
};
};
port@9 {
reg = <9>;
tpda_qdss_in9: endpoint {
remote-endpoint = <&tpdm_prng_out>;
};
};
port@b {
reg = <11>;
tpda_qdss_in11: endpoint {
remote-endpoint = <&tpdm_qm_out>;
};
};
port@c {
reg = <12>;
tpda_qdss_in12: endpoint {
remote-endpoint = <&tpdm_west_out>;
};
};
port@d {
reg = <13>;
tpda_qdss_in13: endpoint {
remote-endpoint = <&tpdm_pimem_out>;
};
};
};
out-ports {
port {
tpda_qdss_out: endpoint {
remote-endpoint = <&funnel_qatb_in>;
};
};
};
};
funnel@6005000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x06005000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_qatb_in: endpoint {
remote-endpoint = <&tpda_qdss_out>;
};
};
};
out-ports {
port {
funnel_qatb_out: endpoint {
remote-endpoint = <&funnel_in0_in6>;
};
};
};
};
cti@6010000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06010000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6011000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06011000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6012000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06012000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6013000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06013000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6014000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06014000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6015000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06015000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6016000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06016000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6017000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06017000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6018000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06018000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6019000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06019000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@601a000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0601a000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@601b000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0601b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@601c000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0601c000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@601d000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0601d000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@601e000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0601e000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@601f000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0601f000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
funnel@6041000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x06041000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
funnel_in0_in6: endpoint {
remote-endpoint = <&funnel_qatb_out>;
};
};
port@7 {
reg = <7>;
funnel_in0_in7: endpoint {
remote-endpoint = <&stm_out>;
};
};
};
out-ports {
port {
funnel_in0_out: endpoint {
remote-endpoint = <&funnel_merg_in0>;
};
};
};
};
funnel@6042000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x06042000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@3 {
reg = <3>;
funnel_in1_in3: endpoint {
remote-endpoint = <&replicator_swao_out0>;
};
};
port@4 {
reg = <4>;
funnel_in1_in4: endpoint {
remote-endpoint = <&tpdm_wcss_out>;
};
};
port@7 {
reg = <7>;
funnel_in1_in7: endpoint {
remote-endpoint = <&funnel_apss_merg_out>;
};
};
};
out-ports {
port {
funnel_in1_out: endpoint {
remote-endpoint = <&funnel_merg_in1>;
};
};
};
};
funnel@6045000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x06045000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_merg_in0: endpoint {
remote-endpoint = <&funnel_in0_out>;
};
};
port@1 {
reg = <1>;
funnel_merg_in1: endpoint {
remote-endpoint = <&funnel_in1_out>;
};
};
};
out-ports {
port {
funnel_merg_out: endpoint {
remote-endpoint = <&tmc_etf_in>;
};
};
};
};
replicator@6046000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x06046000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
replicator0_in: endpoint {
remote-endpoint = <&tmc_etf_out>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
replicator0_out1: endpoint {
remote-endpoint = <&replicator1_in>;
};
};
};
};
tmc@6047000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x06047000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
tmc_etf_in: endpoint {
remote-endpoint = <&funnel_merg_out>;
};
};
};
out-ports {
port {
tmc_etf_out: endpoint {
remote-endpoint = <&replicator0_in>;
};
};
};
};
replicator@604a000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x0604a000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
status = "disabled";
in-ports {
port {
replicator1_in: endpoint {
remote-endpoint = <&replicator0_out1>;
};
};
};
out-ports {
port {
replicator1_out: endpoint {
remote-endpoint = <&funnel_swao_in6>;
};
};
};
};
cti@683b000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x0683b000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
tpdm@6840000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06840000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
status = "disabled";
out-ports {
port {
tpdm_vsense_out: endpoint {
remote-endpoint = <&tpda_qdss_in7>;
};
};
};
};
tpdm@684c000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x0684c000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
out-ports {
port {
tpdm_prng_out: endpoint {
remote-endpoint = <&tpda_qdss_in9>;
};
};
};
};
tpdm@6850000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06850000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_pimem_out: endpoint {
remote-endpoint = <&tpda_qdss_in13>;
};
};
};
};
tpdm@6860000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06860000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_turing_out: endpoint {
remote-endpoint = <&funnel_turing_in>;
};
};
};
};
funnel@6861000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x06861000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_turing_in: endpoint {
remote-endpoint = <&tpdm_turing_out>;
};
};
};
out-ports {
port {
funnel_turing_out: endpoint {
remote-endpoint = <&tpda_qdss_in6>;
};
};
};
};
cti@6867000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06867000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
tpdm@6870000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06870000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
status = "disabled";
out-ports {
port {
tpdm_dcc_out: endpoint {
remote-endpoint = <&tpda_qdss_in8>;
};
};
};
};
tpdm@699c000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x0699c000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
status = "disabled";
out-ports {
port {
tpdm_wcss_out: endpoint {
remote-endpoint = <&funnel_in1_in4>;
};
};
};
};
tpdm@69c0000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x069c0000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_monaq_out: endpoint {
remote-endpoint = <&funnel_monaq_in>;
};
};
};
};
funnel@69c3000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x069c3000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_monaq_in: endpoint {
remote-endpoint = <&tpdm_monaq_out>;
};
};
};
out-ports {
port {
funnel_monaq_out: endpoint {
remote-endpoint = <&tpda_qdss_in4>;
};
};
};
};
tpdm@69d0000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x069d0000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
status = "disabled";
out-ports {
port {
tpdm_qm_out: endpoint {
remote-endpoint = <&tpda_qdss_in11>;
};
};
};
};
tpdm@6a00000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06a00000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
status = "disabled";
out-ports {
port {
tpdm_ddr_out: endpoint {
remote-endpoint = <&funnel_ddr_0_in>;
};
};
};
};
cti@6a02000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06a02000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6a03000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06a03000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6a10000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06a10000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6a11000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06a11000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
funnel@6a05000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x06a05000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
funnel_ddr_0_in: endpoint {
remote-endpoint = <&tpdm_ddr_out>;
};
};
};
out-ports {
port {
funnel_ddr_0_out: endpoint {
remote-endpoint = <&tpda_qdss_in5>;
};
};
};
};
tpda@6b01000 {
compatible = "qcom,coresight-tpda", "arm,primecell";
reg = <0x0 0x06b01000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpda_swao_in0: endpoint {
remote-endpoint = <&tpdm_swao0_out>;
};
};
port@1 {
reg = <1>;
tpda_swao_in1: endpoint {
remote-endpoint = <&tpdm_swao1_out>;
};
};
};
out-ports {
port {
tpda_swao_out: endpoint {
remote-endpoint = <&funnel_swao_in7>;
};
};
};
};
tpdm@6b02000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06b02000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
status = "disabled";
out-ports {
port {
tpdm_swao0_out: endpoint {
remote-endpoint = <&tpda_swao_in0>;
};
};
};
};
tpdm@6b03000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06b03000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
status = "disabled";
out-ports {
port {
tpdm_swao1_out: endpoint {
remote-endpoint = <&tpda_swao_in1>;
};
};
};
};
cti@6b04000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06b04000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6b05000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06b05000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6b06000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06b06000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6b07000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06b07000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
funnel@6b08000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x06b08000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
funnel_swao_in6: endpoint {
remote-endpoint = <&replicator1_out>;
};
};
port@7 {
reg = <7>;
funnel_swao_in7: endpoint {
remote-endpoint = <&tpda_swao_out>;
};
};
};
out-ports {
port {
funnel_swao_out: endpoint {
remote-endpoint = <&tmc_etf_swao_in>;
};
};
};
};
tmc@6b09000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x06b09000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
tmc_etf_swao_in: endpoint {
remote-endpoint = <&funnel_swao_out>;
};
};
};
out-ports {
port {
tmc_etf_swao_out: endpoint {
remote-endpoint = <&replicator_swao_in>;
};
};
};
};
replicator@6b0a000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x0 0x06b0a000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
port {
replicator_swao_in: endpoint {
remote-endpoint = <&tmc_etf_swao_out>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_swao_out0: endpoint {
remote-endpoint = <&funnel_in1_in3>;
};
};
port@1 {
reg = <1>;
replicator_swao_out1: endpoint {
remote-endpoint = <&eud_in>;
};
};
};
};
cti@6b21000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06b21000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
tpdm@6b48000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06b48000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_west_out: endpoint {
remote-endpoint = <&tpda_qdss_in12>;
};
};
};
};
cti@6c13000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06c13000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
/* Not all required clocks can be enabled from the OS */
status = "fail";
};
cti@6c20000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06c20000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
status = "disabled";
};
tpdm@6c28000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x06c28000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
out-ports {
port {
tpdm_center_out: endpoint {
remote-endpoint = <&tpda_qdss_in0>;
};
};
};
};
cti@6c29000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06c29000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@6c2a000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x06c2a000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
cti@7020000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x07020000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
etm@7040000 {
compatible = "arm,primecell";
reg = <0x0 0x07040000 0x0 0x1000>;
cpu = <&cpu0>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint = <&funnel_apss_in0>;
};
};
};
};
cti@7120000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x07120000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
etm@7140000 {
compatible = "arm,primecell";
reg = <0x0 0x07140000 0x0 0x1000>;
cpu = <&cpu1>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint = <&funnel_apss_in1>;
};
};
};
};
cti@7220000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x07220000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
etm@7240000 {
compatible = "arm,primecell";
reg = <0x0 0x07240000 0x0 0x1000>;
cpu = <&cpu2>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm2_out: endpoint {
remote-endpoint = <&funnel_apss_in2>;
};
};
};
};
cti@7320000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x07320000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
etm@7340000 {
compatible = "arm,primecell";
reg = <0x0 0x07340000 0x0 0x1000>;
cpu = <&cpu3>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm3_out: endpoint {
remote-endpoint = <&funnel_apss_in3>;
};
};
};
};
cti@7420000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x07420000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
etm@7440000 {
compatible = "arm,primecell";
reg = <0x0 0x07440000 0x0 0x1000>;
cpu = <&cpu4>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm4_out: endpoint {
remote-endpoint = <&funnel_apss_in4>;
};
};
};
};
cti@7520000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x07520000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
etm@7540000 {
compatible = "arm,primecell";
reg = <0x0 0x07540000 0x0 0x1000>;
cpu = <&cpu5>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm5_out: endpoint {
remote-endpoint = <&funnel_apss_in5>;
};
};
};
};
cti@7620000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x07620000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
etm@7640000 {
compatible = "arm,primecell";
reg = <0x0 0x07640000 0x0 0x1000>;
cpu = <&cpu6>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm6_out: endpoint {
remote-endpoint = <&funnel_apss_in6>;
};
};
};
};
cti@7720000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x0 0x07720000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
};
etm@7740000 {
compatible = "arm,primecell";
reg = <0x0 0x07740000 0x0 0x1000>;
cpu = <&cpu7>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
arm,coresight-loses-context-with-cpu;
qcom,skip-power-up;
out-ports {
port {
etm7_out: endpoint {
remote-endpoint = <&funnel_apss_in7>;
};
};
};
};
funnel@7800000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x07800000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_apss_in0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
funnel_apss_in1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
port@2 {
reg = <2>;
funnel_apss_in2: endpoint {
remote-endpoint = <&etm2_out>;
};
};
port@3 {
reg = <3>;
funnel_apss_in3: endpoint {
remote-endpoint = <&etm3_out>;
};
};
port@4 {
reg = <4>;
funnel_apss_in4: endpoint {
remote-endpoint = <&etm4_out>;
};
};
port@5 {
reg = <5>;
funnel_apss_in5: endpoint {
remote-endpoint = <&etm5_out>;
};
};
port@6 {
reg = <6>;
funnel_apss_in6: endpoint {
remote-endpoint = <&etm6_out>;
};
};
port@7 {
reg = <7>;
funnel_apss_in7: endpoint {
remote-endpoint = <&etm7_out>;
};
};
};
out-ports {
port {
funnel_apss_out: endpoint {
remote-endpoint = <&funnel_apss_merg_in0>;
};
};
};
};
funnel@7810000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x0 0x07810000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel_apss_merg_in0: endpoint {
remote-endpoint = <&funnel_apss_out>;
};
};
port@2 {
reg = <2>;
funnel_apss_merg_in2: endpoint {
remote-endpoint = <&tpda_olc_out>;
};
};
port@3 {
reg = <3>;
funnel_apss_merg_in3: endpoint {
remote-endpoint = <&tpda_llm_silver_out>;
};
};
port@4 {
reg = <4>;
funnel_apss_merg_in4: endpoint {
remote-endpoint = <&tpda_llm_gold_out>;
};
};
port@5 {
reg = <5>;
funnel_apss_merg_in5: endpoint {
remote-endpoint = <&tpda_apss_out>;
};
};
};
out-ports {
port {
funnel_apss_merg_out: endpoint {
remote-endpoint = <&funnel_in1_in7>;
};
};
};
};
tpdm@7830000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x07830000 0x0 0x1000>;
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
qcom,cmb-element-bits = <64>;
--> --------------------
--> maximum size reached
--> --------------------
[ Dauer der Verarbeitung: 0.37 Sekunden
(vorverarbeitet)
]
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2026-04-06
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