// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2025 Google LLC * Author: Marc Zyngier <maz@kernel.org> #include <linux/kvm_host.h>#include <asm /sysreg.h>struct reg_bits_to_feat_map {#define NEVER_FGU BIT(0) /* Can trap, but never UNDEF */ #define CALL_FUNC BIT(1) /* Needs to evaluate tons of crap */ #define FIXED_VALUE BIT(2) /* RAZ/WI or RAO/WI in KVM */ unsigned long flags;union {struct {bool sign;bool (*match)(struct kvm *);bool (*fval)(struct kvm *, u64 *);#define __NEEDS_FEAT_3(m, f, id, fld, lim) \## id), \## _## fld ## _SHIFT, \## _## fld ## _WIDTH, \## _## fld ## _SIGNED , \## _## fld ## _## lim \#define __NEEDS_FEAT_2(m, f, fun, dummy) \#define __NEEDS_FEAT_1(m, f, fun) \#define NEEDS_FEAT_FLAG(m, f, ...) \#define NEEDS_FEAT_FIXED(m, ...) \#define NEEDS_FEAT(m, ...) NEEDS_FEAT_FLAG(m, 0, __VA_ARGS__)#define FEAT_SPE ID_AA64DFR0_EL1, PMSVer, IMP#define FEAT_SPE_FnE ID_AA64DFR0_EL1, PMSVer, V1P2#define FEAT_BRBE ID_AA64DFR0_EL1, BRBE, IMP#define FEAT_TRC_SR ID_AA64DFR0_EL1, TraceVer, IMP#define FEAT_PMUv3 ID_AA64DFR0_EL1, PMUVer, IMP#define FEAT_TRBE ID_AA64DFR0_EL1, TraceBuffer, IMP#define FEAT_TRBEv1p1 ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1#define FEAT_DoubleLock ID_AA64DFR0_EL1, DoubleLock, IMP#define FEAT_TRF ID_AA64DFR0_EL1, TraceFilt, IMP#define FEAT_AA32EL0 ID_AA64PFR0_EL1, EL0, AARCH32#define FEAT_AA32EL1 ID_AA64PFR0_EL1, EL1, AARCH32#define FEAT_AA64EL1 ID_AA64PFR0_EL1, EL1, IMP#define FEAT_AA64EL3 ID_AA64PFR0_EL1, EL3, IMP#define FEAT_AIE ID_AA64MMFR3_EL1, AIE, IMP#define FEAT_S2POE ID_AA64MMFR3_EL1, S2POE, IMP#define FEAT_S1POE ID_AA64MMFR3_EL1, S1POE, IMP#define FEAT_S1PIE ID_AA64MMFR3_EL1, S1PIE, IMP#define FEAT_THE ID_AA64PFR1_EL1, THE, IMP#define FEAT_SME ID_AA64PFR1_EL1, SME, IMP#define FEAT_GCS ID_AA64PFR1_EL1, GCS, IMP#define FEAT_LS64 ID_AA64ISAR1_EL1, LS64, LS64#define FEAT_LS64_V ID_AA64ISAR1_EL1, LS64, LS64_V#define FEAT_LS64_ACCDATA ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA#define FEAT_RAS ID_AA64PFR0_EL1, RAS, IMP#define FEAT_RASv2 ID_AA64PFR0_EL1, RAS, V2#define FEAT_GICv3 ID_AA64PFR0_EL1, GIC, IMP#define FEAT_LOR ID_AA64MMFR1_EL1, LO, IMP#define FEAT_SPEv1p2 ID_AA64DFR0_EL1, PMSVer, V1P2#define FEAT_SPEv1p4 ID_AA64DFR0_EL1, PMSVer, V1P4#define FEAT_SPEv1p5 ID_AA64DFR0_EL1, PMSVer, V1P5#define FEAT_ATS1A ID_AA64ISAR2_EL1, ATS1A, IMP#define FEAT_SPECRES2 ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX#define FEAT_SPECRES ID_AA64ISAR1_EL1, SPECRES, IMP#define FEAT_TLBIRANGE ID_AA64ISAR0_EL1, TLB, RANGE#define FEAT_TLBIOS ID_AA64ISAR0_EL1, TLB, OS#define FEAT_PAN2 ID_AA64MMFR1_EL1, PAN, PAN2#define FEAT_DPB2 ID_AA64ISAR1_EL1, DPB, DPB2#define FEAT_AMUv1 ID_AA64PFR0_EL1, AMU, IMP#define FEAT_AMUv1p1 ID_AA64PFR0_EL1, AMU, V1P1#define FEAT_CMOW ID_AA64MMFR1_EL1, CMOW, IMP#define FEAT_D128 ID_AA64MMFR3_EL1, D128, IMP#define FEAT_DoubleFault2 ID_AA64PFR1_EL1, DF2, IMP#define FEAT_FPMR ID_AA64PFR2_EL1, FPMR, IMP#define FEAT_MOPS ID_AA64ISAR2_EL1, MOPS, IMP#define FEAT_NMI ID_AA64PFR1_EL1, NMI, IMP#define FEAT_SCTLR2 ID_AA64MMFR3_EL1, SCTLRX, IMP#define FEAT_SYSREG128 ID_AA64ISAR2_EL1, SYSREG_128, IMP#define FEAT_TCR2 ID_AA64MMFR3_EL1, TCRX, IMP#define FEAT_XS ID_AA64ISAR1_EL1, XS, IMP#define FEAT_EVT ID_AA64MMFR2_EL1, EVT, IMP#define FEAT_EVT_TTLBxS ID_AA64MMFR2_EL1, EVT, TTLBxS#define FEAT_MTE2 ID_AA64PFR1_EL1, MTE, MTE2#define FEAT_RME ID_AA64PFR0_EL1, RME, IMP#define FEAT_MPAM ID_AA64PFR0_EL1, MPAM, 1#define FEAT_S2FWB ID_AA64MMFR2_EL1, FWB, IMP#define FEAT_TME ID_AA64ISAR0_EL1, TME, IMP#define FEAT_TWED ID_AA64MMFR1_EL1, TWED, IMP#define FEAT_E2H0 ID_AA64MMFR4_EL1, E2H0, IMP#define FEAT_SRMASK ID_AA64MMFR4_EL1, SRMASK, IMP#define FEAT_PoPS ID_AA64MMFR4_EL1, PoPS, IMP#define FEAT_PFAR ID_AA64PFR1_EL1, PFAR, IMP#define FEAT_Debugv8p9 ID_AA64DFR0_EL1, PMUVer, V3P9#define FEAT_PMUv3_SS ID_AA64DFR0_EL1, PMSS, IMP#define FEAT_SEBEP ID_AA64DFR0_EL1, SEBEP, IMP#define FEAT_EBEP ID_AA64DFR1_EL1, EBEP, IMP#define FEAT_ITE ID_AA64DFR1_EL1, ITE, IMP#define FEAT_PMUv3_ICNTR ID_AA64DFR1_EL1, PMICNTR, IMP#define FEAT_SPMU ID_AA64DFR1_EL1, SPMU, IMP#define FEAT_SPE_nVM ID_AA64DFR2_EL1, SPE_nVM, IMP#define FEAT_STEP2 ID_AA64DFR2_EL1, STEP, IMP#define FEAT_SYSREG128 ID_AA64ISAR2_EL1, SYSREG_128, IMP#define FEAT_CPA2 ID_AA64ISAR3_EL1, CPA, CPA2#define FEAT_ASID2 ID_AA64MMFR4_EL1, ASID2, IMP#define FEAT_MEC ID_AA64MMFR3_EL1, MEC, IMP#define FEAT_HAFT ID_AA64MMFR1_EL1, HAFDBS, HAFT#define FEAT_BTI ID_AA64PFR1_EL1, BT, IMP#define FEAT_ExS ID_AA64MMFR0_EL1, EXS, IMP#define FEAT_IESB ID_AA64MMFR2_EL1, IESB, IMP#define FEAT_LSE2 ID_AA64MMFR2_EL1, AT, IMP#define FEAT_LSMAOC ID_AA64MMFR2_EL1, LSM, IMP#define FEAT_MixedEnd ID_AA64MMFR0_EL1, BIGEND, IMP#define FEAT_MixedEndEL0 ID_AA64MMFR0_EL1, BIGENDEL0, IMP#define FEAT_MTE2 ID_AA64PFR1_EL1, MTE, MTE2#define FEAT_MTE_ASYNC ID_AA64PFR1_EL1, MTE_frac, ASYNC#define FEAT_MTE_STORE_ONLY ID_AA64PFR2_EL1, MTESTOREONLY, IMP#define FEAT_PAN ID_AA64MMFR1_EL1, PAN, IMP#define FEAT_PAN3 ID_AA64MMFR1_EL1, PAN, PAN3#define FEAT_SSBS ID_AA64PFR1_EL1, SSBS, IMP#define FEAT_TIDCP1 ID_AA64MMFR1_EL1, TIDCP1, IMP#define FEAT_FGT ID_AA64MMFR0_EL1, FGT, IMP#define FEAT_MTPMU ID_AA64DFR0_EL1, MTPMU, IMPstatic bool not_feat_aa64el3(struct kvm *kvm)return !kvm_has_feat(kvm, FEAT_AA64EL3);static bool feat_nv2(struct kvm *kvm)return ((kvm_has_feat(kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) &&static bool feat_nv2_e2h0_ni(struct kvm *kvm)return feat_nv2(kvm) && !kvm_has_feat(kvm, FEAT_E2H0);static bool feat_rasv1p1(struct kvm *kvm)return (kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) ||static bool feat_csv2_2_csv2_1p2(struct kvm *kvm)return (kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) ||static bool feat_pauth(struct kvm *kvm)return kvm_has_pauth(kvm, PAuth);static bool feat_pauth_lr(struct kvm *kvm)return kvm_has_pauth(kvm, PAuth_LR);static bool feat_aderr(struct kvm *kvm)return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, FEAT_ADERR) &&static bool feat_anerr(struct kvm *kvm)return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ANERR, FEAT_ANERR) &&static bool feat_sme_smps(struct kvm *kvm)/* * Revists this if KVM ever supports SME -- this really should * look at the guest's view of SMIDR_EL1. Funnily enough, this * is not captured in the JSON file, but only as a note in the * ARM ARM. return (kvm_has_feat(kvm, FEAT_SME) &&static bool feat_spe_fds(struct kvm *kvm)/* * Revists this if KVM ever supports SPE -- this really should * look at the guest's view of PMSIDR_EL1. return (kvm_has_feat(kvm, FEAT_SPEv1p4) &&static bool feat_trbe_mpam(struct kvm *kvm)/* * Revists this if KVM ever supports both MPAM and TRBE -- * this really should look at the guest's view of TRBIDR_EL1. return (kvm_has_feat(kvm, FEAT_TRBE) &&static bool feat_asid2_e2h1(struct kvm *kvm)return kvm_has_feat(kvm, FEAT_ASID2) && !kvm_has_feat(kvm, FEAT_E2H0);static bool feat_d128_e2h1(struct kvm *kvm)return kvm_has_feat(kvm, FEAT_D128) && !kvm_has_feat(kvm, FEAT_E2H0);static bool feat_mec_e2h1(struct kvm *kvm)return kvm_has_feat(kvm, FEAT_MEC) && !kvm_has_feat(kvm, FEAT_E2H0);static bool feat_ebep_pmuv3_ss(struct kvm *kvm)return kvm_has_feat(kvm, FEAT_EBEP) || kvm_has_feat(kvm, FEAT_PMUv3_SS);static bool feat_mixedendel0(struct kvm *kvm)return kvm_has_feat(kvm, FEAT_MixedEnd) || kvm_has_feat(kvm, FEAT_MixedEndEL0);static bool feat_mte_async(struct kvm *kvm)return kvm_has_feat(kvm, FEAT_MTE2) && kvm_has_feat_enum(kvm, FEAT_MTE_ASYNC);#define check_pmu_revision(k, r) \static bool feat_pmuv3p1(struct kvm *kvm)return check_pmu_revision(kvm, V3P1);static bool feat_pmuv3p5(struct kvm *kvm)return check_pmu_revision(kvm, V3P5);static bool feat_pmuv3p7(struct kvm *kvm)return check_pmu_revision(kvm, V3P7);static bool feat_pmuv3p9(struct kvm *kvm)return check_pmu_revision(kvm, V3P9);static bool compute_hcr_rw(struct kvm *kvm, u64 *bits)/* This is purely academic: AArch32 and NV are mutually exclusive */ if (bits) {if (kvm_has_feat(kvm, FEAT_AA32EL1))else return true ;static bool compute_hcr_e2h(struct kvm *kvm, u64 *bits)if (bits) {if (kvm_has_feat(kvm, FEAT_E2H0))else return true ;static const struct reg_bits_to_feat_map hfgrtr_feat_map[] = {static const struct reg_bits_to_feat_map hfgwtr_feat_map[] = {static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = {static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = {static const struct reg_bits_to_feat_map hfgitr_feat_map[] = {static const struct reg_bits_to_feat_map hafgrtr_feat_map[] = {static const struct reg_bits_to_feat_map hfgitr2_feat_map[] = {static const struct reg_bits_to_feat_map hfgrtr2_feat_map[] = {static const struct reg_bits_to_feat_map hfgwtr2_feat_map[] = {static const struct reg_bits_to_feat_map hdfgrtr2_feat_map[] = {static const struct reg_bits_to_feat_map hdfgwtr2_feat_map[] = {static const struct reg_bits_to_feat_map hcrx_feat_map[] = {static const struct reg_bits_to_feat_map hcr_feat_map[] = {/* Ignore the original FEAT_NV */ /* Missing from JSON */ static const struct reg_bits_to_feat_map sctlr2_feat_map[] = {static const struct reg_bits_to_feat_map tcr2_el2_feat_map[] = {static const struct reg_bits_to_feat_map sctlr_el1_feat_map[] = {static const struct reg_bits_to_feat_map mdcr_el2_feat_map[] = {static void __init check_feat_map(const struct reg_bits_to_feat_map *map,int map_size, u64 res0, const char *str)for (int i = 0; i < map_size; i++)if (mask != ~res0)"Undefined %s behaviour, bits %016llx\n" ,void __init check_feature_map(void )"HCRX_EL2" );"HCR_EL2" );"SCTLR2_EL1" );"TCR2_EL2" );"SCTLR_EL1" );"MDCR_EL2" );static bool idreg_feat_match(struct kvm *kvm, const struct reg_bits_to_feat_map *map)if (map->sign) {return sfld >= slim;else {return regfld >= map->lo_lim;static u64 __compute_fixed_bits(struct kvm *kvm,const struct reg_bits_to_feat_map *map,int map_size,unsigned long require,unsigned long exclude)for (int i = 0; i < map_size; i++) {bool match;if ((map[i].flags & require) != require)continue ;if (map[i].flags & exclude)continue ;if (map[i].flags & CALL_FUNC)else if (!match || (map[i].flags & FIXED_VALUE))return val;static u64 compute_res0_bits(struct kvm *kvm,const struct reg_bits_to_feat_map *map,int map_size,unsigned long require,unsigned long exclude)return __compute_fixed_bits(kvm, map, map_size, NULL,static u64 compute_fixed_bits(struct kvm *kvm,const struct reg_bits_to_feat_map *map,int map_size,unsigned long require,unsigned long exclude)return __compute_fixed_bits(kvm, map, map_size, fixed_bits,void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt)switch (fgt) {case HFGRTR_GROUP:break ;case HFGITR_GROUP:break ;case HDFGRTR_GROUP:break ;case HAFGRTR_GROUP:break ;case HFGRTR2_GROUP:break ;case HFGITR2_GROUP:break ;case HDFGRTR2_GROUP:break ;default :void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1)switch (reg) {case HFGRTR_EL2:break ;case HFGWTR_EL2:break ;case HFGITR_EL2:break ;case HDFGRTR_EL2:break ;case HDFGWTR_EL2:break ;case HAFGRTR_EL2:break ;case HFGRTR2_EL2:break ;case HFGWTR2_EL2:break ;case HFGITR2_EL2:break ;case HDFGRTR2_EL2:break ;case HDFGWTR2_EL2:break ;case HCRX_EL2:break ;case HCR_EL2:break ;case SCTLR2_EL1:case SCTLR2_EL2:break ;case TCR2_EL2:break ;case SCTLR_EL1:break ;case MDCR_EL2:break ;default :break ;
Messung V0.5 C=95 H=92 G=93
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¤ *© Formatika GbR, Deutschland
