/* make sure these clocks are enabled */ for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
__clk_init_enabled(enable_clks[i]); /* make sure these clocks are disabled */ for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
staticvoid __init m53xx_i2c_init(void)
{ #if IS_ENABLED(CONFIG_I2C_IMX) /* setup Port AS Pin Assignment Register for I2C */ /* set PASPA0 to SCL and PASPA1 to SDA */
u8 r = readb(MCFGPIO_PAR_FECI2C);
r |= 0x0f;
writeb(r, MCFGPIO_PAR_FECI2C); #endif/* IS_ENABLED(CONFIG_I2C_IMX) */
}
/* Set multi-function pins to ethernet mode for fec0 */
v = readb(MCFGPIO_PAR_FECI2C);
v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
writeb(v, MCFGPIO_PAR_FECI2C);
v = readb(MCFGPIO_PAR_FEC);
v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
writeb(v, MCFGPIO_PAR_FEC);
}
#ifdef CONFIG_BDM_DISABLE /* * Disable the BDM clocking. This also turns off most of the rest of * the BDM device. This is good for EMC reasons. This option is not * incompatible with the memory protection option.
*/
wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK); #endif
}
void wtm_init(void); void scm_init(void); void gpio_init(void); void fbcs_init(void); void sdramc_init(void); int clock_pll (int fsys, int flags); int clock_limp (int); int clock_exit_limp (void); int get_sys_clock (void);
void sdramc_init(void)
{ /* * Check to see if the SDRAM has already been initialized * by a run control tool
*/ if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) { /* SDRAM chip select initialization */
/* * Initialize TIN3 as a GPIO output to enable the write * half of the latch.
*/
writeb(0x00, MCFGPIO_PAR_TIMER);
writeb(0x08, MCFGPIO_PDDR_TIMER);
writeb(0x00, MCFGPIO_PCLRR_TIMER);
}
int clock_pll(int fsys, int flags)
{ int fref, temp, fout, mfd;
u32 i;
fref = FREF;
if (fsys == 0) { /* Return current PLL output */
mfd = readb(MCF_PLL_PFDR);
return (fref * mfd / (BUSDIV * 4));
}
/* Check bounds of requested system clock */ if (fsys > MAX_FSYS)
fsys = MAX_FSYS; if (fsys < MIN_FSYS)
fsys = MIN_FSYS;
/* Multiplying by 100 when calculating the temp value, and then dividing by 100 to calculate the mfd allows for exact values without needing to include floating
point libraries. */
temp = 100 * fsys / fref;
mfd = 4 * BUSDIV * temp / 100;
/* Determine the output frequency for selected values */
fout = (fref * mfd / (BUSDIV * 4));
/* * Check to see if the SDRAM has already been initialized. * If it has then the SDRAM needs to be put into self refresh * mode before reprogramming the PLL.
*/ if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF) /* Put SDRAM into self refresh mode */
writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR);
/* * Initialize the PLL to generate the new system clock frequency. * The device must be put into LIMP mode to reprogram the PLL.
*/
/* * Return the SDRAM to normal operation if it is in use.
*/ if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF) /* Exit self refresh mode */
writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
MCF_SDRAMC_SDCR);
/* Errata - workaround for SDRAM operation after exiting LIMP mode */
writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
/* wait for DQS logic to relock */ for (i = 0; i < 0x200; i++)
;
return fout;
}
int clock_limp(int div)
{
u32 temp;
/* Check bounds of divider */ if (div < MIN_LPD)
div = MIN_LPD; if (div > MAX_LPD)
div = MAX_LPD;
/* Save of the current value of the SSIDIV so we don't
overwrite the value*/
temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
/* Apply the divider to the system clock */
writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
/* Exit LIMP mode */
writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
/* Wait for PLL to lock */ while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
;
fout = get_sys_clock();
return fout;
}
int get_sys_clock(void)
{ int divider;
/* Test to see if device is in LIMP mode */ if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF); return (FREF/(2 << divider));
} else return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
}
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