/* fbio ioctls */ /* Returned by FBIOGTYPE */ struct fbtype { int fb_type; /* fb type, see above */ int fb_height; /* pixels */ int fb_width; /* pixels */ int fb_depth; int fb_cmsize; /* color map entries */ int fb_size; /* fb size in bytes */
}; #define FBIOGTYPE _IOR('F', 0, struct fbtype)
struct fbcmap { int index; /* first element (0 origin) */ int count; unsignedchar __user *red; unsignedchar __user *green; unsignedchar __user *blue;
};
struct mdi_cfginfo { int mdi_ncluts; /* Number of implemented CLUTs in this MDI */ int mdi_type; /* FBTYPE name */ int mdi_height; /* height */ int mdi_width; /* width */ int mdi_size; /* available ram */ int mdi_mode; /* 8bpp, 16bpp or 32bpp */ int mdi_pixfreq; /* pixel clock (from PROM) */
};
/* SparcLinux specific ioctl for the MDI, should be replaced for * the SET_XLUT/SET_CLUTn ioctls instead
*/ #define MDI_CLEAR_XLUT (MDI_IOCTL|9)
/* leo & ffb ioctls */ struct fb_clut_alloc {
__u32 clutid; /* Set on return */
__u32 flag;
__u32 index;
};
#ifdef __KERNEL__ /* Addresses on the fd of a cgsix that are mappable */ #define CG6_FBC 0x70000000 #define CG6_TEC 0x70001000 #define CG6_BTREGS 0x70002000 #define CG6_FHC 0x70004000 #define CG6_THC 0x70005000 #define CG6_ROM 0x70006000 #define CG6_RAM 0x70016000 #define CG6_DHC 0x80000000
#define CG3_MMAP_OFFSET 0x4000000
/* Addresses on the fd of a tcx that are mappable */ #define TCX_RAM8BIT 0x00000000 #define TCX_RAM24BIT 0x01000000 #define TCX_UNK3 0x10000000 #define TCX_UNK4 0x20000000 #define TCX_CONTROLPLANE 0x28000000 #define TCX_UNK6 0x30000000 #define TCX_UNK7 0x38000000 #define TCX_TEC 0x70000000 #define TCX_BTREGS 0x70002000 #define TCX_THC 0x70004000 #define TCX_DHC 0x70008000 #define TCX_ALT 0x7000a000 #define TCX_SYNC 0x7000e000 #define TCX_UNK2 0x70010000
/* CG14 definitions */
/* Offsets into the OBIO space: */ #define CG14_REGS 0 /* registers */ #define CG14_CURSORREGS 0x1000 /* cursor registers */ #define CG14_DACREGS 0x2000 /* DAC registers */ #define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */ #define CG14_CLUT1 0x4000 /* Color Look Up Table */ #define CG14_CLUT2 0x5000 /* Color Look Up Table */ #define CG14_CLUT3 0x6000 /* Color Look Up Table */ #define CG14_AUTO 0xf000
#endif/* KERNEL */
/* These are exported to userland for applications to use */ /* Mappable offsets for the cg14: control registers */ #define MDI_DIRECT_MAP 0x10000000 #define MDI_CTLREG_MAP 0x20000000 #define MDI_CURSOR_MAP 0x30000000 #define MDI_SHDW_VRT_MAP 0x40000000
/* Mappable offsets for the cg14: frame buffer resolutions */ /* 32 bits */ #define MDI_CHUNKY_XBGR_MAP 0x50000000 #define MDI_CHUNKY_BGR_MAP 0x60000000
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