// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved. * * Authors: * Alexander Graf <agraf@suse.de> * Kevin Wolf <mail@kevin-wolf.de> * Paul Mackerras <paulus@samba.org> * * Description: * Functions relating to running KVM on Book 3S processors where * we don't have access to hypervisor mode, and we run the guest * in problem state (user mode). * * This file is derived from arch/powerpc/kvm/44x.c, * by Hollis Blanchard <hollisb@us.ibm.com>.
*/
/* Guest MSR values */ #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE |
MSR_TM | MSR_TS_MASK; #else
smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE | MSR_LE; #endif /* Process MSR values */
smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE; /* External providers the guest reserved */
smsr |= (guest_msr & vcpu->arch.guest_owned_ext); /* 64-bit Process MSR values */ #ifdef CONFIG_PPC_BOOK3S_64
smsr |= MSR_HV; #endif #ifdef CONFIG_PPC_TRANSACTIONAL_MEM /* * in guest privileged state, we want to fail all TM transactions. * So disable MSR TM bit so that all tbegin. will be able to be * trapped into host.
*/ if (!(guest_msr & MSR_PR))
smsr &= ~MSR_TM; #endif
vcpu->arch.shadow_msr = smsr;
}
/* Copy data touched by real-mode code from shadow vcpu back to vcpu */ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu)
{ struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu); #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
ulong old_msr; #endif
/* * Maybe we were already preempted and synced the svcpu from * our preempt notifiers. Don't bother touching this svcpu then.
*/ if (!svcpu->in_use) goto out;
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM /* * Unlike other MSR bits, MSR[TS]bits can be changed at guest without * notifying host: * modified by unprivileged instructions like "tbegin"/"tend"/ * "tresume"/"tsuspend" in PR KVM guest. * * It is necessary to sync here to calculate a correct shadow_msr. * * privileged guest's tbegin will be failed at present. So we * only take care of problem state guest.
*/
old_msr = kvmppc_get_msr(vcpu); if (unlikely((old_msr & MSR_PR) &&
(vcpu->arch.shadow_srr1 & (MSR_TS_MASK)) !=
(old_msr & (MSR_TS_MASK)))) {
old_msr &= ~(MSR_TS_MASK);
old_msr |= (vcpu->arch.shadow_srr1 & (MSR_TS_MASK));
kvmppc_set_msr_fast(vcpu, old_msr);
kvmppc_recalc_shadow_msr(vcpu);
} #endif
/* loadup math bits which is enabled at kvmppc_get_msr() but not enabled at * hardware.
*/ staticvoid kvmppc_handle_lost_math_exts(struct kvm_vcpu *vcpu)
{
ulong exit_nr;
ulong ext_diff = (kvmppc_get_msr(vcpu) & ~vcpu->arch.guest_owned_ext) &
(MSR_FP | MSR_VEC | MSR_VSX);
if (kvmppc_get_msr(vcpu) & MSR_TM) {
kvmppc_handle_lost_math_exts(vcpu); if (vcpu->arch.fscr & FSCR_TAR)
kvmppc_handle_fac(vcpu, FSCR_TAR_LG);
}
} #endif
staticint kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu)
{ int r = 1; /* Indicate we want to get back into the guest */
/* We misuse TLB_FLUSH to indicate that we want to clear
all shadow cache entries */ if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
kvmppc_mmu_pte_flush(vcpu, 0, 0);
/* For PAPR guest, make sure MSR reflects guest mode */ if (vcpu->arch.papr_enabled)
msr = (msr & ~MSR_HV) | MSR_ME;
#ifdef EXIT_DEBUG
printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr); #endif
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM /* We should never target guest MSR to TS=10 && PR=0, * since we always fail transaction for guest privilege * state.
*/ if (!(msr & MSR_PR) && MSR_TM_TRANSACTIONAL(msr))
kvmppc_emulate_tabort(vcpu,
TM_CAUSE_KVM_FAC_UNAV | TM_CAUSE_PERSISTENT); #endif
/* * When switching from 32 to 64-bit, we may have a stale 32-bit * magic page around, we need to flush it. Typically 32-bit magic * page will be instantiated when calling into RTAS. Note: We * assume that such transition only happens while in kernel mode, * ie, we never transition from user 32-bit to kernel 64-bit with * a 32-bit magic page around.
*/ if (vcpu->arch.magic_page_pa &&
!(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) { /* going from RTAS to normal kernel code */
kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa,
~0xFFFUL);
}
/* Preload FPU if it's enabled */ if (kvmppc_get_msr(vcpu) & MSR_FP)
kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP);
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM if (kvmppc_get_msr(vcpu) & MSR_TM)
kvmppc_handle_lost_math_exts(vcpu); #endif
}
/* If we are in hypervisor level on 970, we can tell the CPU to
* treat DCBZ as 32 bytes store */
vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32; if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) &&
!strcmp(cur_cpu_spec->platform, "ppc970"))
vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
/* Cell performs badly if MSR_FEx are set. So let's hope nobody
really needs them in a VM on Cell and force disable them. */ if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be"))
to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1);
/* * If they're asking for POWER6 or later, set the flag * indicating that we can do multiple large page sizes * and 1TB segments. * Also set the flag that indicates that tlbie has the large * page bit in the RB operand instead of the instruction.
*/ switch (PVR_VER(pvr)) { case PVR_POWER6: case PVR_POWER7: case PVR_POWER7p: case PVR_POWER8: case PVR_POWER8E: case PVR_POWER8NVL: case PVR_HX_C2000: case PVR_POWER9:
vcpu->arch.hflags |= BOOK3S_HFLAG_MULTI_PGSIZE |
BOOK3S_HFLAG_NEW_TLBIE; break;
}
#ifdef CONFIG_PPC_BOOK3S_32 /* 32 bit Book3S always has 32 byte dcbz */
vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; #endif
/* On some CPUs we can execute paired single operations natively */ asm ( "mfpvr %0" : "=r"(host_pvr)); switch (host_pvr) { case 0x00080200: /* lonestar 2.0 */ case 0x00088202: /* lonestar 2.2 */ case 0x70000100: /* gekko 1.0 */ case 0x00080100: /* gekko 2.0 */ case 0x00083203: /* gekko 2.3a */ case 0x00083213: /* gekko 2.3b */ case 0x00083204: /* gekko 2.4 */ case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */ case 0x00087200: /* broadway */
vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS; /* Enable HID2.PSE - in case we need it later */
mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29));
}
}
/* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To * make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to * emulate 32 bytes dcbz length. * * The Book3s_64 inventors also realized this case and implemented a special bit * in the HID5 register, which is a hypervisor ressource. Thus we can't use it. * * My approach here is to patch the dcbz instruction on executing pages.
*/ staticvoid kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte)
{ struct kvm_host_map map;
u64 hpage_offset;
u32 *page; int i, r;
r = kvm_vcpu_map(vcpu, pte->raddr >> PAGE_SHIFT, &map); if (r) return;
/* patch dcbz into reserved instruction, so we trap */ for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++) if ((be32_to_cpu(page[i]) & 0xff0007ff) == INS_DCBZ)
page[i] &= cpu_to_be32(0xfffffff7);
if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
(!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { /* * If we do the dcbz hack, we have to NX on every execution, * so we can patch the executing code. This renders our guest * NX-less.
*/
pte.may_execute = !data;
}
if (page_found == -ENOENT || page_found == -EPERM) { /* Page not found in guest PTE entries, or protection fault */
u64 flags;
if (page_found == -EPERM)
flags = DSISR_PROTFAULT; else
flags = DSISR_NOHPTE; if (data) {
flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE;
kvmppc_core_queue_data_storage(vcpu, 0, eaddr, flags);
} else {
kvmppc_core_queue_inst_storage(vcpu, flags);
}
} elseif (page_found == -EINVAL) { /* Page not found in guest SLB */
kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu));
kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80);
} elseif (kvmppc_visible_gpa(vcpu, pte.raddr)) { if (data && !(vcpu->arch.fault_dsisr & DSISR_NOHPTE)) { /* * There is already a host HPTE there, presumably * a read-only one for a page the guest thinks * is writable, so get rid of it first.
*/
kvmppc_mmu_unmap_page(vcpu, &pte);
} /* The guest's PTE is not mapped yet. Map on the host */ if (kvmppc_mmu_map_page(vcpu, &pte, iswrite) == -EIO) { /* Exit KVM if mapping failed */
vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; return RESUME_HOST;
} if (data)
vcpu->stat.sp_storage++; elseif (vcpu->arch.mmu.is_dcbz32(vcpu) &&
(!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32)))
kvmppc_patch_dcbz(vcpu, &pte);
} else { /* MMIO */
vcpu->stat.mmio_exits++;
vcpu->arch.paddr_accessed = pte.raddr;
vcpu->arch.vaddr_accessed = pte.eaddr;
r = kvmppc_emulate_mmio(vcpu); if ( r == RESUME_HOST_NV )
r = RESUME_HOST;
}
/* * VSX instructions can access FP and vector registers, so if * we are giving up VSX, make sure we give up FP and VMX as well.
*/ if (msr & MSR_VSX)
msr |= MSR_FP | MSR_VEC;
msr &= vcpu->arch.guest_owned_ext; if (!msr) return;
#ifdef DEBUG_EXT
printk(KERN_INFO "Giving up ext 0x%lx\n", msr); #endif
if (msr & MSR_FP) { /* * Note that on CPUs with VSX, giveup_fpu stores * both the traditional FP registers and the added VSX * registers into thread.fp_state.fpr[].
*/ if (t->regs->msr & MSR_FP)
giveup_fpu(current);
t->fp_save_area = NULL;
}
#ifdef CONFIG_ALTIVEC if (msr & MSR_VEC) { if (current->thread.regs->msr & MSR_VEC)
giveup_altivec(current);
t->vr_save_area = NULL;
} #endif
/* When we have paired singles, we emulate in software */ if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) return RESUME_GUEST;
if (!(kvmppc_get_msr(vcpu) & msr)) {
kvmppc_book3s_queue_irqprio(vcpu, exit_nr); return RESUME_GUEST;
}
if (msr == MSR_VSX) { /* No VSX? Give an illegal instruction interrupt */ #ifdef CONFIG_VSX if (!cpu_has_feature(CPU_FTR_VSX)) #endif
{
kvmppc_core_queue_program(vcpu, SRR1_PROGILL); return RESUME_GUEST;
}
/* * We have to load up all the FP and VMX registers before * we can let the guest use VSX instructions.
*/
msr = MSR_FP | MSR_VEC | MSR_VSX;
}
/* See if we already own all the ext(s) needed */
msr &= ~vcpu->arch.guest_owned_ext; if (!msr) return RESUME_GUEST;
#ifdef DEBUG_EXT
printk(KERN_INFO "Loading up ext 0x%lx\n", msr); #endif
/* * Kernel code using FP or VMX could have flushed guest state to * the thread_struct; if so, get it back now.
*/ staticvoid kvmppc_handle_lost_ext(struct kvm_vcpu *vcpu)
{ unsignedlong lost_ext;
lost_ext = vcpu->arch.guest_owned_ext & ~current->thread.regs->msr; if (!lost_ext) return;
/* Enable facilities (TAR, EBB, DSCR) for the guest */ staticint kvmppc_handle_fac(struct kvm_vcpu *vcpu, ulong fac)
{ bool guest_fac_enabled;
BUG_ON(!cpu_has_feature(CPU_FTR_ARCH_207S));
/* * Not every facility is enabled by FSCR bits, check whether the * guest has this facility enabled at all.
*/ switch (fac) { case FSCR_TAR_LG: case FSCR_EBB_LG:
guest_fac_enabled = (vcpu->arch.fscr & (1ULL << fac)); break; case FSCR_TM_LG:
guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM; break; default:
guest_fac_enabled = false; break;
}
if (!guest_fac_enabled) { /* Facility not enabled by the guest */
kvmppc_trigger_fac_interrupt(vcpu, fac); return RESUME_GUEST;
}
switch (fac) { case FSCR_TAR_LG: /* TAR switching isn't lazy in Linux yet */
current->thread.tar = mfspr(SPRN_TAR);
mtspr(SPRN_TAR, vcpu->arch.tar);
vcpu->arch.shadow_fscr |= FSCR_TAR; break; default:
kvmppc_emulate_fac(vcpu, fac); break;
}
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM /* Since we disabled MSR_TM at privilege state, the mfspr instruction * for TM spr can trigger TM fac unavailable. In this case, the * emulation is handled by kvmppc_emulate_fac(), which invokes * kvmppc_emulate_mfspr() finally. But note the mfspr can include * RT for NV registers. So it need to restore those NV reg to reflect * the update.
*/ if ((fac == FSCR_TM_LG) && !(kvmppc_get_msr(vcpu) & MSR_PR)) return RESUME_GUEST_NV; #endif
return RESUME_GUEST;
}
void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr)
{ if (fscr & FSCR_SCV)
fscr &= ~FSCR_SCV; /* SCV must not be enabled */ /* Prohibit prefixed instructions for now */
fscr &= ~FSCR_PREFIX; if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) { /* TAR got dropped, drop it in shadow too */
kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
} elseif (!(vcpu->arch.fscr & FSCR_TAR) && (fscr & FSCR_TAR)) {
vcpu->arch.fscr = fscr;
kvmppc_handle_fac(vcpu, FSCR_TAR_LG); return;
}
/* * shadow_srr1 only contains valid flags if we came here via a program * exception. The other exceptions (emulation assist, FP unavailable, * etc.) do not provide flags in SRR1, so use an illegal-instruction * exception when injecting a program interrupt into the guest.
*/ if (exit_nr == BOOK3S_INTERRUPT_PROGRAM)
flags = vcpu->arch.shadow_srr1 & 0x1f0000ull; else
flags = SRR1_PROGILL;
vcpu->stat.emulated_inst_exits++;
er = kvmppc_emulate_instruction(vcpu); switch (er) { case EMULATE_DONE:
r = RESUME_GUEST_NV; break; case EMULATE_AGAIN:
r = RESUME_GUEST; break; case EMULATE_FAIL:
pr_crit("%s: emulation at %lx failed (%08x)\n",
__func__, kvmppc_get_pc(vcpu), ppc_inst_val(last_inst));
kvmppc_core_queue_program(vcpu, flags);
r = RESUME_GUEST; break; case EMULATE_DO_MMIO:
vcpu->run->exit_reason = KVM_EXIT_MMIO;
r = RESUME_HOST_NV; break; case EMULATE_EXIT_USER:
r = RESUME_HOST_NV; break; default:
BUG();
}
return r;
}
int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsignedint exit_nr)
{ struct kvm_run *run = vcpu->run; int r = RESUME_HOST; int s;
if (kvmppc_is_split_real(vcpu))
kvmppc_fixup_split_real(vcpu);
#ifdef CONFIG_PPC_BOOK3S_32 /* We set segments as unused segments when invalidating them. So
* treat the respective fault as segment fault. */
{ struct kvmppc_book3s_shadow_vcpu *svcpu;
u32 sr;
svcpu = svcpu_get(vcpu);
sr = svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT];
svcpu_put(svcpu); if (sr == SR_INVALID) {
kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu));
r = RESUME_GUEST; break;
}
} #endif
/* only care about PTEG not found errors, but leave NX alone */ if (shadow_srr1 & 0x40000000) { int idx = srcu_read_lock(&vcpu->kvm->srcu);
r = kvmppc_handle_pagefault(vcpu, kvmppc_get_pc(vcpu), exit_nr);
srcu_read_unlock(&vcpu->kvm->srcu, idx);
vcpu->stat.sp_instruc++;
} elseif (vcpu->arch.mmu.is_dcbz32(vcpu) &&
(!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) { /* * XXX If we do the dcbz hack we use the NX bit to flush&patch the page, * so we can't use the NX bit inside the guest. Let's cross our fingers, * that no guest that needs the dcbz hack does NX.
*/
kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL);
r = RESUME_GUEST;
} else {
kvmppc_core_queue_inst_storage(vcpu,
shadow_srr1 & 0x58000000);
r = RESUME_GUEST;
} break;
} case BOOK3S_INTERRUPT_DATA_STORAGE:
{
ulong dar = kvmppc_get_fault_dar(vcpu);
u32 fault_dsisr = vcpu->arch.fault_dsisr;
vcpu->stat.pf_storage++;
#ifdef CONFIG_PPC_BOOK3S_32 /* We set segments as unused segments when invalidating them. So
* treat the respective fault as segment fault. */
{ struct kvmppc_book3s_shadow_vcpu *svcpu;
u32 sr;
svcpu = svcpu_get(vcpu);
sr = svcpu->sr[dar >> SID_SHIFT];
svcpu_put(svcpu); if (sr == SR_INVALID) {
kvmppc_mmu_map_segment(vcpu, dar);
r = RESUME_GUEST; break;
}
} #endif
/* * We need to handle missing shadow PTEs, and * protection faults due to us mapping a page read-only * when the guest thinks it is writable.
*/ if (fault_dsisr & (DSISR_NOHPTE | DSISR_PROTFAULT)) { int idx = srcu_read_lock(&vcpu->kvm->srcu);
r = kvmppc_handle_pagefault(vcpu, dar, exit_nr);
srcu_read_unlock(&vcpu->kvm->srcu, idx);
} else {
kvmppc_core_queue_data_storage(vcpu, 0, dar, fault_dsisr);
r = RESUME_GUEST;
} break;
} case BOOK3S_INTERRUPT_DATA_SEGMENT: if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) {
kvmppc_set_dar(vcpu, kvmppc_get_fault_dar(vcpu));
kvmppc_book3s_queue_irqprio(vcpu,
BOOK3S_INTERRUPT_DATA_SEGMENT);
}
r = RESUME_GUEST; break; case BOOK3S_INTERRUPT_INST_SEGMENT: if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) {
kvmppc_book3s_queue_irqprio(vcpu,
BOOK3S_INTERRUPT_INST_SEGMENT);
}
r = RESUME_GUEST; break; /* We're good on these - the host merely wanted to get our attention */ case BOOK3S_INTERRUPT_DECREMENTER: case BOOK3S_INTERRUPT_HV_DECREMENTER: case BOOK3S_INTERRUPT_DOORBELL: case BOOK3S_INTERRUPT_H_DOORBELL:
vcpu->stat.dec_exits++;
r = RESUME_GUEST; break; case BOOK3S_INTERRUPT_EXTERNAL: case BOOK3S_INTERRUPT_EXTERNAL_HV: case BOOK3S_INTERRUPT_H_VIRT:
vcpu->stat.ext_intr_exits++;
r = RESUME_GUEST; break; case BOOK3S_INTERRUPT_HMI: case BOOK3S_INTERRUPT_PERFMON: case BOOK3S_INTERRUPT_SYSTEM_RESET:
r = RESUME_GUEST; break; case BOOK3S_INTERRUPT_PROGRAM: case BOOK3S_INTERRUPT_H_EMUL_ASSIST:
r = kvmppc_exit_pr_progint(vcpu, exit_nr); break; case BOOK3S_INTERRUPT_SYSCALL:
{
ppc_inst_t last_sc; int emul;
/* Get last sc for papr */ if (vcpu->arch.papr_enabled) { /* The sc instruction points SRR0 to the next inst */
emul = kvmppc_get_last_inst(vcpu, INST_SC, &last_sc); if (emul != EMULATE_DONE) {
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) - 4);
r = RESUME_GUEST; break;
}
}
run->exit_reason = KVM_EXIT_OSI; for (i = 0; i < 32; i++)
gprs[i] = kvmppc_get_gpr(vcpu, i);
vcpu->arch.osi_needed = 1;
r = RESUME_HOST_NV;
} elseif (!(kvmppc_get_msr(vcpu) & MSR_PR) &&
(((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) { /* KVM PV hypercalls */
kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
r = RESUME_GUEST;
} else { /* Guest syscalls */
vcpu->stat.syscall_exits++;
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
r = RESUME_GUEST;
} break;
} case BOOK3S_INTERRUPT_FP_UNAVAIL: case BOOK3S_INTERRUPT_ALTIVEC: case BOOK3S_INTERRUPT_VSX:
{ int ext_msr = 0; int emul;
ppc_inst_t last_inst;
if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) { /* Do paired single instruction emulation */
emul = kvmppc_get_last_inst(vcpu, INST_GENERIC,
&last_inst); if (emul == EMULATE_DONE)
r = kvmppc_exit_pr_progint(vcpu, exit_nr); else
r = RESUME_GUEST;
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
}
r = RESUME_GUEST; break;
} #ifdef CONFIG_PPC_BOOK3S_64 case BOOK3S_INTERRUPT_FAC_UNAVAIL:
r = kvmppc_handle_fac(vcpu, vcpu->arch.shadow_fscr >> 56); break; #endif case BOOK3S_INTERRUPT_MACHINE_CHECK:
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
r = RESUME_GUEST; break; case BOOK3S_INTERRUPT_TRACE: if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
run->exit_reason = KVM_EXIT_DEBUG;
r = RESUME_HOST;
} else {
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
r = RESUME_GUEST;
} break; default:
{
ulong shadow_srr1 = vcpu->arch.shadow_srr1; /* Ugh - bork here! What did we get? */
printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n",
exit_nr, kvmppc_get_pc(vcpu), shadow_srr1);
r = RESUME_HOST;
BUG(); break;
}
}
if (!(r & RESUME_HOST)) { /* To avoid clobbering exit_reason, only check for signals if * we aren't already exiting to userspace for some other
* reason. */
/* * Interrupts could be timers for the guest which we have to * inject again, so let's postpone them until we're in the guest * and if we really did time things so badly, then we just exit * again due to a host external interrupt.
*/
s = kvmppc_prepare_to_enter(vcpu); if (s <= 0)
r = s; else { /* interrupts now hard-disabled */
kvmppc_fix_ee_before_entry();
}
vcpu3s->sdr1 = sregs->u.s.sdr1; #ifdef CONFIG_PPC_BOOK3S_64 if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) { /* Flush all SLB entries */
vcpu->arch.mmu.slbmte(vcpu, 0, 0);
vcpu->arch.mmu.slbia(vcpu);
for (i = 0; i < 64; i++) {
u64 rb = sregs->u.s.ppc64.slb[i].slbe;
u64 rs = sregs->u.s.ppc64.slb[i].slbv;
if (rb & SLB_ESID_V)
vcpu->arch.mmu.slbmte(vcpu, rs, rb);
}
} else #endif
{ for (i = 0; i < 16; i++) {
vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]);
} for (i = 0; i < 8; i++) {
kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false,
(u32)sregs->u.s.ppc32.ibat[i]);
kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true,
(u32)(sregs->u.s.ppc32.ibat[i] >> 32));
kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false,
(u32)sregs->u.s.ppc32.dbat[i]);
kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true,
(u32)(sregs->u.s.ppc32.dbat[i] >> 32));
}
}
/* Flush the MMU after messing with the segments */
kvmppc_mmu_pte_flush(vcpu, 0, 0);
return 0;
}
staticint kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val)
{ int r = 0;
switch (id) { case KVM_REG_PPC_DEBUG_INST:
*val = get_reg_val(id, KVMPPC_INST_SW_BREAKPOINT); break; case KVM_REG_PPC_HIOR:
*val = get_reg_val(id, to_book3s(vcpu)->hior); break; case KVM_REG_PPC_VTB:
*val = get_reg_val(id, to_book3s(vcpu)->vtb); break; case KVM_REG_PPC_LPCR: case KVM_REG_PPC_LPCR_64: /* * We are only interested in the LPCR_ILE bit
*/ if (vcpu->arch.intr_msr & MSR_LE)
*val = get_reg_val(id, LPCR_ILE); else
*val = get_reg_val(id, 0); break; #ifdef CONFIG_PPC_TRANSACTIONAL_MEM case KVM_REG_PPC_TFHAR:
*val = get_reg_val(id, vcpu->arch.tfhar); break; case KVM_REG_PPC_TFIAR:
*val = get_reg_val(id, vcpu->arch.tfiar); break; case KVM_REG_PPC_TEXASR:
*val = get_reg_val(id, vcpu->arch.texasr); break; case KVM_REG_PPC_TM_GPR0 ... KVM_REG_PPC_TM_GPR31:
*val = get_reg_val(id,
vcpu->arch.gpr_tm[id-KVM_REG_PPC_TM_GPR0]); break; case KVM_REG_PPC_TM_VSR0 ... KVM_REG_PPC_TM_VSR63:
{ int i, j;
i = id - KVM_REG_PPC_TM_VSR0; if (i < 32) for (j = 0; j < TS_FPRWIDTH; j++)
val->vsxval[j] = vcpu->arch.fp_tm.fpr[i][j]; else { if (cpu_has_feature(CPU_FTR_ALTIVEC))
val->vval = vcpu->arch.vr_tm.vr[i-32]; else
r = -ENXIO;
} break;
} case KVM_REG_PPC_TM_CR:
*val = get_reg_val(id, vcpu->arch.cr_tm); break; case KVM_REG_PPC_TM_XER:
*val = get_reg_val(id, vcpu->arch.xer_tm); break; case KVM_REG_PPC_TM_LR:
*val = get_reg_val(id, vcpu->arch.lr_tm); break; case KVM_REG_PPC_TM_CTR:
*val = get_reg_val(id, vcpu->arch.ctr_tm); break; case KVM_REG_PPC_TM_FPSCR:
*val = get_reg_val(id, vcpu->arch.fp_tm.fpscr); break; case KVM_REG_PPC_TM_AMR:
*val = get_reg_val(id, vcpu->arch.amr_tm); break; case KVM_REG_PPC_TM_PPR:
*val = get_reg_val(id, vcpu->arch.ppr_tm); break; case KVM_REG_PPC_TM_VRSAVE:
*val = get_reg_val(id, vcpu->arch.vrsave_tm); break; case KVM_REG_PPC_TM_VSCR: if (cpu_has_feature(CPU_FTR_ALTIVEC))
*val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); else
r = -ENXIO; break; case KVM_REG_PPC_TM_DSCR:
*val = get_reg_val(id, vcpu->arch.dscr_tm); break; case KVM_REG_PPC_TM_TAR:
*val = get_reg_val(id, vcpu->arch.tar_tm); break; #endif default:
r = -EINVAL; break;
}
p = __get_free_page(GFP_KERNEL|__GFP_ZERO); if (!p) goto free_shadow_vcpu;
vcpu->arch.shared = (void *)p; #ifdef CONFIG_PPC_BOOK3S_64 /* Always start the shared struct in native endian mode */ #ifdef __BIG_ENDIAN__
vcpu->arch.shared_big_endian = true; #else
vcpu->arch.shared_big_endian = false; #endif
/* * Default to the same as the host if we're on sufficiently * recent machine that we have 1TB segments; * otherwise default to PPC970FX.
*/
vcpu->arch.pvr = 0x3C0301; if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
vcpu->arch.pvr = mfspr(SPRN_PVR);
vcpu->arch.intr_msr = MSR_SF; #else /* default to book3s_32 (750) */
vcpu->arch.pvr = 0x84202;
vcpu->arch.intr_msr = 0; #endif
kvmppc_set_pvr_pr(vcpu, vcpu->arch.pvr);
vcpu->arch.slb_nr = 64;
vcpu->arch.shadow_msr = MSR_USER64 & ~MSR_LE;
err = kvmppc_mmu_init_pr(vcpu); if (err < 0) goto free_shared_page;
staticint kvmppc_vcpu_run_pr(struct kvm_vcpu *vcpu)
{ int ret;
/* Check if we can run the vcpu at all */ if (!vcpu->arch.sane) {
vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
ret = -EINVAL; goto out;
}
kvmppc_setup_debug(vcpu);
/* * Interrupts could be timers for the guest which we have to inject * again, so let's postpone them until we're in the guest and if we * really did time things so badly, then we just exit again due to * a host external interrupt.
*/
ret = kvmppc_prepare_to_enter(vcpu); if (ret <= 0) goto out; /* interrupts now hard-disabled */
/* Save FPU, Altivec and VSX state */
giveup_all(current);
/* Preload FPU if it's enabled */ if (kvmppc_get_msr(vcpu) & MSR_FP)
kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP);
kvmppc_fix_ee_before_entry();
ret = __kvmppc_vcpu_run(vcpu);
kvmppc_clear_debug(vcpu);
/* No need for guest_exit. It's done in handle_exit.
We also get here with interrupts enabled. */
/* Make sure we save the guest FPU/Altivec/VSX state */
kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
/* Make sure we save the guest TAR/EBB/DSCR state */
kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
/* * Get (and clear) the dirty memory log for a memory slot.
*/ staticint kvm_vm_ioctl_get_dirty_log_pr(struct kvm *kvm, struct kvm_dirty_log *log)
{ struct kvm_memory_slot *memslot; struct kvm_vcpu *vcpu;
ulong ga, ga_end; int is_dirty = 0; int r; unsignedlong n;
mutex_lock(&kvm->slots_lock);
r = kvm_get_dirty_log(kvm, log, &is_dirty, &memslot); if (r) goto out;
/* If nothing is dirty, don't bother messing with page tables. */ if (is_dirty) {
ga = memslot->base_gfn << PAGE_SHIFT;
ga_end = ga + (memslot->npages << PAGE_SHIFT);
/* SLB is always 64 entries */
info->slb_size = 64;
/* Standard 4k base page size segment */
info->sps[0].page_shift = 12;
info->sps[0].slb_enc = 0;
info->sps[0].enc[0].page_shift = 12;
info->sps[0].enc[0].pte_enc = 0;
/* * 64k large page size. * We only want to put this in if the CPUs we're emulating * support it, but unfortunately we don't have a vcpu easily * to hand here to test. Just pick the first vcpu, and if * that doesn't exist yet, report the minimum capability, * i.e., no 64k pages. * 1T segment support goes along with 64k pages.
*/
i = 1;
vcpu = kvm_get_vcpu(kvm, 0); if (vcpu && (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) {
info->flags = KVM_PPC_1T_SEGMENTS;
info->sps[i].page_shift = 16;
info->sps[i].slb_enc = SLB_VSID_L | SLB_VSID_LP_01;
info->sps[i].enc[0].page_shift = 16;
info->sps[i].enc[0].pte_enc = 1;
++i;
}
/* Standard 16M large page size segment */
info->sps[i].page_shift = 24;
info->sps[i].slb_enc = SLB_VSID_L;
info->sps[i].enc[0].page_shift = 24;
info->sps[i].enc[0].pte_enc = 0;
return 0;
}
staticint kvm_configure_mmu_pr(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg)
{ if (!cpu_has_feature(CPU_FTR_ARCH_300)) return -ENODEV; /* Require flags and process table base and size to all be zero. */ if (cfg->flags || cfg->process_table) return -EINVAL; return 0;
}
#else staticint kvm_vm_ioctl_get_smmu_info_pr(struct kvm *kvm, struct kvm_ppc_smmu_info *info)
{ /* We should not get called */
BUG(); return 0;
} #endif/* CONFIG_PPC64 */
if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
spin_lock(&kvm_global_user_count_lock);
BUG_ON(kvm_global_user_count == 0); if (--kvm_global_user_count == 0)
pseries_enable_reloc_on_exc();
spin_unlock(&kvm_global_user_count_lock);
}
}
staticint kvmppc_core_check_processor_compat_pr(void)
{ /* * PR KVM can work on POWER9 inside a guest partition * running in HPT mode. It can't work if we are using * radix translation (because radix provides no way for * a process to have unique translations in quadrant 3).
*/ if (cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled()) return -EIO; return 0;
}
MODULE_DESCRIPTION("KVM on Book3S without using hypervisor mode");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(KVM_MINOR);
MODULE_ALIAS("devname:kvm"); #endif
Messung V0.5
¤ Dauer der Verarbeitung: 0.24 Sekunden
(vorverarbeitet)
¤
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:
Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.
