/* * Linux PTEL encoding. * * Hardware and software bit definitions for the PTEL value (see below for * notes on SH-X2 MMUs and 64-bit PTEs): * * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4). * * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set, * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT). * * In order to keep this relatively clean, do not use these for defining * SH-3 specific flags until all of the other unused bits have been * exhausted. * * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE. * * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages. * Bit 10 is used for _PAGE_ACCESSED, and bit 11 is used for _PAGE_SPECIAL. * * - On 29 bit platforms, bits 31 to 29 are used for the space attributes * and timing control which (together with bit 0) are moved into the * old-style PTEA on the parts that support it. * * SH-X2 MMUs and extended PTEs * * SH-X2 supports an extended mode TLB with split data arrays due to the * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and * SZ bit placeholders still exist in data array 1, but are implemented as * reserved bits, with the real logic existing in data array 2. * * The downside to this is that we can no longer fit everything in to a 32-bit * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus * side, this gives us quite a few spare bits to play with for future usage.
*/ /* Legacy and compat mode bits */ #define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */ #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */ #define _PAGE_DIRTY 0x004 /* D-bit : page changed */ #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */ #define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */ #define _PAGE_RW 0x020 /* PR0-bit : write access allowed */ #define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/ #define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */ #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */ #define _PAGE_PROTNONE 0x200 /* software: if not present */ #define _PAGE_ACCESSED 0x400 /* software: page referenced */ #define _PAGE_SPECIAL 0x800 /* software: special page */
#define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */ #define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */ #define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
#define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */ #define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */ #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
/* * Stub out _PAGE_SZHUGE if we don't have a good definition for it, * to make pte_mkhuge() happy.
*/ #ifndef _PAGE_SZHUGE # define _PAGE_SZHUGE (_PAGE_FLAGS_HARD) #endif
/* * Mask of bits that are to be preserved across pgprot changes.
*/ #define _PAGE_CHG_MASK \
(PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | \
_PAGE_DIRTY | _PAGE_SPECIAL)
/* * Certain architectures need to do special things when PTEs * within a page table are directly modified. Thus, the following * hook is made available.
*/ #ifdef CONFIG_X2TLB staticinlinevoid set_pte(pte_t *ptep, pte_t pte)
{
ptep->pte_high = pte.pte_high;
smp_wmb();
ptep->pte_low = pte.pte_low;
} #else #define set_pte(pteptr, pteval) (*(pteptr) = pteval) #endif
/* * (pmds are folded into pgds so this doesn't get actually called, * but the define is needed for a generic inline function.)
*/ #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
#ifdef CONFIG_X2TLB /* * We cheat a bit in the SH-X2 TLB case. As the permission bits are * individually toggled (and user permissions are entirely decoupled from * kernel permissions), we attempt to couple them a bit more sanely here.
*/
PTE_BIT_FUNC(high, wrprotect, &= ~(_PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE));
PTE_BIT_FUNC(high, mkwrite_novma, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE); #else
PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
PTE_BIT_FUNC(low, mkwrite_novma, |= _PAGE_RW);
PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE); #endif
/* * Macro and implementation to make a page protection as uncachable.
*/ #define pgprot_writecombine(prot) \
__pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
/* * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that * are !pte_none() && !pte_present(). * * Constraints: * _PAGE_PRESENT at bit 8 * _PAGE_PROTNONE at bit 9 * * For the normal case, we encode the swap type and offset into the swap PTE * such that bits 8 and 9 stay zero. For the 64-bit PTE case, we use the * upper 32 for the swap offset and swap type, following the same approach as * x86 PAE. This keeps the logic quite simple. * * As is evident by the Alpha code, if we ever get a 64-bit unsigned * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes * much cleaner..
*/
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