// SPDX-License-Identifier: GPL-2.0 /* * arch/sh/kernel/cpu/sh4a/clock-sh7343.c * * SH7343 clock framework support * * Copyright (C) 2009 Magnus Damm #include <linux/init.h>#include <linux/kernel.h>#include <linux/io.h>#include <linux/clkdev.h>#include <asm /clock.h>/* SH7343 registers */ #define FRQCR 0xa4150000#define VCLKCR 0xa4150004#define SCLKACR 0xa4150008#define SCLKBCR 0xa415000c#define PLLCR 0xa4150024#define MSTPCR0 0xa4150030#define MSTPCR1 0xa4150034#define MSTPCR2 0xa4150038#define DLLFRQ 0xa4150050/* Fixed 32 KHz root clock for RTC and Power Management purposes */ static struct clk r_clk = {/* * Default rate for the root input clock, reset this with clk_set_rate() * from the platform code. struct clk extal_clk = {/* The dll block multiplies the 32khz r_clk, may be used instead of extal */ static unsigned long dll_recalc(struct clk *clk)unsigned long mult;if (__raw_readl(PLLCR) & 0x1000)else return clk->parent->rate * mult;static struct sh_clk_ops dll_clk_ops = {static struct clk dll_clk = {static unsigned long pll_recalc(struct clk *clk)unsigned long mult = 1;if (__raw_readl(PLLCR) & 0x4000)return clk->parent->rate * mult;static struct sh_clk_ops pll_clk_ops = {static struct clk pll_clk = {struct clk *main_clks[] = {static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };static struct clk_div_mult_table div4_div_mult_table = {static struct clk_div4_table div4_table = {enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,#define DIV4(_reg, _bit, _mask, _flags) \struct clk div4_clks[DIV4_NR] = {enum { DIV6_V, DIV6_NR };struct clk div6_clks[DIV6_NR] = {#define MSTP(_parent, _reg, _bit, _flags) \enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,static struct clk mstp_clks[MSTP_NR] = {static struct clk_lookup lookups[] = {/* main clocks */ "rclk" , &r_clk),"extal" , &extal_clk),"dll_clk" , &dll_clk),"pll_clk" , &pll_clk),/* DIV4 clocks */ "cpu_clk" , &div4_clks[DIV4_I]),"umem_clk" , &div4_clks[DIV4_U]),"shyway_clk" , &div4_clks[DIV4_SH]),"bus_clk" , &div4_clks[DIV4_B]),"b3_clk" , &div4_clks[DIV4_B3]),"peripheral_clk" , &div4_clks[DIV4_P]),"siua_clk" , &div4_clks[DIV4_SIUA]),"siub_clk" , &div4_clks[DIV4_SIUB]),/* DIV6 clocks */ "video_clk" , &div6_clks[DIV6_V]),/* MSTP32 clocks */ "tlb0" , &mstp_clks[MSTP031]),"ic0" , &mstp_clks[MSTP030]),"oc0" , &mstp_clks[MSTP029]),"uram0" , &mstp_clks[MSTP028]),"xymem0" , &mstp_clks[MSTP026]),"intc3" , &mstp_clks[MSTP023]),"intc0" , &mstp_clks[MSTP022]),"dmac0" , &mstp_clks[MSTP021]),"sh0" , &mstp_clks[MSTP020]),"hudi0" , &mstp_clks[MSTP019]),"ubc0" , &mstp_clks[MSTP017]),"tmu_fck" , &mstp_clks[MSTP015]),"fck" , "sh-cmt-32.0" , &mstp_clks[MSTP014]),"rwdt0" , &mstp_clks[MSTP013]),"mfi0" , &mstp_clks[MSTP011]),"flctl0" , &mstp_clks[MSTP010]),"fck" , "sh-sci.0" , &mstp_clks[MSTP007]),"fck" , "sh-sci.1" , &mstp_clks[MSTP006]),"fck" , "sh-sci.2" , &mstp_clks[MSTP005]),"fck" , "sh-sci.3" , &mstp_clks[MSTP004]),"sio0" , &mstp_clks[MSTP003]),"siof0" , &mstp_clks[MSTP002]),"siof1" , &mstp_clks[MSTP001]),"i2c-sh_mobile.0" , &mstp_clks[MSTP109]),"i2c-sh_mobile.1" , &mstp_clks[MSTP108]),"tpu0" , &mstp_clks[MSTP225]),"irda0" , &mstp_clks[MSTP224]),"sdhi0" , &mstp_clks[MSTP218]),"mmcif0" , &mstp_clks[MSTP217]),"sim0" , &mstp_clks[MSTP216]),"keysc0" , &mstp_clks[MSTP214]),"tsif0" , &mstp_clks[MSTP213]),"s3d40" , &mstp_clks[MSTP212]),"usbf0" , &mstp_clks[MSTP211]),"siu0" , &mstp_clks[MSTP208]),"jpu0" , &mstp_clks[MSTP206]),"vou0" , &mstp_clks[MSTP205]),"beu0" , &mstp_clks[MSTP204]),"ceu0" , &mstp_clks[MSTP203]),"veu0" , &mstp_clks[MSTP202]),"vpu0" , &mstp_clks[MSTP201]),"lcdc0" , &mstp_clks[MSTP200]),int __init arch_clk_init(void )int k, ret = 0;/* autodetect extal or dll configuration */ if (__raw_readl(PLLCR) & 0x1000)else for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)if (!ret)if (!ret)if (!ret)return ret;
Messung V0.5 C=97 H=93 G=94
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