// SPDX-License-Identifier: GPL-2.0 /* Performance event support for sparc64. * * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net> * * This code is based almost entirely upon the x86 perf event * code, which is: * * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar * Copyright (C) 2009 Jaswinder Singh Rajput * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
*/
/* Two classes of sparc64 chips currently exist. All of which have * 32-bit counters which can generate overflow interrupts on the * transition from 0xffffffff to 0. * * All chips upto and including SPARC-T3 have two performance * counters. The two 32-bit counters are accessed in one go using a * single 64-bit register. * * On these older chips both counters are controlled using a single * control register. The only way to stop all sampling is to clear * all of the context (user, supervisor, hypervisor) sampling enable * bits. But these bits apply to both counters, thus the two counters * can't be enabled/disabled individually. * * Furthermore, the control register on these older chips have two * event fields, one for each of the two counters. It's thus nearly * impossible to have one counter going while keeping the other one * stopped. Therefore it is possible to get overflow interrupts for * counters not currently "in use" and that condition must be checked * in the overflow interrupt handler. * * So we use a hack, in that we program inactive counters with the * "sw_count0" and "sw_count1" events. These count how many times * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an * unusual way to encode a NOP and therefore will not trigger in * normal code. * * Starting with SPARC-T4 we have one control register per counter. * And the counters are stored in individual registers. The registers * for the counters are 64-bit but only a 32-bit counter is * implemented. The event selections on SPARC-T4 lack any * restrictions, therefore we can elide all of the complicated * conflict resolution code we have for SPARC-T3 and earlier chips.
*/
struct cpu_hw_events { /* Number of events currently scheduled onto this cpu. * This tells how many entries in the arrays below * are valid.
*/ int n_events;
/* Number of new events added since the last hw_perf_disable(). * This works because the perf event layer always adds new * events inside of a perf_{disable,enable}() sequence.
*/ int n_added;
/* Array of events current scheduled on this cpu. */ struct perf_event *event[MAX_HWEVENTS];
/* Array of encoded longs, specifying the %pcr register * encoding and the mask of PIC counters this even can * be scheduled on. See perf_event_encode() et al.
*/ unsignedlong events[MAX_HWEVENTS];
/* The current counter index assigned to an event. When the * event hasn't been programmed into the cpu yet, this will * hold PIC_NO_INDEX. The event->hw.idx value tells us where * we ought to schedule the event.
*/ int current_idx[MAX_HWEVENTS];
/* Software copy of %pcr register(s) on this cpu. */
u64 pcr[MAX_HWEVENTS];
/* An event map describes the characteristics of a performance * counter event. In particular it gives the encoding as well as * a mask telling which counters the event can be measured on. * * The mask is unused on SPARC-T4 and later.
*/ struct perf_event_map {
u16 encoding;
u8 pic_mask; #define PIC_NONE 0x00 #define PIC_UPPER 0x01 #define PIC_LOWER 0x02
};
/* Encode a perf_event_map entry into a long. */ staticunsignedlong perf_event_encode(conststruct perf_event_map *pmap)
{ return ((unsignedlong) pmap->encoding << 16) | pmap->pic_mask;
}
static u8 perf_event_get_msk(unsignedlong val)
{ return val & 0xff;
}
static u64 perf_event_get_enc(unsignedlong val)
{ return val >> 16;
}
struct sparc_pmu { conststruct perf_event_map *(*event_map)(int); const cache_map_t *cache_map; int max_events;
u32 (*read_pmc)(int); void (*write_pmc)(int, u64); int upper_shift; int lower_shift; int event_mask; int user_bit; int priv_bit; int hv_bit; int irq_bit; int upper_nop; int lower_nop; unsignedint flags; #define SPARC_PMU_ALL_EXCLUDES_SAME 0x00000001 #define SPARC_PMU_HAS_CONFLICTS 0x00000002 int max_hw_events; int num_pcrs; int num_pic_regs;
};
/* Niagara1 is very limited. The upper PIC is hard-locked to count * only instructions, so it is free running which creates all kinds of * problems. Some hardware designs make one wonder if the creator * even looked at how this stuff gets used by software.
*/ staticconststruct perf_event_map niagara1_perfmon_event_map[] = {
[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
[PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
[PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
[PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
};
/* We explicitly don't support hypervisor tracing. The T4 * generates the overflow event for precise events via a trap * which will not be generated (ie. it's completely lost) if * we happen to be in the hypervisor when the event triggers. * Essentially, the overflow event reporting is completely * unusable when you have hypervisor mode tracing enabled.
*/
.hv_bit = 0,
staticint sparc_perf_event_set_period(struct perf_event *event, struct hw_perf_event *hwc, int idx)
{
s64 left = local64_read(&hwc->period_left);
s64 period = hwc->sample_period; int ret = 0;
/* The period may have been changed by PERF_EVENT_IOC_PERIOD */ if (unlikely(period != hwc->last_period))
left = period - (hwc->last_period - left);
if (unlikely(left <= -period)) {
left = period;
local64_set(&hwc->period_left, left);
hwc->last_period = period;
ret = 1;
}
if (unlikely(left <= 0)) {
left += period;
local64_set(&hwc->period_left, left);
hwc->last_period = period;
ret = 1;
} if (left > MAX_PERIOD)
left = MAX_PERIOD;
/* On this PMU all PICs are programmed using a single PCR. Calculate * the combined control register value. * * For such chips we require that all of the events have the same * configuration, so just fetch the settings from the first entry.
*/ staticvoid calculate_single_pcr(struct cpu_hw_events *cpuc)
{ int i;
if (!cpuc->n_added) goto out;
/* Assign to counters all unassigned events. */ for (i = 0; i < cpuc->n_events; i++) { struct perf_event *cp = cpuc->event[i]; struct hw_perf_event *hwc = &cp->hw; int idx = hwc->idx;
u64 enc;
if (cpuc->current_idx[i] != PIC_NO_INDEX) continue;
staticvoid sparc_pmu_start(struct perf_event *event, int flags);
/* On this PMU each PIC has its own PCR control register. */ staticvoid calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
{ int i;
if (!cpuc->n_added) goto out;
for (i = 0; i < cpuc->n_events; i++) { struct perf_event *cp = cpuc->event[i]; struct hw_perf_event *hwc = &cp->hw; int idx = hwc->idx;
if (cpuc->current_idx[i] != PIC_NO_INDEX) continue;
cpuc->current_idx[i] = idx;
if (cp->hw.state & PERF_HES_ARCH) continue;
sparc_pmu_start(cp, PERF_EF_RELOAD);
}
out: for (i = 0; i < cpuc->n_events; i++) { struct perf_event *cp = cpuc->event[i]; int idx = cp->hw.idx;
cpuc->pcr[idx] |= cp->hw.config_base;
}
}
/* If performance event entries have been added, move existing events * around (if necessary) and then assign new entries to counters.
*/ staticvoid update_pcrs_for_enable(struct cpu_hw_events *cpuc)
{ if (cpuc->n_added)
read_in_all_counters(cpuc);
staticvoid sparc_pmu_del(struct perf_event *event, int _flags)
{ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); unsignedlong flags; int i;
local_irq_save(flags);
for (i = 0; i < cpuc->n_events; i++) { if (event == cpuc->event[i]) { /* Absorb the final count and turn off the * event.
*/
sparc_pmu_stop(event, PERF_EF_UPDATE);
/* Shift remaining entries down into * the existing slot.
*/ while (++i < cpuc->n_events) {
cpuc->event[i - 1] = cpuc->event[i];
cpuc->events[i - 1] = cpuc->events[i];
cpuc->current_idx[i - 1] =
cpuc->current_idx[i];
}
/* Make sure all events can be scheduled into the hardware at * the same time. This is simplified by the fact that we only * need to support 2 simultaneous HW events. * * As a side effect, the evts[]->hw.idx values will be assigned * on success. These are pending indexes. When the events are * actually programmed into the chip, these values will propagate * to the per-cpu cpuc->current_idx[] slots, see the code in * maybe_change_configuration() for details.
*/ staticint sparc_check_constraints(struct perf_event **evts, unsignedlong *events, int n_ev)
{
u8 msk0 = 0, msk1 = 0; int idx0 = 0;
/* This case is possible when we are invoked from * hw_perf_group_sched_in().
*/ if (!n_ev) return 0;
if (n_ev > sparc_pmu->max_hw_events) return -1;
if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) { int i;
for (i = 0; i < n_ev; i++)
evts[i]->hw.idx = i; return 0;
}
/* If both events can go on any counter, OK. */ if (msk0 == (PIC_UPPER | PIC_LOWER) &&
msk1 == (PIC_UPPER | PIC_LOWER)) goto success;
/* If one event is limited to a specific counter, * and the other can go on both, OK.
*/ if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
msk1 == (PIC_UPPER | PIC_LOWER)) { if (msk0 & PIC_LOWER)
idx0 = 1; goto success;
}
/* If the events are fixed to different counters, OK. */ if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
(msk0 == PIC_LOWER && msk1 == PIC_UPPER)) { if (msk0 & PIC_LOWER)
idx0 = 1; goto success;
}
staticint check_excludes(struct perf_event **evts, int n_prev, int n_new)
{ int eu = 0, ek = 0, eh = 0; struct perf_event *event; int i, n, first;
if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME)) return 0;
n = n_prev + n_new; if (n <= 1) return 0;
first = 1; for (i = 0; i < n; i++) {
event = evts[i]; if (first) {
eu = event->attr.exclude_user;
ek = event->attr.exclude_kernel;
eh = event->attr.exclude_hv;
first = 0;
} elseif (event->attr.exclude_user != eu ||
event->attr.exclude_kernel != ek ||
event->attr.exclude_hv != eh) { return -EAGAIN;
}
}
return 0;
}
staticint collect_events(struct perf_event *group, int max_count, struct perf_event *evts[], unsignedlong *events, int *current_idx)
{ struct perf_event *event; int n = 0;
/* * If group events scheduling transaction was started, * skip the schedulability test here, it will be performed * at commit time(->commit_txn) as a whole
*/ if (cpuc->txn_flags & PERF_PMU_TXN_ADD) goto nocheck;
if (check_excludes(cpuc->event, n0, 1)) goto out; if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) goto out;
nocheck:
cpuc->n_events++;
cpuc->n_added++;
ret = 0;
out:
local_irq_restore(flags); return ret;
}
/* does not support taken branch sampling */ if (has_branch_stack(event)) return -EOPNOTSUPP;
switch (attr->type) { case PERF_TYPE_HARDWARE: if (attr->config >= sparc_pmu->max_events) return -EINVAL;
pmap = sparc_pmu->event_map(attr->config); break;
case PERF_TYPE_HW_CACHE:
pmap = sparc_map_cache_event(attr->config); if (IS_ERR(pmap)) return PTR_ERR(pmap); break;
case PERF_TYPE_RAW:
pmap = NULL; break;
default: return -ENOENT;
}
if (pmap) {
hwc->event_base = perf_event_encode(pmap);
} else { /* * User gives us "(encoding << 16) | pic_mask" for * PERF_TYPE_RAW events.
*/
hwc->event_base = attr->config;
}
/* We save the enable bits in the config_base. */
hwc->config_base = sparc_pmu->irq_bit; if (!attr->exclude_user)
hwc->config_base |= sparc_pmu->user_bit; if (!attr->exclude_kernel)
hwc->config_base |= sparc_pmu->priv_bit; if (!attr->exclude_hv)
hwc->config_base |= sparc_pmu->hv_bit;
n = 0; if (event->group_leader != event) {
n = collect_events(event->group_leader,
sparc_pmu->max_hw_events - 1,
evts, events, current_idx_dmy); if (n < 0) return -EINVAL;
}
events[n] = hwc->event_base;
evts[n] = event;
if (check_excludes(evts, n, 1)) return -EINVAL;
if (sparc_check_constraints(evts, events, n + 1)) return -EINVAL;
hwc->idx = PIC_NO_INDEX;
/* Try to do all error checking before this point, as unwinding * state after grabbing the PMC is difficult.
*/
perf_event_grab_pmc();
event->destroy = hw_perf_event_destroy;
/* * Start group events scheduling transaction * Set the flag to make pmu::enable() not perform the * schedulability test, it will be performed at commit time
*/ staticvoid sparc_pmu_start_txn(struct pmu *pmu, unsignedint txn_flags)
{ struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
cpuhw->txn_flags = txn_flags; if (txn_flags & ~PERF_PMU_TXN_ADD) return;
perf_pmu_disable(pmu);
}
/* * Stop group events scheduling transaction * Clear the flag and pmu::enable() will perform the * schedulability test.
*/ staticvoid sparc_pmu_cancel_txn(struct pmu *pmu)
{ struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); unsignedint txn_flags;
WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
/* * Commit group events scheduling transaction * Perform the group schedulability test as a whole * Return 0 if success
*/ staticint sparc_pmu_commit_txn(struct pmu *pmu)
{ struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); int n;
if (!sparc_pmu) return -EINVAL;
WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
void perf_event_print_debug(void)
{ unsignedlong flags; int cpu, i;
if (!sparc_pmu) return;
local_irq_save(flags);
cpu = smp_processor_id();
pr_info("\n"); for (i = 0; i < sparc_pmu->num_pcrs; i++)
pr_info("CPU#%d: PCR%d[%016llx]\n",
cpu, i, pcr_ops->read_pcr(i)); for (i = 0; i < sparc_pmu->num_pic_regs; i++)
pr_info("CPU#%d: PIC%d[%016llx]\n",
cpu, i, pcr_ops->read_pic(i));
if (!atomic_read(&active_events)) return NOTIFY_DONE;
switch (cmd) { case DIE_NMI: break;
default: return NOTIFY_DONE;
}
start_clock = sched_clock();
regs = args->regs;
cpuc = this_cpu_ptr(&cpu_hw_events);
/* If the PMU has the TOE IRQ enable bits, we need to do a * dummy write to the %pcr to clear the overflow bits and thus * the interrupt. * * Do this before we peek at the counters to determine * overflow so we don't lose any events.
*/ if (sparc_pmu->irq_bit &&
sparc_pmu->num_pcrs == 1)
pcr_ops->write_pcr(0, cpuc->pcr[0]);
for (i = 0; i < cpuc->n_events; i++) { struct perf_event *event = cpuc->event[i]; int idx = cpuc->current_idx[i]; struct hw_perf_event *hwc;
u64 val;
if (sparc_pmu->irq_bit &&
sparc_pmu->num_pcrs > 1)
pcr_ops->write_pcr(idx, cpuc->pcr[idx]);
hwc = &event->hw;
val = sparc_perf_event_update(event, hwc, idx); if (val & (1ULL << 31)) continue;
perf_sample_data_init(&data, 0, hwc->last_period); if (!sparc_perf_event_set_period(event, hwc, idx)) continue;
if (kstack_is_trap_frame(current_thread_info(), regs)) { if (user_mode(regs)) break;
pc = regs->tpc;
fp = regs->u_regs[UREG_I6] + STACK_BIAS;
} else {
pc = sf->callers_pc;
fp = (unsignedlong)sf->fp + STACK_BIAS;
}
perf_callchain_store(entry, pc); #ifdef CONFIG_FUNCTION_GRAPH_TRACER if ((pc + 8UL) == (unsignedlong) &return_to_handler) { struct ftrace_ret_stack *ret_stack;
ret_stack = ftrace_graph_get_ret_stack(current,
graph); if (ret_stack) {
pc = ret_stack->ret;
perf_callchain_store(entry, pc);
graph++;
}
} #endif
} while (entry->nr < entry->max_stack);
}
staticinlineint
valid_user_frame(constvoid __user *fp, unsignedlong size)
{ /* addresses should be at least 4-byte aligned */ if (((unsignedlong) fp) & 3) return 0;
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