// SPDX-License-Identifier: GPL-2.0-only /* * Per core/cpu state * * Used to coordinate shared registers between HT threads or * among events on a single PMU. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt#include <linux/stddef.h>#include <linux/types.h>#include <linux/init.h>#include <linux/slab.h>#include <linux/export.h>#include <linux/nmi.h>#include <linux/kvm_host.h>#include <asm /cpufeature.h>#include <asm /debugreg.h>#include <asm /hardirq.h>#include <asm /intel-family.h>#include <asm /intel_pt.h>#include <asm /apic.h>#include <asm /cpu_device_id.h>#include <asm /msr.h>#include "../perf_event.h" /* * Intel PerfMon, used on Core and later. static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =/* pseudo-encoding */ static struct event_constraint intel_core_event_constraints[] __read_mostly =/* FP_ASSIST */ /* MUL */ /* DIV */ /* CYCLES_DIV_BUSY */ /* DELAYED_BYPASS */ /* FP_COMP_INSTR_RET */ static struct event_constraint intel_core2_event_constraints[] __read_mostly =/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* FP_COMP_OPS_EXE */ /* FP_ASSIST */ /* MUL */ /* DIV */ /* CYCLES_DIV_BUSY */ /* IDLE_DURING_DIV */ /* DELAYED_BYPASS */ /* RS_UOPS_DISPATCH_CYCLES */ /* ITLB_MISS_RETIRED (T30-9) */ /* MEM_LOAD_RETIRED */ static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* L1D_CACHE_LD */ /* L1D_CACHE_ST */ /* L1D_CACHE_LOCK */ /* L1D_ALL_REF */ /* L1D_PEND_MISS */ /* L1D_PREFETCH */ /* L1D */ /* CACHE_LOCK_CYCLES */ static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =/* must define OFFCORE_RSP_X first, see intel_fixup_er() */ static struct event_constraint intel_westmere_event_constraints[] __read_mostly =/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* L1D */ /* OFFCORE_REQUESTS_OUTSTANDING */ /* CACHE_LOCK_CYCLES */ /* SNOOPQ_REQUEST_OUTSTANDING */ static struct event_constraint intel_snb_event_constraints[] __read_mostly =/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ /* L1D_PEND_MISS.PENDING */ /* INST_RETIRED.PREC_DIST */ /* MEM_TRANS_RETIRED.LOAD_LATENCY */ /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ /* * When HT is off these events can only run on the bottom 4 counters * When HT is on, they are impacted by the HT bug and require EXCL access /* MEM_UOPS_RETIRED.* */ /* MEM_LOAD_UOPS_RETIRED.* */ /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ static struct event_constraint intel_ivb_event_constraints[] __read_mostly =/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* L1D_PEND_MISS.PENDING */ /* IDQ.EMPTY */ /* IDQ_UOPS_NOT_DELIVERED.CORE */ /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */ /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ /* CYCLE_ACTIVITY.STALLS_L2_PENDING */ /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */ /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ /* INST_RETIRED.PREC_DIST */ /* * When HT is off these events can only run on the bottom 4 counters * When HT is on, they are impacted by the HT bug and require EXCL access /* MEM_UOPS_RETIRED.* */ /* MEM_LOAD_UOPS_RETIRED.* */ /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ static struct extra_reg intel_westmere_extra_regs[] __read_mostly =/* must define OFFCORE_RSP_X first, see intel_fixup_er() */ static struct event_constraint intel_v1_event_constraints[] __read_mostly =static struct event_constraint intel_gen_event_constraints[] __read_mostly =/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* SLOTS */ static struct event_constraint intel_slm_event_constraints[] __read_mostly =/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* pseudo CPU_CLK_UNHALTED.REF */ static struct event_constraint intel_grt_event_constraints[] __read_mostly = {/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* pseudo CPU_CLK_UNHALTED.REF */ /* CPU_CLK_UNHALTED.REF_TSC_P */ static struct event_constraint intel_skt_event_constraints[] __read_mostly = {/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* pseudo CPU_CLK_UNHALTED.REF */ /* CPU_CLK_UNHALTED.REF_TSC_P */ /* TOPDOWN_BAD_SPECULATION.ALL */ /* TOPDOWN_FE_BOUND.ALL */ /* TOPDOWN_RETIRING.ALL */ static struct event_constraint intel_skl_event_constraints[] = {/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* INST_RETIRED.PREC_DIST */ /* * when HT is off, these can only run on the bottom 4 counters /* MEM_INST_RETIRED.* */ /* MEM_LOAD_RETIRED.* */ /* MEM_LOAD_L3_HIT_RETIRED.* */ /* MEM_TRANS_RETIRED.* */ /* FRONTEND_RETIRED.* */ static struct extra_reg intel_knl_extra_regs[] __read_mostly = {static struct extra_reg intel_snb_extra_regs[] __read_mostly = {/* must define OFFCORE_RSP_X first, see intel_fixup_er() */ static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {/* must define OFFCORE_RSP_X first, see intel_fixup_er() */ static struct extra_reg intel_skl_extra_regs[] __read_mostly = {/* * Note the low 8 bits eventsel code is not a continuous field, containing * some #GPing bits. These are masked out. static struct event_constraint intel_icl_event_constraints[] = {/* INST_RETIRED.ANY */ /* old INST_RETIRED.PREC_DIST */ /* INST_RETIRED.PREC_DIST */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* SLOTS */ /* SW_PREFETCH_ACCESS.* */ /* CYCLE_ACTIVITY.STALLS_TOTAL */ /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */ /* CYCLE_ACTIVITY.STALLS_MEM_ANY */ /* CYCLE_ACTIVITY.* */ static struct extra_reg intel_icl_extra_regs[] __read_mostly = {static struct extra_reg intel_glc_extra_regs[] __read_mostly = {static struct event_constraint intel_glc_event_constraints[] = {/* INST_RETIRED.ANY */ /* INST_RETIRED.PREC_DIST */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* CPU_CLK_UNHALTED.REF_TSC_P */ /* SLOTS */ /* * Generally event codes < 0x90 are restricted to counters 0-3. * The 0x2E and 0x3C are exception, which has no restriction. /* * Generally event codes >= 0x90 are likely to have no restrictions. * The exception are defined as above. static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {static struct event_constraint intel_lnc_event_constraints[] = {/* INST_RETIRED.ANY */ /* INST_RETIRED.PREC_DIST */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* CPU_CLK_UNHALTED.REF_TSC_P */ /* SLOTS */ static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {"event=0x0b,umask=0x10,ldlat=3" );"event=0xcd,umask=0x1,ldlat=3" );"event=0xcd,umask=0x2" );static struct attribute *nhm_mem_events_attrs[] = {/* * topdown events for Intel Core CPUs. * * The events are all in slots, which is a free slot in a 4 wide * pipeline. Some events are already reported in slots, for cycle * events we multiply by the pipeline width (4). * * With Hyper Threading on, topdown metrics are either summed or averaged * between the threads of a core: (count_t0 + count_t1). * * For the average case the metric is always scaled to pipeline width, * so we use factor 2 ((count_t0 + count_t1) / 2 * 4) "event=0x3c,umask=0x0" , /* cpu_clk_unhalted.thread */ "event=0x3c,umask=0x0,any=1" ); /* cpu_clk_unhalted.thread_any */ "4" , "2" );"event=0xe,umask=0x1" ); /* uops_issued.any */ "event=0xc2,umask=0x2" ); /* uops_retired.retire_slots */ "event=0x9c,umask=0x1" ); /* idq_uops_not_delivered_core */ "event=0xd,umask=0x3,cmask=1" , /* int_misc.recovery_cycles */ "event=0xd,umask=0x3,cmask=1,any=1" ); /* int_misc.recovery_cycles_any */ "4" , "2" );"event=0x00,umask=0x4" );"event=0x00,umask=0x80" );"event=0x00,umask=0x81" );"event=0x00,umask=0x82" );"event=0x00,umask=0x83" );"event=0x00,umask=0x84" );"event=0x00,umask=0x85" );"event=0x00,umask=0x86" );"event=0x00,umask=0x87" );static struct attribute *snb_events_attrs[] = {static struct attribute *snb_mem_events_attrs[] = {static struct event_constraint intel_hsw_event_constraints[] = {/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* L1D_PEND_MISS.PENDING */ /* INST_RETIRED.PREC_DIST */ /* MEM_TRANS_RETIRED.LOAD_LATENCY */ /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ /* * When HT is off these events can only run on the bottom 4 counters * When HT is on, they are impacted by the HT bug and require EXCL access /* MEM_UOPS_RETIRED.* */ /* MEM_LOAD_UOPS_RETIRED.* */ /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ static struct event_constraint intel_bdw_event_constraints[] = {/* INST_RETIRED.ANY */ /* CPU_CLK_UNHALTED.CORE */ /* CPU_CLK_UNHALTED.REF */ /* L1D_PEND_MISS.PENDING */ /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ /* * when HT is off, these can only run on the bottom 4 counters /* MEM_INST_RETIRED.* */ /* MEM_LOAD_RETIRED.* */ /* MEM_LOAD_L3_HIT_RETIRED.* */ /* MEM_TRANS_RETIRED.* */ static u64 intel_pmu_event_map(int hw_event)return intel_perfmon_event_map[hw_event];static __initconst const u64 glc_hw_cache_event_idsstatic __initconst const u64 glc_hw_cache_extra_regs/* * Notes on the events: * - data reads do not include code reads (comparable to earlier tables) * - data counts include speculative execution (except L1 write, dtlb, bpu) * - remote node access includes remote memory, remote cache, remote mmio. * - prefetches are not included in the counts. * - icache miss does not include decoded icache #define SKL_DEMAND_DATA_RD BIT_ULL(0)#define SKL_DEMAND_RFO BIT_ULL(1)#define SKL_ANY_RESPONSE BIT_ULL(16)#define SKL_SUPPLIER_NONE BIT_ULL(17)#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \#define SKL_SPL_HIT BIT_ULL(30)#define SKL_SNOOP_NONE BIT_ULL(31)#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)#define SKL_SNOOP_MISS BIT_ULL(33)#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)#define SKL_SNOOP_HITM BIT_ULL(36)#define SKL_SNOOP_NON_DRAM BIT_ULL(37)#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \#define SKL_DEMAND_WRITE SKL_DEMAND_RFO#define SKL_LLC_ACCESS SKL_ANY_RESPONSE#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \static __initconst const u64 skl_hw_cache_event_ids/* MEM_INST_RETIRED.ALL_LOADS */ /* L1D.REPLACEMENT */ /* MEM_INST_RETIRED.ALL_STORES */ /* ICACHE_64B.MISS */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* MEM_INST_RETIRED.ALL_LOADS */ /* DTLB_LOAD_MISSES.WALK_COMPLETED */ /* MEM_INST_RETIRED.ALL_STORES */ /* DTLB_STORE_MISSES.WALK_COMPLETED */ /* ITLB_MISSES.STLB_HIT */ /* ITLB_MISSES.WALK_COMPLETED */ /* BR_INST_RETIRED.ALL_BRANCHES */ /* BR_MISP_RETIRED.ALL_BRANCHES */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ static __initconst const u64 skl_hw_cache_extra_regs#define SNB_DMND_DATA_RD (1ULL << 0)#define SNB_DMND_RFO (1ULL << 1)#define SNB_DMND_IFETCH (1ULL << 2)#define SNB_DMND_WB (1ULL << 3)#define SNB_PF_DATA_RD (1ULL << 4)#define SNB_PF_RFO (1ULL << 5)#define SNB_PF_IFETCH (1ULL << 6)#define SNB_LLC_DATA_RD (1ULL << 7)#define SNB_LLC_RFO (1ULL << 8)#define SNB_LLC_IFETCH (1ULL << 9)#define SNB_BUS_LOCKS (1ULL << 10)#define SNB_STRM_ST (1ULL << 11)#define SNB_OTHER (1ULL << 15)#define SNB_RESP_ANY (1ULL << 16)#define SNB_NO_SUPP (1ULL << 17)#define SNB_LLC_HITM (1ULL << 18)#define SNB_LLC_HITE (1ULL << 19)#define SNB_LLC_HITS (1ULL << 20)#define SNB_LLC_HITF (1ULL << 21)#define SNB_LOCAL (1ULL << 22)#define SNB_REMOTE (0xffULL << 23)#define SNB_SNP_NONE (1ULL << 31)#define SNB_SNP_NOT_NEEDED (1ULL << 32)#define SNB_SNP_MISS (1ULL << 33)#define SNB_NO_FWD (1ULL << 34)#define SNB_SNP_FWD (1ULL << 35)#define SNB_HITM (1ULL << 36)#define SNB_NON_DRAM (1ULL << 37)#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)#define SNB_L3_ACCESS SNB_RESP_ANY#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)static __initconst const u64 snb_hw_cache_extra_regsstatic __initconst const u64 snb_hw_cache_event_ids/* MEM_UOP_RETIRED.LOADS */ /* L1D.REPLACEMENT */ /* MEM_UOP_RETIRED.STORES */ /* L1D.ALL_M_REPLACEMENT */ /* HW_PRE_REQ.DL1_MISS */ /* ICACHE.MISSES */ /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ /* MEM_UOP_RETIRED.ALL_LOADS */ /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ /* MEM_UOP_RETIRED.ALL_STORES */ /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ /* ITLB_MISSES.STLB_HIT */ /* ITLB_MISSES.CAUSES_A_WALK */ /* BR_INST_RETIRED.ALL_BRANCHES */ /* BR_MISP_RETIRED.ALL_BRANCHES */ /* * Notes on the events: * - data reads do not include code reads (comparable to earlier tables) * - data counts include speculative execution (except L1 write, dtlb, bpu) * - remote node access includes remote memory, remote cache, remote mmio. * - prefetches are not included in the counts because they are not * reliably counted. #define HSW_DEMAND_DATA_RD BIT_ULL(0)#define HSW_DEMAND_RFO BIT_ULL(1)#define HSW_ANY_RESPONSE BIT_ULL(16)#define HSW_SUPPLIER_NONE BIT_ULL(17)#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \#define HSW_SNOOP_NONE BIT_ULL(31)#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)#define HSW_SNOOP_MISS BIT_ULL(33)#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)#define HSW_SNOOP_HITM BIT_ULL(36)#define HSW_SNOOP_NON_DRAM BIT_ULL(37)#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD#define HSW_DEMAND_WRITE HSW_DEMAND_RFO#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\#define HSW_LLC_ACCESS HSW_ANY_RESPONSE#define BDW_L3_MISS_LOCAL BIT(26)#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \static __initconst const u64 hsw_hw_cache_event_ids/* MEM_UOPS_RETIRED.ALL_LOADS */ /* L1D.REPLACEMENT */ /* MEM_UOPS_RETIRED.ALL_STORES */ /* ICACHE.MISSES */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* MEM_UOPS_RETIRED.ALL_LOADS */ /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */ /* MEM_UOPS_RETIRED.ALL_STORES */ /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ /* ITLB_MISSES.STLB_HIT */ /* ITLB_MISSES.MISS_CAUSES_A_WALK */ /* BR_INST_RETIRED.ALL_BRANCHES */ /* BR_MISP_RETIRED.ALL_BRANCHES */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ static __initconst const u64 hsw_hw_cache_extra_regsstatic __initconst const u64 westmere_hw_cache_event_ids/* MEM_INST_RETIRED.LOADS */ /* L1D.REPL */ /* MEM_INST_RETURED.STORES */ /* L1D.M_REPL */ /* L1D_PREFETCH.REQUESTS */ /* L1D_PREFETCH.MISS */ /* L1I.READS */ /* L1I.MISSES */ /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ /* * Use RFO, not WRITEBACK, because a write miss would typically occur * on RFO. /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ /* MEM_INST_RETIRED.LOADS */ /* DTLB_LOAD_MISSES.ANY */ /* MEM_INST_RETURED.STORES */ /* MEM_STORE_RETIRED.DTLB_MISS */ /* INST_RETIRED.ANY_P */ /* ITLB_MISSES.ANY */ /* BR_INST_RETIRED.ALL_BRANCHES */ /* BPU_CLEARS.ANY */ /* * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; * See IA32 SDM Vol 3B 30.6.1.3 #define NHM_DMND_DATA_RD (1 << 0)#define NHM_DMND_RFO (1 << 1)#define NHM_DMND_IFETCH (1 << 2)#define NHM_DMND_WB (1 << 3)#define NHM_PF_DATA_RD (1 << 4)#define NHM_PF_DATA_RFO (1 << 5)#define NHM_PF_IFETCH (1 << 6)#define NHM_OFFCORE_OTHER (1 << 7)#define NHM_UNCORE_HIT (1 << 8)#define NHM_OTHER_CORE_HIT_SNP (1 << 9)#define NHM_OTHER_CORE_HITM (1 << 10)/* reserved */ #define NHM_REMOTE_CACHE_FWD (1 << 12)#define NHM_REMOTE_DRAM (1 << 13)#define NHM_LOCAL_DRAM (1 << 14)#define NHM_NON_DRAM (1 << 15)#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)#define NHM_REMOTE (NHM_REMOTE_DRAM)#define NHM_DMND_READ (NHM_DMND_DATA_RD)#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)static __initconst const u64 nehalem_hw_cache_extra_regsstatic __initconst const u64 nehalem_hw_cache_event_ids/* MEM_INST_RETIRED.LOADS */ /* L1D.REPL */ /* MEM_INST_RETURED.STORES */ /* L1D.M_REPL */ /* L1D_PREFETCH.REQUESTS */ /* L1D_PREFETCH.MISS */ /* L1I.READS */ /* L1I.MISSES */ /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ /* * Use RFO, not WRITEBACK, because a write miss would typically occur * on RFO. /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ /* L1D_CACHE_LD.MESI (alias) */ /* DTLB_LOAD_MISSES.ANY */ /* L1D_CACHE_ST.MESI (alias) */ /* MEM_STORE_RETIRED.DTLB_MISS */ /* INST_RETIRED.ANY_P */ /* ITLB_MISS_RETIRED */ /* BR_INST_RETIRED.ALL_BRANCHES */ /* BPU_CLEARS.ANY */ static __initconst const u64 core2_hw_cache_event_ids/* L1D_CACHE_LD.MESI */ /* L1D_CACHE_LD.I_STATE */ /* L1D_CACHE_ST.MESI */ /* L1D_CACHE_ST.I_STATE */ /* L1D_PREFETCH.REQUESTS */ /* L1I.READS */ /* L1I.MISSES */ /* L2_LD.MESI */ /* L2_LD.ISTATE */ /* L2_ST.MESI */ /* L2_ST.ISTATE */ /* L1D_CACHE_LD.MESI (alias) */ /* DTLB_MISSES.MISS_LD */ /* L1D_CACHE_ST.MESI (alias) */ /* DTLB_MISSES.MISS_ST */ /* INST_RETIRED.ANY_P */ /* ITLBMISSES */ /* BR_INST_RETIRED.ANY */ /* BP_INST_RETIRED.MISPRED */ static __initconst const u64 atom_hw_cache_event_ids/* L1D_CACHE.LD */ /* L1D_CACHE.ST */ /* L1I.READS */ /* L1I.MISSES */ /* L2_LD.MESI */ /* L2_LD.ISTATE */ /* L2_ST.MESI */ /* L2_ST.ISTATE */ /* L1D_CACHE_LD.MESI (alias) */ /* DTLB_MISSES.MISS_LD */ /* L1D_CACHE_ST.MESI (alias) */ /* DTLB_MISSES.MISS_ST */ /* INST_RETIRED.ANY_P */ /* ITLB.MISSES */ /* BR_INST_RETIRED.ANY */ /* BP_INST_RETIRED.MISPRED */ "event=0x3c" );"2" );/* no_alloc_cycles.not_delivered */ "event=0xca,umask=0x50" );"2" );/* uops_retired.all */ "event=0xc2,umask=0x10" );/* uops_retired.all */ "event=0xc2,umask=0x10" );static struct attribute *slm_events_attrs[] = {static struct extra_reg intel_slm_extra_regs[] __read_mostly =/* must define OFFCORE_RSP_X first, see intel_fixup_er() */ #define SLM_DMND_READ SNB_DMND_DATA_RD#define SLM_DMND_WRITE SNB_DMND_RFO#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)#define SLM_LLC_ACCESS SNB_RESP_ANY#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)static __initconst const u64 slm_hw_cache_extra_regsstatic __initconst const u64 slm_hw_cache_event_ids/* LD_DCU_MISS */ /* ICACHE.ACCESSES */ /* ICACGE.MISSES */ /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ /* LD_DTLB_MISS */ /* INST_RETIRED.ANY_P */ /* PAGE_WALKS.I_SIDE_WALKS */ /* BR_INST_RETIRED.ANY */ /* BP_INST_RETIRED.MISPRED */ "event=0x3c" );"3" );/* UOPS_NOT_DELIVERED.ANY */ "event=0x9c" );/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */ "event=0xca,umask=0x02" );/* UOPS_RETIRED.ANY */ "event=0xc2" );/* UOPS_ISSUED.ANY */ "event=0x0e" );static struct attribute *glm_events_attrs[] = {static struct extra_reg intel_glm_extra_regs[] __read_mostly = {/* must define OFFCORE_RSP_X first, see intel_fixup_er() */ #define GLM_DEMAND_DATA_RD BIT_ULL(0)#define GLM_DEMAND_RFO BIT_ULL(1)#define GLM_ANY_RESPONSE BIT_ULL(16)#define GLM_SNP_NONE_OR_MISS BIT_ULL(33)#define GLM_DEMAND_READ GLM_DEMAND_DATA_RD#define GLM_DEMAND_WRITE GLM_DEMAND_RFO#define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)#define GLM_LLC_ACCESS GLM_ANY_RESPONSE#define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)#define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)static __initconst const u64 glm_hw_cache_event_ids/* MEM_UOPS_RETIRED.ALL_LOADS */ /* MEM_UOPS_RETIRED.ALL_STORES */ /* ICACHE.ACCESSES */ /* ICACHE.MISSES */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* MEM_UOPS_RETIRED.ALL_LOADS */ /* MEM_UOPS_RETIRED.ALL_STORES */ /* INST_RETIRED.ANY_P */ /* ITLB.MISS */ /* BR_INST_RETIRED.ALL_BRANCHES */ /* BR_MISP_RETIRED.ALL_BRANCHES */ static __initconst const u64 glm_hw_cache_extra_regsstatic __initconst const u64 glp_hw_cache_event_ids/* MEM_UOPS_RETIRED.ALL_LOADS */ /* MEM_UOPS_RETIRED.ALL_STORES */ /* ICACHE.ACCESSES */ /* ICACHE.MISSES */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* OFFCORE_RESPONSE */ /* MEM_UOPS_RETIRED.ALL_LOADS */ /* DTLB_LOAD_MISSES.WALK_COMPLETED */ /* MEM_UOPS_RETIRED.ALL_STORES */ /* DTLB_STORE_MISSES.WALK_COMPLETED */ /* INST_RETIRED.ANY_P */ /* ITLB.MISS */
Messung V0.5 C=92 H=91 G=91
¤ Dauer der Verarbeitung: 0.33 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
