// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2022 MediaTek Inc. * Author: Garmin Chang <garmin.chang@mediatek.com> #include <dt-bindings/clock/mediatek,mt8188-clk.h>#include <dt-bindings/reset/mt8188-resets.h>#include <linux/clk-provider.h>#include <linux/platform_device.h>#include "clk-gate.h" #include "clk-mtk.h" static const struct mtk_gate_regs infra_ao0_cg_regs = {static const struct mtk_gate_regs infra_ao1_cg_regs = {static const struct mtk_gate_regs infra_ao2_cg_regs = {static const struct mtk_gate_regs infra_ao3_cg_regs = {static const struct mtk_gate_regs infra_ao4_cg_regs = {#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \#define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \#define GATE_INFRA_AO4(_id, _name, _parent, _shift) \static const struct mtk_gate infra_ao_clks[] = {/* INFRA_AO0 */ "infra_ao_pmic_tmr" , "top_pwrap_ulposc" , 0),"infra_ao_pmic_ap" , "top_pwrap_ulposc" , 1),"infra_ao_pmic_md" , "top_pwrap_ulposc" , 2),"infra_ao_pmic_conn" , "top_pwrap_ulposc" , 3),/* infra_ao_sej is main clock is for secure engine with JTAG support */ "infra_ao_sej" , "top_axi" , 5, CLK_IS_CRITICAL),"infra_ao_apxgpt" , "top_axi" , 6),"infra_ao_gce" , "top_axi" , 8),"infra_ao_gce2" , "top_axi" , 9),"infra_ao_therm" , "top_axi" , 10),"infra_ao_pwm_h" , "top_axi" , 15),"infra_ao_pwm1" , "top_pwm" , 16),"infra_ao_pwm2" , "top_pwm" , 17),"infra_ao_pwm3" , "top_pwm" , 18),"infra_ao_pwm4" , "top_pwm" , 19),"infra_ao_pwm" , "top_pwm" , 21),"infra_ao_uart0" , "top_uart" , 22),"infra_ao_uart1" , "top_uart" , 23),"infra_ao_uart2" , "top_uart" , 24),"infra_ao_uart3" , "top_uart" , 25),"infra_ao_uart4" , "top_uart" , 26),"infra_ao_gce_26m" , "clk26m" , 27),"infra_ao_dma" , "pad_fpc_ck" , 28),"infra_ao_uart5" , "top_uart" , 29),/* INFRA_AO1 */ "infra_ao_hdmi_26m" , "clk26m" , 0),"infra_ao_spi0" , "top_spi" , 1),"infra_ao_msdc0" , "top_msdc5hclk" , 2),"infra_ao_msdc1" , "top_axi" , 4),"infra_ao_msdc2" , "top_axi" , 5),"infra_ao_msdc0_clk" , "top_msdc50_0" , 6),/* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux. */ "infra_ao_dvfsrc" ,"clk26m" , 7, CLK_IS_CRITICAL),"infra_ao_trng" , "top_axi" , 9),"infra_ao_auxadc" , "clk26m" , 10),"infra_ao_cpum" , "top_axi" , 11),"infra_ao_hdmi_32k" , "clk32k" , 12),"infra_ao_cec_66m_hclk" , "top_axi" , 13),"infra_ao_pcie_tl_26m" , "clk26m" , 15),"infra_ao_msdc1_clk" , "top_msdc30_1" , 16),"infra_ao_cec_66m_bclk" , "top_axi" , 17),"infra_ao_pcie_tl_96m" , "top_tl" , 18),/* infra_ao_dapc is for device access permission control module */ "infra_ao_dapc" ,"top_axi" , 20, CLK_IS_CRITICAL),"infra_ao_ecc_66m_hclk" , "top_axi" , 23),"infra_ao_debugsys" , "top_axi" , 24),"infra_ao_audio" , "top_axi" , 25),"infra_ao_pcie_tl_32k" , "clk32k" , 26),"infra_ao_dbg_trace" , "top_axi" , 29),"infra_ao_dramc26" , "clk26m" , 31),/* INFRA_AO2 */ "infra_ao_irtx" , "top_axi" , 0),"infra_ao_disp_pwm" , "top_disp_pwm0" , 2),"infra_ao_cldmabclk" , "top_axi" , 3),"infra_ao_audio26m" , "clk26m" , 4),"infra_ao_spi1" , "top_spi" , 6),"infra_ao_spi2" , "top_spi" , 9),"infra_ao_spi3" , "top_spi" , 10),"infra_ao_fsspm" ,"top_sspm" , 15, CLK_IS_CRITICAL),"infra_ao_sspm_hclk" ,"top_axi" , 17, CLK_IS_CRITICAL),"infra_ao_apdma_bclk" , "top_axi" , 18),"infra_ao_spi4" , "top_spi" , 25),"infra_ao_spi5" , "top_spi" , 26),"infra_ao_cq_dma" , "top_axi" , 27),/* INFRA_AO3 */ "infra_ao_msdc0sf" , "top_msdc50_0" , 0),"infra_ao_msdc1sf" , "top_msdc50_0" , 1),"infra_ao_msdc2sf" , "top_msdc50_0" , 2),"infra_ao_i2s_dma" , "top_axi" , 5),"infra_ao_ap_msdc0" , "top_msdc50_0" , 7),"infra_ao_md_msdc0" , "top_msdc50_0" , 8),"infra_ao_msdc30_2" , "top_msdc30_2" , 9),"infra_ao_gcpu" , "top_gcpu" , 10),"infra_ao_pcie_peri_26m" , "clk26m" , 15),"infra_ao_gcpu_66m_bclk" , "top_axi" , 16),"infra_ao_gcpu_133m_bclk" , "top_axi" , 17),"infra_ao_disp_pwm1" , "top_disp_pwm1" , 20),"infra_ao_fbist2fpc" , "top_msdc50_0" , 24),/* infra_ao_dapc_sync is for device access permission control module */ "infra_ao_dapc_sync" ,"top_axi" , 25, CLK_IS_CRITICAL),"infra_ao_pcie_p1_peri_26m" , "clk26m" , 26),/* INFRA_AO4 */ /* infra_ao_133m_mclk_set/infra_ao_66m_mclk_set are main clocks of peripheral */ "infra_ao_133m_mclk_set" ,"top_axi" , 0, CLK_IS_CRITICAL),"infra_ao_66m_mclk_set" ,"top_axi" , 1, CLK_IS_CRITICAL),"infra_ao_pcie_pl_p_250m_p0" ,"pextp_pipe" , 7),"infra_ao_aes_msdcfde_0p" , "top_aes_msdcfde" , 18),static u16 infra_ao_rst_ofs[] = {static u16 infra_ao_idx_map[] = {static const struct mtk_clk_rst_desc infra_ao_rst_desc = {static const struct mtk_clk_desc infra_ao_desc = {static const struct of_device_id of_match_clk_mt8188_infra_ao[] = {"mediatek,mt8188-infracfg-ao" , .data = &infra_ao_desc },/* sentinel */ } static struct platform_driver clk_mt8188_infra_ao_drv = {"clk-mt8188-infra_ao" ,"MediaTek MT8188 infracfg clocks driver" );"GPL" );
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