/* * Copyright 2012-2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD *
*/
/** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
*/ #define MAX_SURFACES 4 /** * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
*/ #define MAX_PLANES 6 #define MAX_STREAMS 6 #define MIN_VIEWPORT_SIZE 12 #define MAX_NUM_EDP 2 #define MAX_SUPPORTED_FORMATS 7
// Sizes defined as multiples of 64KB enum det_size {
DET_SIZE_DEFAULT = 0,
DET_SIZE_192KB = 3,
DET_SIZE_256KB = 4,
DET_SIZE_320KB = 5,
DET_SIZE_384KB = 6
};
struct dc_plane_cap { enum dc_plane_type type;
uint32_t per_pixel_alpha : 1; struct {
uint32_t argb8888 : 1;
uint32_t nv12 : 1;
uint32_t fp16 : 1;
uint32_t p010 : 1;
uint32_t ayuv : 1;
} pixel_format_support; // max upscaling factor x1000 // upscaling factors are always >= 1 // for example, 1080p -> 8K is 4.0, or 4000 raw value struct {
uint32_t argb8888;
uint32_t nv12;
uint32_t fp16;
} max_upscale_factor; // max downscale factor x1000 // downscale factors are always <= 1 // for example, 8K -> 1080p is 0.25, or 250 raw value struct {
uint32_t argb8888;
uint32_t nv12;
uint32_t fp16;
} max_downscale_factor; // minimal width/height
uint32_t min_width;
uint32_t min_height;
};
/** * DOC: color-management-caps * * **Color management caps (DPP and MPC)** * * Modules/color calculates various color operations which are translated to * abstracted HW. DCE 5-12 had almost no important changes, but starting with * DCN1, every new generation comes with fairly major differences in color * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can * decide mapping to HW block based on logical capabilities.
*/
/** * struct rom_curve_caps - predefined transfer function caps for degamma and regamma * @srgb: RGB color space transfer func * @bt2020: BT.2020 transfer func * @gamma2_2: standard gamma * @pq: perceptual quantizer transfer function * @hlg: hybrid log–gamma transfer function
*/ struct rom_curve_caps {
uint16_t srgb : 1;
uint16_t bt2020 : 1;
uint16_t gamma2_2 : 1;
uint16_t pq : 1;
uint16_t hlg : 1;
};
/** * struct dpp_color_caps - color pipeline capabilities for display pipe and * plane blocks * * @dcn_arch: all DCE generations treated the same * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, * just plain 256-entry lookup * @icsc: input color space conversion * @dgam_ram: programmable degamma LUT * @post_csc: post color space conversion, before gamut remap * @gamma_corr: degamma correction * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared * with MPC by setting mpc:shared_3d_lut flag * @ogam_ram: programmable out/blend gamma LUT * @ocsc: output color space conversion * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT * * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
*/ struct dpp_color_caps {
uint16_t dcn_arch : 1;
uint16_t input_lut_shared : 1;
uint16_t icsc : 1;
uint16_t dgam_ram : 1;
uint16_t post_csc : 1;
uint16_t gamma_corr : 1;
uint16_t hw_3d_lut : 1;
uint16_t ogam_ram : 1;
uint16_t ocsc : 1;
uint16_t dgam_rom_for_yuv : 1; struct rom_curve_caps dgam_rom_caps; struct rom_curve_caps ogam_rom_caps;
};
/* Below structure is to describe the HW support for mem layout, extend support
range to match what OS could handle in the roadmap */ struct lut3d_caps {
uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ struct {
uint32_t swizzle_3d_rgb : 1;
uint32_t swizzle_3d_bgr : 1;
uint32_t linear_1d : 1;
} mem_layout_support; struct {
uint32_t unorm_12msb : 1;
uint32_t unorm_12lsb : 1;
uint32_t float_fp1_5_10 : 1;
} mem_format_support; struct {
uint32_t order_rgba : 1;
uint32_t order_bgra : 1;
} mem_pixel_order_support; /*< size options are 9, 17, 33, 45, 65 */ struct {
uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */
uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */
uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */
uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */
uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */
} lut_dim_caps;
};
/** * struct mpc_color_caps - color pipeline capabilities for multiple pipe and * plane combined blocks * * @gamut_remap: color transformation matrix * @ogam_ram: programmable out gamma LUT * @ocsc: output color space conversion matrix * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single * instance * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT * @mcm_3d_lut_caps: HW support cap for MCM LUT memory * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory * @preblend: whether color manager supports preblend with MPC
*/ struct mpc_color_caps {
uint16_t gamut_remap : 1;
uint16_t ogam_ram : 1;
uint16_t ocsc : 1;
uint16_t num_3dluts : 3;
uint16_t num_rmcm_3dluts : 3;
uint16_t shared_3d_lut:1; struct rom_curve_caps ogam_rom_caps; struct lut3d_caps mcm_3d_lut_caps; struct lut3d_caps rmcm_3d_lut_caps; bool preblend;
};
/** * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks * @dpp: color pipes caps for DPP * @mpc: color pipes caps for MPC
*/ struct dc_color_caps { struct dpp_color_caps dpp; struct mpc_color_caps mpc;
};
struct dc_dcc_setting { unsignedint max_compressed_blk_size; unsignedint max_uncompressed_blk_size; bool independent_64b_blks; //These bitfields to be used starting with DCN 3.0 struct {
uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0
uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0
uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)
uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case)
uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x
uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case)
} dcc_controls;
};
/* Surface update type is used by dc_update_surfaces_and_stream * The update type is determined at the very beginning of the function based * on parameters passed in and decides how much programming (or updating) is * going to be done during the call. * * UPDATE_TYPE_FAST is used for really fast updates that do not require much * logical calculations or hardware register programming. This update MUST be * ISR safe on windows. Currently fast update will only be used to flip surface * address. * * UPDATE_TYPE_MED is used for slower updates which require significant hw * re-programming however do not affect bandwidth consumption or clock * requirements. At present, this is the level at which front end updates * that do not require us to run bw_calcs happen. These are in/out transfer func * updates, viewport offset changes, recout size changes and pixel depth changes. * This update can be done at ISR, but we want to minimize how often this happens. * * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front * end related. Any time viewport dimensions, recout dimensions, scaling ratios or * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do * a full update. This cannot be done at ISR level and should be a rare event. * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting * underscan we don't expect to see this call at all.
*/
enum surface_update_type {
UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
UPDATE_TYPE_FULL, /* may need to shuffle resources */
};
enum in_game_fams_config {
INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
INGAME_FAMS_DISABLE, // disable in-game fams
INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies
};
/** * enum pipe_split_policy - Pipe split strategy supported by DCN * * This enum is used to define the pipe split policy supported by DCN. By * default, DC favors MPC_SPLIT_DYNAMIC.
*/ enum pipe_split_policy { /** * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the * pipe in order to bring the best trade-off between performance and * power consumption. This is the recommended option.
*/
MPC_SPLIT_DYNAMIC = 0,
/** * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not * try any sort of split optimization.
*/
MPC_SPLIT_AVOID = 1,
/** * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to * optimize the pipe utilization when using a single display; if the * user connects to a second display, DC will avoid pipe split.
*/
MPC_SPLIT_AVOID_MULT_DISP = 2,
};
/* * struct dc_clocks - DC pipe clocks * * For any clocks that may differ per pipe only the max is stored in this * structure
*/ struct dc_clocks { int dispclk_khz; int actual_dispclk_khz; int dppclk_khz; int actual_dppclk_khz; int disp_dpp_voltage_level_khz; int dcfclk_khz; int socclk_khz; int dcfclk_deep_sleep_khz; int fclk_khz; int phyclk_khz; int dramclk_khz; bool p_state_change_support; enum dcn_zstate_support_state zstate_support; bool dtbclk_en; int ref_dtbclk_khz; bool fclk_p_state_change_support; enum dcn_pwr_state pwr_state; /* * Elements below are not compared for the purposes of * optimization required
*/ bool prev_p_state_change_support; bool fclk_prev_p_state_change_support; int num_ways; int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM];
/* * @fw_based_mclk_switching * * DC has a mechanism that leverage the variable refresh rate to switch * memory clock in cases that we have a large latency to achieve the * memory clock change and a short vblank window. DC has some * requirements to enable this feature, and this field describes if the * system support or not such a feature.
*/ bool fw_based_mclk_switching; bool fw_based_mclk_switching_shut_down; int prev_num_ways; enum dtm_pstate dtm_level; int max_supported_dppclk_khz; int max_supported_dispclk_khz; int bw_dppclk_khz; /*a copy of dppclk_khz*/ int bw_dispclk_khz; int idle_dramclk_khz; int idle_fclk_khz; int subvp_prefetch_dramclk_khz; int subvp_prefetch_fclk_khz;
};
struct dc_bounding_box_overrides { int sr_exit_time_ns; int sr_enter_plus_exit_time_ns; int sr_exit_z8_time_ns; int sr_enter_plus_exit_z8_time_ns; int urgent_latency_ns; int percent_of_ideal_drambw; int dram_clock_change_latency_ns; int dummy_clock_change_latency_ns; int fclk_clock_change_latency_ns; /* This forces a hard min on the DCFCLK we use * for DML. Unlike the debug option for forcing * DCFCLK, this override affects watermark calculations
*/ int min_dcfclk_mhz;
};
/* * struct dc_debug_options - DC debug struct * * This struct provides a simple mechanism for developers to change some * configurations, enable/disable features, and activate extra debug options. * This can be very handy to narrow down whether some specific feature is * causing an issue or not.
*/ struct dc_debug_options { bool native422_support; bool disable_dsc; enum visual_confirm visual_confirm; int visual_confirm_rect_height;
/* * @pipe_split_policy: Define which pipe split policy is used by the * display core.
*/ enum pipe_split_policy pipe_split_policy; bool force_single_disp_pipe_split; bool voltage_align_fclk; bool disable_min_fclk;
/* Generic structure that can be used to query properties of DC. More fields * can be added as required.
*/ struct dc_current_properties { unsignedint cursor_size_limit;
};
int num_virtual_links; /* * If 'vbios_override' not NULL, it will be called instead * of the real VBIOS. Intended use is Diagnostics on FPGA.
*/ struct dc_bios *vbios_override; enum dce_environment dce_environment;
struct dpcd_vendor_signature vendor_signature; bool force_smu_not_present; /* * IP offset for run time initializaion of register addresses * * DCN3.5+ will fail dc_create() if these fields are null for them. They are * applicable starting with DCN32/321 and are not used for ASICs upstreamed * before them.
*/
uint32_t *dcn_reg_offsets;
uint32_t *nbio_reg_offsets;
uint32_t *clk_reg_offsets; void *bb_from_dmub;
};
struct dc *dc_create(conststruct dc_init_data *init_params); void dc_hardware_init(struct dc *dc);
int dc_get_vmid_use_vector(struct dc *dc); void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); /* Returns the number of vmids supported */ int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); void dc_init_callbacks(struct dc *dc, conststruct dc_callback_init *init_params); void dc_deinit_callbacks(struct dc *dc); void dc_destroy(struct dc **dc);
/* Surface Interfaces */
enum {
TRANSFER_FUNC_POINTS = 1025
};
struct dc_hdr_static_metadata { /* display chromaticities and white point in units of 0.00001 */ unsignedint chromaticity_green_x; unsignedint chromaticity_green_y; unsignedint chromaticity_blue_x; unsignedint chromaticity_blue_y; unsignedint chromaticity_red_x; unsignedint chromaticity_red_y; unsignedint chromaticity_white_point_x; unsignedint chromaticity_white_point_y;
struct dc_transfer_func { struct kref refcount; enum dc_transfer_func_type type; enum dc_transfer_func_predefined tf; /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
uint32_t sdr_ref_white_level; union { struct pwl_params pwl; struct dc_transfer_func_distributed_points tf_pts;
};
};
union dc_3dlut_state { struct {
uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
uint32_t rmu_mux_num:3; /*index of mux to use*/
uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
uint32_t mpc_rmu1_mux:4;
uint32_t mpc_rmu2_mux:4;
uint32_t reserved:15;
} bits;
uint32_t raw;
};
struct dc_3dlut { struct kref refcount; struct tetrahedral_params lut_3d; struct fixed31_32 hdr_multiplier; union dc_3dlut_state state;
}; /* * This structure is filled in by dc_surface_get_status and contains * the last requested address and the currently active address so the called * can determine if there are any outstanding flips
*/ struct dc_plane_status { struct dc_plane_address requested_address; struct dc_plane_address current_address; bool is_flip_pending; bool is_right_eye;
};
struct dc_scratch_space { /* used to temporarily backup plane states of a stream during * dc update. The reason is that plane states are overwritten * with surface updates in dc update. Once they are overwritten * current state is no longer valid. We want to temporarily * store current value in plane states so we can still recover * a valid current state during dc update.
*/ struct dc_plane_state plane_states[MAX_SURFACES];
struct dc_stream_state stream_state;
};
/* * A link contains one or more sinks and their connected status. * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
*/ struct dc_link { struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; unsignedint sink_count; struct dc_sink *local_sink; unsignedint link_index; enum dc_connection_type type; enum signal_type connector_signal; enum dc_irq_source irq_source_hpd; enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ enum dc_irq_source irq_source_read_request;/* Read Request */
bool is_hpd_filter_disabled; bool dp_ss_off;
/** * @link_state_valid: * * If there is no link and local sink, this variable should be set to * false. Otherwise, it should be set to true; usually, the function * core_link_enable_stream sets this field to true.
*/ bool link_state_valid; bool aux_access_disabled; bool sync_lt_in_progress; bool skip_stream_reenable; bool is_internal_display; /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ bool is_dig_mapping_flexible; bool hpd_status; /* HPD status of link without physical HPD pin. */ bool is_hpd_pending; /* Indicates a new received hpd */
/* USB4 DPIA links skip verifying link cap, instead performing the fallback method * for every link training. This is incompatible with DP LL compliance automation, * which expects the same link settings to be used every retry on a link loss. * This flag is used to skip the fallback when link loss occurs during automation.
*/ bool skip_fallback_on_link_loss;
bool edp_sink_present;
struct dp_trace dp_trace;
/* caps is the same as reported_link_cap. link_traing use * reported_link_cap. Will clean up. TODO
*/ struct dc_link_settings reported_link_cap; struct dc_link_settings verified_link_cap; struct dc_link_settings cur_link_settings; struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; struct dc_link_settings preferred_link_setting; /* preferred_training_settings are override values that * come from DM. DM is responsible for the memory * management of the override pointers.
*/ struct dc_link_training_overrides preferred_training_settings; struct dp_audio_test_data audio_test_data;
uint8_t ddc_hw_inst;
uint8_t hpd_src;
uint8_t link_enc_hw_inst; /* DIG link encoder ID. Used as index in link encoder resource pool. * For links with fixed mapping to DIG, this is not changed after dc_link * object creation.
*/ enum engine_id eng_id; enum engine_id dpia_preferred_eng_id;
bool test_pattern_enabled; /* Pending/Current test pattern are only used to perform and track * FIXED_VS retimer test pattern/lane adjustment override state. * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, * to perform specific lane adjust overrides before setting certain * PHY test patterns. In cases when lane adjust and set test pattern * calls are not performed atomically (i.e. performing link training), * pending_test_pattern will be invalid or contain a non-PHY test pattern * and current_test_pattern will contain required context for any future * set pattern/set lane adjust to transition between override state(s).
* */ enum dp_test_pattern current_test_pattern; enum dp_test_pattern pending_test_pattern;
union compliance_test_state compliance_test_state;
void *priv;
struct ddc_service *ddc;
enum dp_panel_mode panel_mode; bool aux_mode;
/* Private to DC core */
conststruct dc *dc;
struct dc_context *ctx;
struct panel_cntl *panel_cntl; struct link_encoder *link_enc; struct graphics_object_id link_id; /* Endpoint type distinguishes display endpoints which do not have entries * in the BIOS connector table from those that do. Helps when tracking link * encoder to display endpoint assignments.
*/ enum display_endpoint_type ep_type; union ddi_channel_mapping ddi_channel_mapping; struct connector_device_tag_info device_tag; struct dpcd_caps dpcd_caps;
uint32_t dongle_max_pix_clk; unsignedshort chip_caps; unsignedint dpcd_sink_count; struct hdcp_caps hdcp_caps; enum edp_revision edp_revision; union dpcd_sink_ext_caps dpcd_sink_ext_caps;
/* MST record stream using this link */ struct link_flags { bool dp_keep_receiver_powered; bool dp_skip_DID2; bool dp_skip_reset_segment; bool dp_skip_fs_144hz; bool dp_mot_reset_segment; /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ bool dpia_mst_dsc_always_on; /* Forced DPIA into TBT3 compatibility mode. */ bool dpia_forced_tbt3_mode; bool dongle_mode_timing_override; bool blank_stream_on_ocs_change; bool read_dpcd204h_on_irq_hpd; bool force_dp_ffe_preset; bool skip_phy_ssc_reduction;
} wa_flags; union dc_dp_ffe_preset forced_dp_ffe_preset; struct link_mst_stream_allocation_table mst_stream_alloc_table;
struct gpio *hpd_gpio; enum dc_link_fec_state fec_state; bool is_dds; bool is_display_mux_present; bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly
/* Scratch memory */ struct { struct { /* * For matching clock_limits table in driver with table * from PMFW.
*/ struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
} update_bw_bounding_box; struct dc_scratch_space current_state; struct dc_scratch_space new_state; struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack struct dc_link temp_link; bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */
} scratch;
bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); void populate_fast_updates(struct dc_fast_update *fast_update, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_update *stream_update); /* * Set up streams and links associated to drive sinks * The streams parameter is an absolute set of all active streams. * * After this call: * Phy, Encoder, Timing Generator are programmed and enabled. * New streams are enabled with blank stream; no memory read.
*/ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);
struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, struct dc_stream_state *stream, int mpcc_inst);
uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
/* The function returns minimum bandwidth required to drive a given timing * return - minimum required timing bandwidth in kbps.
*/
uint32_t dc_bandwidth_in_kbps_from_timing( conststruct dc_crtc_timing *timing, constenum dc_link_encoding_format link_encoding);
/* Link Interfaces */ /* Return an enumerated dc_link. * dc_link order is constant and determined at * boot time. They cannot be created or destroyed. * Use dc_get_caps() to get number of links.
*/ struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
/* Return instance id of the edp link. Inst 0 is primary edp link. */ bool dc_get_edp_link_panel_inst(conststruct dc *dc, conststruct dc_link *link, unsignedint *inst_out);
/* Return an array of link pointers to edp links. */ void dc_get_edp_links(conststruct dc *dc, struct dc_link **edp_links, int *edp_num);
void dc_set_edp_power(conststruct dc *dc, struct dc_link *edp_link, bool powerOn);
/* The function initiates detection handshake over the given link. It first * determines if there are display connections over the link. If so it initiates * detection protocols supported by the connected receiver device. The function * contains protocol specific handshake sequences which are sometimes mandatory * to establish a proper connection between TX and RX. So it is always * recommended to call this function as the first link operation upon HPD event * or power up event. Upon completion, the function will update link structure * in place based on latest RX capabilities. The function may also cause dpms * to be reset to off for all currently enabled streams to the link. It is DM's * responsibility to serialize detection and DPMS updates. * * @reason - Indicate which event triggers this detection. dc may customize * detection flow depending on the triggering events. * return false - if detection is not fully completed. This could happen when * there is an unrecoverable error during detection or detection is partially * completed (detection has been delegated to dm mst manager ie. * link->connection_type == dc_connection_mst_branch when returning false). * return true - detection is completed, link has been fully updated with latest * detection result.
*/ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
struct dc_sink_init_data;
/* When link connection type is dc_connection_mst_branch, remote sink can be * added to the link. The interface creates a remote sink and associates it with * current link. The sink will be retained by link until remove remote sink is * called. * * @dc_link - link the remote sink will be added to. * @edid - byte array of EDID raw data. * @len - size of the edid in byte * @init_data -
*/ struct dc_sink *dc_link_add_remote_sink( struct dc_link *dc_link, const uint8_t *edid, int len, struct dc_sink_init_data *init_data);
/* Remove remote sink from a link with dc_connection_mst_branch connection type. * @link - link the sink should be removed from * @sink - sink to be removed.
*/ void dc_link_remove_remote_sink( struct dc_link *link, struct dc_sink *sink);
/* Enable HPD interrupt handler for a given link */ void dc_link_enable_hpd(conststruct dc_link *link);
/* Disable HPD interrupt handler for a given link */ void dc_link_disable_hpd(conststruct dc_link *link);
/* determine if there is a sink connected to the link * * @type - dc_connection_single if connected, dc_connection_none otherwise. * return - false if an unexpected error occurs, true otherwise. * * NOTE: This function doesn't detect downstream sink connections i.e * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will * return dc_connection_single if the branch device is connected despite of * downstream sink's connection status.
*/ bool dc_link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type);
/* query current hpd pin value * return - true HPD is asserted (HPD high), false otherwise (HPD low) *
*/ bool dc_link_get_hpd_state(struct dc_link *link);
/* Getter for cached link status from given link */ conststruct dc_link_status *dc_link_get_status(conststruct dc_link *link);
/* enable/disable hardware HPD filter. * * @link - The link the HPD pin is associated with. * @enable = true - enable hardware HPD filter. HPD event will only queued to irq * handler once after no HPD change has been detected within dc default HPD * filtering interval since last HPD event. i.e if display keeps toggling hpd * pulses within default HPD interval, no HPD event will be received until HPD * toggles have stopped. Then HPD event will be queued to irq handler once after * dc default HPD filtering interval since last HPD event. * * @enable = false - disable hardware HPD filter. HPD event will be queued * immediately to irq handler after no HPD change has been detected within * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
*/ void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
/* submit i2c read/write payloads through ddc channel * @link_index - index to a link with ddc in i2c mode * @cmd - i2c command structure * return - true if success, false otherwise.
*/ bool dc_submit_i2c( struct dc *dc,
uint32_t link_index, struct i2c_command *cmd);
/* submit i2c read/write payloads through oem channel * @link_index - index to a link with ddc in i2c mode * @cmd - i2c command structure * return - true if success, false otherwise.
*/ bool dc_submit_i2c_oem( struct dc *dc, struct i2c_command *cmd);
enum aux_return_code_type; /* Attempt to transfer the given aux payload. This function does not perform * retries or handle error states. The reply is returned in the payload->reply * and the result through operation_result. Returns the number of bytes * transferred,or -1 on a failure.
*/ int dc_link_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result);
struct ddc_service *
dc_get_oem_i2c_device(struct dc *dc);
bool dc_is_oem_i2c_device_present( struct dc *dc,
size_t slave_address
);
/* return true if the connected receiver supports the hdcp version */ bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). * * TODO - When defer_handling is true the function will have a different purpose. * It no longer does complete hpd rx irq handling. We should create a separate * interface specifically for this case. * * Return: * true - Downstream port status changed. DM should call DC to do the * detection. * false - no change in Downstream port status. No further action required * from DM.
*/ bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, bool defer_handling, bool *has_left_work); /* handle DP specs define test automation sequence*/ void dc_link_dp_handle_automated_test(struct dc_link *link);
/* handle DP Link loss sequence and try to recover RX link loss with best * effort
*/ void dc_link_dp_handle_link_loss(struct dc_link *link);
/* Determine if hpd rx irq should be handled or ignored * return true - hpd rx irq should be handled. * return false - it is safe to ignore hpd rx irq event
*/ bool dc_link_dp_allow_hpd_rx_irq(conststruct dc_link *link);
/* Determine if link loss is indicated with a given hpd_irq_dpcd_data. * @link - link the hpd irq data associated with * @hpd_irq_dpcd_data - input hpd irq data * return - true if hpd irq data indicates a link lost
*/ bool dc_link_check_link_loss_status(struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data);
/* Read hpd rx irq data from a given link * @link - link where the hpd irq data should be read from * @irq_data - output hpd irq data * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data * read has failed.
*/ enum dc_status dc_link_dp_read_hpd_rx_irq_data( struct dc_link *link, union hpd_irq_data *irq_data);
/* The function clears recorded DP RX states in the link. DM should call this * function when it is resuming from S3 power state to previously connected links. * * TODO - in the future we should consider to expand link resume interface to * support clearing previous rx states. So we don't have to rely on dm to call * this interface explicitly.
*/ void dc_link_clear_dprx_states(struct dc_link *link);
/* Destruct the mst topology of the link and reset the allocated payload table * * NOTE: this should only be called if DM chooses not to call dc_link_detect but
* still wants to reset MST topology on an unplug event */ bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
/* The function calculates effective DP link bandwidth when a given link is * using the given link settings. * * return - total effective link bandwidth in kbps.
*/
uint32_t dc_link_bandwidth_kbps( conststruct dc_link *link, conststruct dc_link_settings *link_setting);
/* The function calculates the minimum size of hblank (in bytes) needed to * support the specified channel count and sample rate combination, given the * link encoding and timing to be used. This calculation is not supported * for 8b/10b SST. * * return - min hblank size in bytes, 0 if 8b/10b SST.
*/
uint32_t dc_link_required_hblank_size_bytes( conststruct dc_link *link, struct dp_audio_bandwidth_params *audio_params);
/* The function takes a snapshot of current link resource allocation state * @dc: pointer to dc of the dm calling this * @map: a dc link resource snapshot defined internally to dc. * * DM needs to capture a snapshot of current link resource allocation mapping * and store it in its persistent storage. * * Some of the link resource is using first come first serve policy. * The allocation mapping depends on original hotplug order. This information * is lost after driver is loaded next time. The snapshot is used in order to * restore link resource to its previous state so user will get consistent * link capability allocation across reboot. *
*/ void dc_get_cur_link_res_map(conststruct dc *dc, uint32_t *map);
/* This function restores link resource allocation state from a snapshot * @dc: pointer to dc of the dm calling this * @map: a dc link resource snapshot defined internally to dc. * * DM needs to call this function after initial link detection on boot and
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