/* * These devices are able to scan from 0 to N, N being the highest voltage * channel requested by the user. The temperature can be included or not, * but cannot be retrieved alone. Based on the below * ->available_scan_masks, the core will select the most appropriate * ->active_scan_mask and the "minimum" number of channels will be * scanned and pushed to the buffers. * * For example, if the user wants channels 1, 4 and 5, all channels from * 0 to 5 will be scanned and pushed to the IIO buffers. The core will then * filter out the unneeded samples based on the ->active_scan_mask that has * been selected and only channels 1, 4 and 5 will be available to the user * in the shared buffer.
*/ #define MAX1X27_SCAN_MASK_TEMP BIT(0)
if (st->spi->irq) {
ret = wait_for_completion_timeout(&st->complete,
msecs_to_jiffies(1000));
reinit_completion(&st->complete); if (!ret) return -ETIMEDOUT;
} else { if (indio_dev->active_scan_mask)
conversion_time *= hweight32(*indio_dev->active_scan_mask);
/* Scan from chan 0 to the highest requested channel. Include temperature on demand. */ staticint max1027_configure_chans_and_start(struct iio_dev *indio_dev)
{ struct max1027_state *st = iio_priv(indio_dev);
/* * Start acquisition on: * MODE0: external hardware trigger wired to the cnvst input pin * MODE2: conversion register write
*/ if (enable)
st->reg |= MAX1027_CKS_MODE0; else
st->reg |= MAX1027_CKS_MODE2;
return spi_write(st->spi, &st->reg, 1);
}
staticint max1027_read_single_value(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val)
{ int ret; struct max1027_state *st = iio_priv(indio_dev);
/* Configure conversion register with the requested chan */
st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
MAX1027_NOSCAN; if (chan->type == IIO_TEMP)
st->reg |= MAX1027_TEMP;
ret = spi_write(st->spi, &st->reg, 1); if (ret < 0) {
dev_err(&indio_dev->dev, "Failed to configure conversion register\n"); return ret;
}
/* * For an unknown reason, when we use the mode "10" (write * conversion register), the interrupt doesn't occur every time. * So we just wait the maximum conversion time and deliver the value.
*/
ret = max1027_wait_eoc(indio_dev); if (ret) return ret;
/* Read result */
ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2); if (ret < 0) return ret;
*val = be16_to_cpu(st->buffer[0]);
return IIO_VAL_INT;
}
staticint max1027_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask)
{ int ret = 0; struct max1027_state *st = iio_priv(indio_dev);
guard(mutex)(&st->lock);
switch (mask) { case IIO_CHAN_INFO_RAW: if (!iio_device_claim_direct(indio_dev)) return -EBUSY;
/* * In order to disable the convst trigger, start acquisition on * conversion register write, which basically disables triggering * conversions upon cnvst changes and thus has the effect of disabling * the external hardware trigger.
*/
ret = max1027_enable_trigger(indio_dev, state); if (ret) return ret;
if (state) {
ret = max1027_configure_chans_and_start(indio_dev); if (ret) return ret;
}
/* * If buffers are disabled (raw read) or when using external triggers, * we just need to unlock the waiters which will then handle the data. * * When using the internal trigger, we must hand-off the choice of the * handler to the core which will then lookup through the interrupt tree * for the right handler registered with iio_triggered_buffer_setup() * to execute, as this trigger might very well be used in conjunction * with another device. The core will then call the relevant handler to * perform the data processing step.
*/ if (!iio_buffer_enabled(indio_dev))
complete(&st->complete); else
iio_trigger_poll(indio_dev->trig);
st->buffer = devm_kmalloc_array(&indio_dev->dev,
indio_dev->num_channels, 2,
GFP_KERNEL); if (!st->buffer) return -ENOMEM;
/* Enable triggered buffers */
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
&iio_pollfunc_store_time,
&max1027_trigger_handler,
NULL); if (ret < 0) {
dev_err(&indio_dev->dev, "Failed to setup buffer\n"); return ret;
}
/* If there is an EOC interrupt, register the cnvst hardware trigger */ if (spi->irq) {
st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
indio_dev->name); if (!st->trig) {
ret = -ENOMEM;
dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n"); return ret;
}
st->trig->ops = &max1027_trigger_ops;
iio_trigger_set_drvdata(st->trig, indio_dev);
ret = devm_iio_trigger_register(&indio_dev->dev,
st->trig); if (ret < 0) {
dev_err(&indio_dev->dev, "Failed to register iio trigger\n"); return ret;
}
ret = devm_request_irq(&spi->dev, spi->irq, max1027_handler,
IRQF_TRIGGER_FALLING,
spi->dev.driver->name, indio_dev); if (ret < 0) {
dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n"); return ret;
}
}
/* Internal reset */
st->reg = MAX1027_RST_REG;
ret = spi_write(st->spi, &st->reg, 1); if (ret < 0) {
dev_err(&indio_dev->dev, "Failed to reset the ADC\n"); return ret;
}
/* Disable averaging */
st->reg = MAX1027_AVG_REG;
ret = spi_write(st->spi, &st->reg, 1); if (ret < 0) {
dev_err(&indio_dev->dev, "Failed to configure averaging register\n"); return ret;
}
/* Assume conversion on register write for now */
ret = max1027_enable_trigger(indio_dev, false); if (ret) return ret;
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