/* Signal strength */ if (*status & FE_HAS_SIGNAL) { for (i = 0; i < 2; i++) {
ret = regmap_bulk_read(dev->regmap[2], 0x8e + i,
&buf[i], 1); if (ret) goto err;
}
ret = regmap_write(dev->regmap[2], 0x00, 0x66); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x01, 0x00); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x02, 0x01); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x04, bandwidth_val); if (ret) goto err;
/* IF */
utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, dev->clk);
buf[0] = (utmp >> 16) & 0xff;
buf[1] = (utmp >> 8) & 0xff;
buf[2] = (utmp >> 0) & 0xff; for (i = 0; i < 3; i++) {
ret = regmap_write(dev->regmap[2], 0x10 + i, buf[i]); if (ret) goto err;
}
/* Bandwidth */ if (bandwidth_vals_ptr) { for (i = 0; i < 7; i++) {
ret = regmap_write(dev->regmap[2], 0x13 + i,
bandwidth_vals_ptr[i]); if (ret) goto err;
}
}
ret = regmap_write(dev->regmap[0], 0xb4, reg_bank0_b4_val); if (ret) goto err;
ret = regmap_write(dev->regmap[0], 0xcd, reg_bank0_cd_val); if (ret) goto err;
ret = regmap_write(dev->regmap[0], 0xd4, reg_bank0_d4_val); if (ret) goto err;
ret = regmap_write(dev->regmap[0], 0xd6, reg_bank0_d6_val); if (ret) goto err;
switch (c->delivery_system) { case SYS_DVBT:
ret = regmap_write(dev->regmap[0], 0x07, 0x26); if (ret) goto err;
ret = regmap_write(dev->regmap[0], 0x00, 0xba); if (ret) goto err;
ret = regmap_write(dev->regmap[0], 0x01, 0x13); if (ret) goto err; break; case SYS_DVBT2:
ret = regmap_write(dev->regmap[2], 0x2b, 0x13); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x4f, 0x05); if (ret) goto err;
ret = regmap_write(dev->regmap[1], 0xf6, 0x05); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x32,
(c->stream_id == NO_STREAM_ID_FILTER) ? 0 :
c->stream_id ); if (ret) goto err; break; case SYS_DVBC_ANNEX_A: break; default: break;
}
/* Reset FSM */
ret = regmap_write(dev->regmap[2], 0xf8, 0x9f); if (ret) goto err;
/* Power up */
ret = regmap_write(dev->regmap[2], 0x05, 0x00); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x0b, 0x00); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x0c, 0x00); if (ret) goto err;
/* Check if firmware is already running */
ret = regmap_read(dev->regmap[0], 0xf5, &utmp); if (ret) goto err; if (!(utmp & 0x01)) goto warm;
ret = request_firmware(&firmware, name, &client->dev); if (ret) {
dev_err(&client->dev, "firmware file '%s' not found\n", name); goto err;
}
dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
ret = regmap_write(dev->regmap[0], 0xf5, 0x03); if (ret) goto err_release_firmware;
for (rem = firmware->size; rem > 0; rem -= (dev->i2c_write_max - 1)) {
len = min(dev->i2c_write_max - 1, rem);
ret = regmap_bulk_write(dev->regmap[0], 0xf6,
&firmware->data[firmware->size - rem],
len); if (ret) {
dev_err(&client->dev, "firmware download failed %d\n",
ret); goto err_release_firmware;
}
}
/* Parity check of firmware */
ret = regmap_read(dev->regmap[0], 0xf8, &utmp); if (ret) goto err_release_firmware; if (utmp & 0x10) {
ret = -EINVAL;
dev_err(&client->dev, "firmware did not run\n"); goto err_release_firmware;
}
ret = regmap_write(dev->regmap[0], 0xf5, 0x00); if (ret) goto err_release_firmware;
release_firmware(firmware);
warm: /* TS config */ switch (dev->ts_mode) { case SERIAL_TS_MODE:
utmp = 0x1d; break; case PARALLEL_TS_MODE:
utmp = 0x00; break; default:
ret = -EINVAL; goto err;
}
ret = regmap_write(dev->regmap[2], 0x08, utmp); if (ret) goto err;
switch (dev->ts_clk) { case VARIABLE_TS_CLOCK:
utmp = 0xe3; break; case FIXED_TS_CLOCK:
utmp = 0xe1; break; default:
ret = -EINVAL; goto err;
}
ret = regmap_write(dev->regmap[0], 0xd9, utmp); if (ret) goto err;
/* Power down */
ret = regmap_write(dev->regmap[2], 0x0c, 0x30); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x0b, 0x30); if (ret) goto err;
ret = regmap_write(dev->regmap[2], 0x05, 0x3e); if (ret) goto err;
/* * Chip has three I2C addresses for different register banks. Used * addresses are 0x18, 0x1a and 0x1c. We register two dummy clients, * 0x1a and 0x1c, in order to get own I2C client for each register bank. * * Also, register bank 2 do not support sequential I/O. Only single * register write or read is allowed to that bank.
*/
dev->client[1] = i2c_new_dummy_device(client->adapter, 0x1a); if (IS_ERR(dev->client[1])) {
ret = PTR_ERR(dev->client[1]);
dev_err(&client->dev, "I2C registration failed\n"); goto err_regmap_0_regmap_exit;
}
dev->regmap[1] = regmap_init_i2c(dev->client[1], ®map_config); if (IS_ERR(dev->regmap[1])) {
ret = PTR_ERR(dev->regmap[1]); goto err_client_1_i2c_unregister_device;
}
i2c_set_clientdata(dev->client[1], dev);
dev->client[2] = i2c_new_dummy_device(client->adapter, 0x1c); if (IS_ERR(dev->client[2])) {
ret = PTR_ERR(dev->client[2]);
dev_err(&client->dev, "2nd I2C registration failed\n"); goto err_regmap_1_regmap_exit;
}
dev->regmap[2] = regmap_init_i2c(dev->client[2], ®map_config); if (IS_ERR(dev->regmap[2])) {
ret = PTR_ERR(dev->regmap[2]); goto err_client_2_i2c_unregister_device;
}
i2c_set_clientdata(dev->client[2], dev);
/* Check demod answers with correct chip id */
ret = regmap_read(dev->regmap[2], 0xff, &utmp); if (ret) goto err_regmap_2_regmap_exit;
dev_dbg(&client->dev, "chip id=%02x\n", utmp);
if (utmp != 0x02) {
ret = -ENODEV; goto err_regmap_2_regmap_exit;
}
/* Sleep because chip is active by default */
ret = regmap_write(dev->regmap[2], 0x05, 0x3e); if (ret) goto err_regmap_2_regmap_exit;
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