/* * Write data to the device. The bit should be set after 3 subframe * times (each frame is 64 clocks). We wait a maximum of 6 subframes. * We really should try doing something more productive while we * wait.
*/ staticvoid
mcp_sa11x0_write(struct mcp *mcp, unsignedint reg, unsignedint val)
{ struct mcp_sa11x0 *m = priv(mcp); int ret = -ETIME; int i;
for (i = 0; i < 2; i++) {
udelay(mcp->rw_timeout); if (readl_relaxed(MCSR(m)) & MCSR_CWC) {
ret = 0; break;
}
}
if (ret < 0)
printk(KERN_WARNING "mcp: write timed out\n");
}
/* * Read data from the device. The bit should be set after 3 subframe * times (each frame is 64 clocks). We wait a maximum of 6 subframes. * We really should try doing something more productive while we * wait.
*/ staticunsignedint
mcp_sa11x0_read(struct mcp *mcp, unsignedint reg)
{ struct mcp_sa11x0 *m = priv(mcp); int ret = -ETIME; int i;
writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m));
for (i = 0; i < 2; i++) {
udelay(mcp->rw_timeout); if (readl_relaxed(MCSR(m)) & MCSR_CRC) {
ret = readl_relaxed(MCDR2(m)) & 0xffff; break;
}
}
if (ret < 0)
printk(KERN_WARNING "mcp: read timed out\n");
m->base0 = ioremap(mem0->start, resource_size(mem0));
m->base1 = ioremap(mem1->start, resource_size(mem1)); if (!m->base0 || !m->base1) {
ret = -ENOMEM; goto err_ioremap;
}
platform_set_drvdata(dev, mcp);
/* * Initialise device. Note that we initially * set the sampling rate to minimum.
*/
writel_relaxed(-1, MCSR(m));
writel_relaxed(m->mccr1, MCCR1(m));
writel_relaxed(m->mccr0, MCCR0(m));
/* * Calculate the read/write timeout (us) from the bit clock * rate. This is the period for 3 64-bit frames. Always * round this time up.
*/
mcp->rw_timeout = DIV_ROUND_UP(64 * 3 * 1000000, mcp->sclk_rate);
ret = mcp_host_add(mcp, data->codec_pdata); if (ret == 0) return 0;
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