/* * NAND special boot partitions * * @page_offset: offset of the partition where spare data is not protected * by ECC (value in pages) * @page_offset: size of the partition where spare data is not protected * by ECC (value in pages)
*/ struct qcom_nand_boot_partition {
u32 page_offset;
u32 page_size;
};
/* * Qcom op for each exec_op transfer * * @data_instr: data instruction pointer * @data_instr_idx: data instruction index * @rdy_timeout_ms: wait ready timeout in ms * @rdy_delay_ns: Additional delay in ns * @addr1_reg: Address1 register value * @addr2_reg: Address2 register value * @cmd_reg: CMD register value * @flag: flag for misc instruction
*/ struct qcom_op { conststruct nand_op_instr *data_instr; unsignedint data_instr_idx; unsignedint rdy_timeout_ms; unsignedint rdy_delay_ns;
__le32 addr1_reg;
__le32 addr2_reg;
__le32 cmd_reg;
u8 flag;
};
/* * NAND chip structure * * @boot_partitions: array of boot partitions where offset and size of the * boot partitions are stored * * @chip: base NAND chip structure * @node: list node to add itself to host_list in * qcom_nand_controller * * @nr_boot_partitions: count of the boot partitions where spare data is not * protected by ECC * * @cs: chip select value for this chip * @cw_size: the number of bytes in a single step/codeword * of a page, consisting of all data, ecc, spare * and reserved bytes * @cw_data: the number of bytes within a codeword protected * by ECC * @ecc_bytes_hw: ECC bytes used by controller hardware for this * chip * * @last_command: keeps track of last command on this chip. used * for reading correct status * * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for * ecc/non-ecc mode for the current nand flash * device * * @status: value to be returned if NAND_CMD_STATUS command * is executed * @codeword_fixup: keep track of the current layout used by * the driver for read/write operation. * @use_ecc: request the controller to use ECC for the * upcoming read/write * @bch_enabled: flag to tell whether BCH ECC mode is used
*/ struct qcom_nand_host { struct qcom_nand_boot_partition *boot_partitions;
struct nand_chip chip; struct list_head node;
int nr_boot_partitions;
int cs; int cw_size; int cw_data; int ecc_bytes_hw; int spare_bytes; int bbm_size;
/* Helper to check whether this is the last CW or not */ staticbool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
{ return cw == (ecc->steps - 1);
}
/** * nandc_set_read_loc_first() - to set read location first register * @chip: NAND Private Flash Chip Data * @reg_base: location register base * @cw_offset: code word offset * @read_size: code word read length * @is_last_read_loc: is this the last read location * * This function will set location register value
*/ staticvoid nandc_set_read_loc_first(struct nand_chip *chip, int reg_base, u32 cw_offset,
u32 read_size, u32 is_last_read_loc)
{ struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
__le32 locreg_val;
u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
/** * nandc_set_read_loc_last - to set read location last register * @chip: NAND Private Flash Chip Data * @reg_base: location register base * @cw_offset: code word offset * @read_size: code word read length * @is_last_read_loc: is this the last read location * * This function will set location last register value
*/ staticvoid nandc_set_read_loc_last(struct nand_chip *chip, int reg_base, u32 cw_offset,
u32 read_size, u32 is_last_read_loc)
{ struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
__le32 locreg_val;
u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
/* * update_rw_regs: set up read/write register values, these will be * written to the NAND controller registers via DMA * * @num_cw: number of steps for the read/write operation * @read: read or write operation * @cw : which code word
*/ staticvoid update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, int cw)
{ struct nand_chip *chip = &host->chip;
__le32 cmd, cfg0, cfg1, ecc_bch_cfg; struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
/* * Helper to prepare dma descriptors to configure registers needed for reading a * single codeword in page
*/ staticvoid
config_nand_single_cw_page_read(struct nand_chip *chip, bool use_ecc, int cw)
{
config_nand_page_read(chip);
config_nand_cw_read(chip, use_ecc, cw);
}
/* * Helper to prepare DMA descriptors used to configure registers needed for * before writing a NAND page.
*/ staticvoid config_nand_page_write(struct nand_chip *chip)
{ struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
/* * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read * an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS. * * when using RS ECC, the HW reports the same erros when reading an erased CW, * but it notifies that it is an erased CW by placing special characters at * certain offsets in the buffer. * * verify if the page is erased or not, and fix up the page for RS ECC by * replacing the special characters with 0xff.
*/ staticbool erased_chunk_check_and_fixup(u8 *data_buf, int data_len)
{
u8 empty1, empty2;
/* * an erased page flags an error in NAND_FLASH_STATUS, check if the page * is erased by looking for 0x54s at offsets 3 and 175 from the * beginning of each codeword
*/
empty1 = data_buf[3];
empty2 = data_buf[175];
/* * if the erased codework markers, if they exist override them with * 0xffs
*/ if ((empty1 == 0x54 && empty2 == 0xff) ||
(empty1 == 0xff && empty2 == 0x54)) {
data_buf[3] = 0xff;
data_buf[175] = 0xff;
}
/* * check if the entire chunk contains 0xffs or not. if it doesn't, then * restore the original values at the special offsets
*/ if (memchr_inv(data_buf, 0xff, data_len)) {
data_buf[3] = empty1;
data_buf[175] = empty2;
/* reads back FLASH_STATUS register set by the controller */ staticint check_flash_errors(struct qcom_nand_host *host, int cw_cnt)
{ struct nand_chip *chip = &host->chip; struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); int i;
qcom_nandc_dev_to_mem(nandc, true);
for (i = 0; i < cw_cnt; i++) {
u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
if (flash & (FS_OP_ERR | FS_MPU_ERR)) return -EIO;
}
return 0;
}
/* performs raw read for one codeword */ staticint
qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
u8 *data_buf, u8 *oob_buf, int page, int cw)
{ struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; int data_size1, data_size2, oob_size1, oob_size2; int ret, reg_off = FLASH_BUF_ACC, read_loc = 0; int raw_cw = cw;
ret = qcom_submit_descs(nandc); if (ret) {
dev_err(nandc->dev, "failure to read raw cw %d\n", cw); return ret;
}
return check_flash_errors(host, 1);
}
/* * Bitflips can happen in erased codewords also so this function counts the * number of 0 in each CW for which ECC engine returns the uncorrectable * error. The page will be assumed as erased if this count is less than or * equal to the ecc->strength for each CW. * * 1. Both DATA and OOB need to be checked for number of 0. The * top-level API can be called with only data buf or OOB buf so use * chip->data_buf if data buf is null and chip->oob_poi if oob buf * is null for copying the raw bytes. * 2. Perform raw read for all the CW which has uncorrectable errors. * 3. For each CW, check the number of 0 in cw_data and usable OOB bytes. * The BBM and spare bytes bit flip won’t affect the ECC so don’t check * the number of bitflips in this area.
*/ staticint
check_for_erased_page(struct qcom_nand_host *host, u8 *data_buf,
u8 *oob_buf, unsignedlong uncorrectable_cws, int page, unsignedint max_bitflips)
{ struct nand_chip *chip = &host->chip; struct mtd_info *mtd = nand_to_mtd(chip); struct nand_ecc_ctrl *ecc = &chip->ecc;
u8 *cw_data_buf, *cw_oob_buf; int cw, data_size, oob_size, ret;
if (!data_buf)
data_buf = nand_get_data_buf(chip);
if (!oob_buf) {
nand_get_data_buf(chip);
oob_buf = chip->oob_poi;
}
ret = qcom_nandc_read_cw_raw(mtd, chip, cw_data_buf,
cw_oob_buf, page, cw); if (ret) return ret;
/* * make sure it isn't an erased page reported * as not-erased by HW because of a few bitflips
*/
ret = nand_check_erased_ecc_chunk(cw_data_buf, data_size,
cw_oob_buf + host->bbm_size,
oob_size, NULL,
0, ecc->strength); if (ret < 0) {
mtd->ecc_stats.failed++;
} else {
mtd->ecc_stats.corrected += ret;
max_bitflips = max_t(unsignedint, max_bitflips, ret);
}
}
return max_bitflips;
}
/* * reads back status registers set by the controller to notify page read * errors. this is equivalent to what 'ecc->correct()' would do.
*/ staticint parse_read_errors(struct qcom_nand_host *host, u8 *data_buf,
u8 *oob_buf, int page)
{ struct nand_chip *chip = &host->chip; struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct mtd_info *mtd = nand_to_mtd(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; unsignedint max_bitflips = 0, uncorrectable_cws = 0; struct read_stats *buf; bool flash_op_err = false, erased; int i;
u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
/* * Check ECC failure for each codeword. ECC failure can * happen in either of the following conditions * 1. If number of bitflips are greater than ECC engine * capability. * 2. If this codeword contains all 0xff for which erased * codeword detection check will be done.
*/ if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) { /* * For BCH ECC, ignore erased codeword errors, if * ERASED_CW bits are set.
*/ if (host->bch_enabled) {
erased = (erased_cw & ERASED_CW) == ERASED_CW; /* * For RS ECC, HW reports the erased CW by placing * special characters at certain offsets in the buffer. * These special characters will be valid only if * complete page is read i.e. data_buf is not NULL.
*/
} elseif (data_buf) {
erased = erased_chunk_check_and_fixup(data_buf,
data_len);
} else {
erased = false;
}
if (!erased)
uncorrectable_cws |= BIT(i); /* * Check if MPU or any other operational error (timeout, * device failure, etc.) happened for this codeword and * make flash_op_err true. If flash_op_err is set, then * EIO will be returned for page read.
*/
} elseif (flash & (FS_OP_ERR | FS_MPU_ERR)) {
flash_op_err = true; /* * No ECC or operational errors happened. Check the number of * bits corrected and update the ecc_stats.corrected.
*/
} else { unsignedint stat;
if (nandc->props->supports_bam) { if (data_buf && oob_buf) {
nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
nandc_set_read_loc(chip, i, 1, data_size,
oob_size, 1);
} elseif (data_buf) {
nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
} else {
nandc_set_read_loc(chip, i, 0, data_size,
oob_size, 1);
}
}
config_nand_cw_read(chip, true, i);
if (data_buf)
qcom_read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
data_size, 0);
/* * when ecc is enabled, the controller doesn't read the real * or dummy bad block markers in each chunk. To maintain a * consistent layout across RAW and ECC reads, we just * leave the real/dummy BBM offsets empty (i.e, filled with * 0xffs)
*/ if (oob_buf) { int j;
/* * a helper that copies the last step/codeword of a page (containing free oob) * into our local buffer
*/ staticint copy_last_cw(struct qcom_nand_host *host, int page)
{ struct nand_chip *chip = &host->chip; struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct nand_ecc_ctrl *ecc = &chip->ecc; int size; int ret;
ret = qcom_submit_descs(nandc); if (ret)
dev_err(nandc->dev, "failed to copy last codeword\n");
return ret;
}
staticbool qcom_nandc_is_boot_partition(struct qcom_nand_host *host, int page)
{ struct qcom_nand_boot_partition *boot_partition;
u32 start, end; int i;
/* * Since the frequent access will be to the non-boot partitions like rootfs, * optimize the page check by: * * 1. Checking if the page lies after the last boot partition. * 2. Checking from the boot partition end.
*/
/* First check the last boot partition */
boot_partition = &host->boot_partitions[host->nr_boot_partitions - 1];
start = boot_partition->page_offset;
end = start + boot_partition->page_size;
/* Page is after the last boot partition end. This is NOT a boot partition */ if (page > end) returnfalse;
/* Actually check if it's a boot partition */ if (page < end && page >= start) returntrue;
/* Check the other boot partitions starting from the second-last partition */ for (i = host->nr_boot_partitions - 2; i >= 0; i--) {
boot_partition = &host->boot_partitions[i];
start = boot_partition->page_offset;
end = start + boot_partition->page_size;
/* * when ECC is enabled, we don't really need to write anything * to oob for the first n - 1 codewords since these oob regions * just contain ECC bytes that's written by the controller * itself. For the last codeword, we skip the bbm positions and * write to the free oob area.
*/ if (qcom_nandc_is_last_cw(ecc, i)) {
oob_buf += host->bbm_size;
ret = qcom_submit_descs(nandc); if (ret) {
dev_err(nandc->dev, "failure to write raw page\n"); return ret;
}
return nand_prog_page_end_op(chip);
}
/* * implements ecc->write_oob() * * the NAND controller cannot write only data or only OOB within a codeword * since ECC is calculated for the combined codeword. So update the OOB from * chip->oob_poi, and pad the data area with OxFF before writing.
*/ staticint qcom_nandc_write_oob(struct nand_chip *chip, int page)
{ struct mtd_info *mtd = nand_to_mtd(chip); struct qcom_nand_host *host = to_qcom_nand_host(chip); struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); struct nand_ecc_ctrl *ecc = &chip->ecc;
u8 *oob = chip->oob_poi; int data_size, oob_size; int ret;
if (host->nr_boot_partitions)
qcom_nandc_codeword_fixup(host, page);
/* * configure registers for a raw sub page read, the address is set to * the beginning of the last codeword, we don't care about reading ecc * portion of oob. we just want the first few bytes from this codeword * that contains the BBM
*/
host->use_ecc = false;
qcom_clear_bam_transaction(nandc);
ret = copy_last_cw(host, page); if (ret) goto err;
if (check_flash_errors(host, 1)) {
dev_warn(nandc->dev, "error when trying to read BBM\n"); goto err;
}
/* * to mark the BBM as bad, we flash the entire last codeword with 0s. * we don't care about the rest of the content in the codeword since * we aren't going to use this block again
*/
memset(nandc->data_buffer, 0x00, host->cw_size);
ret = qcom_submit_descs(nandc); if (ret) {
dev_err(nandc->dev, "failure to update BBM\n"); return ret;
}
return nand_prog_page_end_op(chip);
}
/* * NAND controller page layout info * * Layout with ECC enabled: * * |----------------------| |---------------------------------| * | xx.......yy| | *********xx.......yy| * | DATA xx..ECC..yy| | DATA **SPARE**xx..ECC..yy| * | (516) xx.......yy| | (516-n*4) **(n*4)**xx.......yy| * | xx.......yy| | *********xx.......yy| * |----------------------| |---------------------------------| * codeword 1,2..n-1 codeword n * <---(528/532 Bytes)--> <-------(528/532 Bytes)---------> * * n = Number of codewords in the page * . = ECC bytes * * = Spare/free bytes * x = Unused byte(s) * y = Reserved byte(s) * * 2K page: n = 4, spare = 16 bytes * 4K page: n = 8, spare = 32 bytes * 8K page: n = 16, spare = 64 bytes * * the qcom nand controller operates at a sub page/codeword level. each * codeword is 528 and 532 bytes for 4 bit and 8 bit ECC modes respectively. * the number of ECC bytes vary based on the ECC strength and the bus width. * * the first n - 1 codewords contains 516 bytes of user data, the remaining * 12/16 bytes consist of ECC and reserved data. The nth codeword contains * both user data and spare(oobavail) bytes that sum up to 516 bytes. * * When we access a page with ECC enabled, the reserved bytes(s) are not * accessible at all. When reading, we fill up these unreadable positions * with 0xffs. When writing, the controller skips writing the inaccessible * bytes. * * Layout with ECC disabled: * * |------------------------------| |---------------------------------------| * | yy xx.......| | bb *********xx.......| * | DATA1 yy DATA2 xx..ECC..| | DATA1 bb DATA2 **SPARE**xx..ECC..| * | (size1) yy (size2) xx.......| | (size1) bb (size2) **(n*4)**xx.......| * | yy xx.......| | bb *********xx.......| * |------------------------------| |---------------------------------------| * codeword 1,2..n-1 codeword n * <-------(528/532 Bytes)------> <-----------(528/532 Bytes)-----------> * * n = Number of codewords in the page * . = ECC bytes * * = Spare/free bytes * x = Unused byte(s) * y = Dummy Bad Bock byte(s) * b = Real Bad Block byte(s) * size1/size2 = function of codeword size and 'n' * * when the ECC block is disabled, one reserved byte (or two for 16 bit bus * width) is now accessible. For the first n - 1 codewords, these are dummy Bad * Block Markers. In the last codeword, this position contains the real BBM * * In order to have a consistent layout between RAW and ECC modes, we assume * the following OOB layout arrangement: * * |-----------| |--------------------| * |yyxx.......| |bb*********xx.......| * |yyxx..ECC..| |bb*FREEOOB*xx..ECC..| * |yyxx.......| |bb*********xx.......| * |yyxx.......| |bb*********xx.......| * |-----------| |--------------------| * first n - 1 nth OOB region * OOB regions * * n = Number of codewords in the page * . = ECC bytes * * = FREE OOB bytes * y = Dummy bad block byte(s) (inaccessible when ECC enabled) * x = Unused byte(s) * b = Real bad block byte(s) (inaccessible when ECC enabled) * * This layout is read as is when ECC is disabled. When ECC is enabled, the * inaccessible Bad Block byte(s) are ignored when we write to a page/oob, * and assumed as 0xffs when we read a page/oob. The ECC, unused and * dummy/real bad block bytes are grouped as ecc bytes (i.e, ecc->bytes is * the sum of the three).
*/ staticint qcom_nand_ooblayout_ecc(struct mtd_info *mtd, int section, struct mtd_oob_region *oobregion)
{ struct nand_chip *chip = mtd_to_nand(mtd); struct qcom_nand_host *host = to_qcom_nand_host(chip); struct nand_ecc_ctrl *ecc = &chip->ecc;
/* * Each CW has 4 available OOB bytes which will be protected with ECC * so remaining bytes can be used for ECC.
*/
ret = nand_ecc_choose_conf(chip, &qcom_nandc_ecc_caps,
mtd->oobsize - (cwperpage * 4)); if (ret) {
dev_err(nandc->dev, "No valid ECC settings possible\n"); return ret;
}
if (ecc->strength >= 8) { /* 8 bit ECC defaults to BCH ECC on all platforms */
host->bch_enabled = true;
ecc_mode = ECC_MODE_8BIT;
if (wide_bus) {
host->ecc_bytes_hw = 14;
host->spare_bytes = 0;
host->bbm_size = 2;
} else {
host->ecc_bytes_hw = 13;
host->spare_bytes = 2;
host->bbm_size = 1;
}
} else { /* * if the controller supports BCH for 4 bit ECC, the controller * uses lesser bytes for ECC. If RS is used, the ECC bytes is * always 10 bytes
*/ if (nandc->props->ecc_modes & ECC_BCH_4BIT) { /* BCH */
host->bch_enabled = true;
ecc_mode = ECC_MODE_4BIT;
/* * we consider ecc->bytes as the sum of all the non-data content in a * step. It gives us a clean representation of the oob area (even if * all the bytes aren't used for ECC).It is always 16 bytes for 8 bit * ECC and 12 bytes for 4 bit ECC
*/
ecc->bytes = host->ecc_bytes_hw + host->spare_bytes + host->bbm_size;
mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops); /* Free the initially allocated BAM transaction for reading the ONFI params */ if (nandc->props->supports_bam)
qcom_free_bam_transaction(nandc);
/* Now allocate the BAM transaction based on updated max_cwperpage */ if (nandc->props->supports_bam) {
nandc->bam_txn = qcom_alloc_bam_transaction(nandc); if (!nandc->bam_txn) {
dev_err(nandc->dev, "failed to allocate bam transaction\n"); return -ENOMEM;
}
}
/* * DATA_UD_BYTES varies based on whether the read/write command protects * spare data with ECC too. We protect spare data by default, so we set * it to main + spare data, which are 512 and 4 bytes respectively.
*/
host->cw_data = 516;
/* * total bytes in a step, either 528 bytes for 4 bit ECC, or 532 bytes * for 8 bit ECC
*/
host->cw_size = host->cw_data + ecc->bytes;
bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
/* kill onenand */ if (!nandc->props->nandc_part_of_qpic)
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
if (!nandc->props->qpic_version2)
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
NAND_DEV_CMD_VLD_VAL);
/* enable ADM or BAM DMA */ if (nandc->props->supports_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
/* *NAND_CTRL is an operational registers, and CPU * access to operational registers are read only * in BAM mode. So update the NAND_CTRL register * only if it is not in BAM mode. In most cases BAM * mode will be enabled in bootloader
*/ if (!(nand_ctrl & BAM_MODE_EN))
nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
/* save the original values of these registers */ if (!nandc->props->qpic_version2) {
nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1));
nandc->vld = NAND_DEV_CMD_VLD_VAL;
}
/* * the bad block marker is readable only when we read the last codeword * of a page with ECC disabled. currently, the nand_base and nand_bbt * helpers don't allow us to read BB from a nand chip with ECC * disabled (MTD_OPS_PLACE_OOB is set by default). use the block_bad * and block_markbad helpers until we permanently switch to using * MTD_OPS_RAW for all drivers (with the help of badblockbits)
*/
chip->legacy.block_bad = qcom_nandc_block_bad;
chip->legacy.block_markbad = qcom_nandc_block_markbad;
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