/** * hclge_cmd_send - send command to command queue * @hw: pointer to the hw struct * @desc: prefilled descriptor for describing the command * @num : the number of descriptors to be sent * * This is the main send command for command queue, it * sends the queue, cleans the queue, etc
**/ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
{ return hclge_comm_cmd_send(&hw->hw, desc, num);
}
staticvoid hclge_trace_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc, int num, bool is_special)
{ int i;
trace_hclge_pf_cmd_send(hw, desc, 0, num);
if (!is_special) { for (i = 1; i < num; i++)
trace_hclge_pf_cmd_send(hw, &desc[i], i, num);
} else { for (i = 1; i < num; i++)
trace_hclge_pf_special_cmd_send(hw, (__le32 *)&desc[i],
i, num);
}
}
staticvoid hclge_trace_cmd_get(struct hclge_comm_hw *hw, struct hclge_desc *desc, int num, bool is_special)
{ int i;
if (!HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) return;
trace_hclge_pf_cmd_get(hw, desc, 0, num);
if (!is_special) { for (i = 1; i < num; i++)
trace_hclge_pf_cmd_get(hw, &desc[i], i, num);
} else { for (i = 1; i < num; i++)
trace_hclge_pf_special_cmd_get(hw, (__le32 *)&desc[i],
i, num);
}
}
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); if (ret) {
dev_err(&hdev->pdev->dev, "Get MAC pkt stats fail, status = %d.\n", ret);
return ret;
}
/* The first desc has a 64-bit header, so data size need to minus 1 */
data_size = sizeof(desc) / (sizeof(u64)) - 1;
desc_data = (__le64 *)(&desc[0].data[0]); for (i = 0; i < data_size; i++) { /* data memory is continuous becase only the first desc has a * header in this command
*/
*data += le64_to_cpu(*desc_data);
data++;
desc_data++;
}
/* The first desc has a 64-bit header, so need to consider it */
desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1;
/* This may be called inside atomic sections, * so GFP_ATOMIC is more suitable here
*/
desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC); if (!desc) return -ENOMEM;
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC_ALL, true);
ret = hclge_cmd_send(&hdev->hw, desc, desc_num); if (ret) {
kfree(desc); return ret;
}
desc_data = (__le64 *)(&desc[0].data[0]); for (i = 0; i < data_size; i++) { /* data memory is continuous becase only the first desc has a * header in this command
*/
*data += le64_to_cpu(*desc_data);
data++;
desc_data++;
}
/* Driver needs total register number of both valid registers and * reserved registers, but the old firmware only returns number * of valid registers in device V2. To be compatible with these * devices, driver uses a fixed value.
*/ if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
*reg_num = HCLGE_MAC_STATS_MAX_NUM_V1; return 0;
}
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1); if (ret) {
dev_err(&hdev->pdev->dev, "failed to query mac statistic reg number, ret = %d\n",
ret); return ret;
}
*reg_num = le32_to_cpu(desc.data[0]); if (*reg_num == 0) {
dev_err(&hdev->pdev->dev, "mac statistic reg number is invalid!\n"); return -ENODATA;
}
return 0;
}
int hclge_mac_update_stats(struct hclge_dev *hdev)
{ /* The firmware supports the new statistics acquisition method */ if (hdev->ae_dev->dev_specs.mac_stats_num) return hclge_mac_update_stats_complete(hdev); else return hclge_mac_update_stats_defective(hdev);
}
/* Loopback test support rules: * mac: only GE mode support * serdes: all mac mode will support include GE/XGE/LGE/CGE * phy: only support when phy device exist on board
*/ if (stringset == ETH_SS_TEST) { /* clear loopback bit flags at first */
handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 ||
hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
count += 1;
handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
}
hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic); if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
dev_err(&hdev->pdev->dev, "only %u msi resources available, not enough for pf(min:2).\n",
hdev->num_nic_msi); return -EINVAL;
}
if (hnae3_dev_roce_supported(hdev)) {
hdev->num_roce_msi =
le16_to_cpu(req->pf_intr_vector_number_roce);
/* PF should have NIC vectors and Roce vectors, * NIC vectors are queued before Roce vectors.
*/
hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi;
} else {
hdev->num_msi = hdev->num_nic_msi;
}
return 0;
}
staticint hclge_parse_speed(u8 speed_cmd, u32 *speed)
{ switch (speed_cmd) { case HCLGE_FW_MAC_SPEED_10M:
*speed = HCLGE_MAC_SPEED_10M; break; case HCLGE_FW_MAC_SPEED_100M:
*speed = HCLGE_MAC_SPEED_100M; break; case HCLGE_FW_MAC_SPEED_1G:
*speed = HCLGE_MAC_SPEED_1G; break; case HCLGE_FW_MAC_SPEED_10G:
*speed = HCLGE_MAC_SPEED_10G; break; case HCLGE_FW_MAC_SPEED_25G:
*speed = HCLGE_MAC_SPEED_25G; break; case HCLGE_FW_MAC_SPEED_40G:
*speed = HCLGE_MAC_SPEED_40G; break; case HCLGE_FW_MAC_SPEED_50G:
*speed = HCLGE_MAC_SPEED_50G; break; case HCLGE_FW_MAC_SPEED_100G:
*speed = HCLGE_MAC_SPEED_100G; break; case HCLGE_FW_MAC_SPEED_200G:
*speed = HCLGE_MAC_SPEED_200G; break; default: return -EINVAL;
}
staticvoid hclge_convert_setting_sr(u16 speed_ability, unsignedlong *link_mode)
{ int i;
for (i = 0; i < ARRAY_SIZE(hclge_sr_link_mode_bmap); i++) { if (speed_ability & hclge_sr_link_mode_bmap[i].support_bit)
linkmode_set_bit(hclge_sr_link_mode_bmap[i].link_mode,
link_mode);
}
}
staticvoid hclge_convert_setting_lr(u16 speed_ability, unsignedlong *link_mode)
{ int i;
for (i = 0; i < ARRAY_SIZE(hclge_lr_link_mode_bmap); i++) { if (speed_ability & hclge_lr_link_mode_bmap[i].support_bit)
linkmode_set_bit(hclge_lr_link_mode_bmap[i].link_mode,
link_mode);
}
}
staticvoid hclge_convert_setting_cr(u16 speed_ability, unsignedlong *link_mode)
{ int i;
for (i = 0; i < ARRAY_SIZE(hclge_cr_link_mode_bmap); i++) { if (speed_ability & hclge_cr_link_mode_bmap[i].support_bit)
linkmode_set_bit(hclge_cr_link_mode_bmap[i].link_mode,
link_mode);
}
}
staticvoid hclge_convert_setting_kr(u16 speed_ability, unsignedlong *link_mode)
{ int i;
for (i = 0; i < ARRAY_SIZE(hclge_kr_link_mode_bmap); i++) { if (speed_ability & hclge_kr_link_mode_bmap[i].support_bit)
linkmode_set_bit(hclge_kr_link_mode_bmap[i].link_mode,
link_mode);
}
}
staticvoid hclge_convert_setting_fec(struct hclge_mac *mac)
{ /* If firmware has reported fec_ability, don't need to convert by speed */ if (mac->fec_ability) goto out;
switch (mac->speed) { case HCLGE_MAC_SPEED_10G: case HCLGE_MAC_SPEED_40G:
mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) |
BIT(HNAE3_FEC_NONE); break; case HCLGE_MAC_SPEED_25G: case HCLGE_MAC_SPEED_50G:
mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE); break; case HCLGE_MAC_SPEED_100G:
mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
BIT(HNAE3_FEC_NONE); break; case HCLGE_MAC_SPEED_200G:
mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
BIT(HNAE3_FEC_LLRS); break; default:
mac->fec_ability = 0; break;
}
/* HCLGE_CFG_PF_RSS_SIZE_M is the PF max rss size, which is a * power of 2, instead of reading out directly. This would * be more flexible for future changes and expansions. * When VF max rss size field is HCLGE_CFG_RSS_SIZE_S, * it does not make sense if PF's field is 0. In this case, PF and VF * has the same max rss size filed: HCLGE_CFG_RSS_SIZE_S.
*/
cfg->pf_rss_size_max = cfg->pf_rss_size_max ?
1U << cfg->pf_rss_size_max :
cfg->vf_rss_size_max;
/* The unit of the tx spare buffer size queried from configuration * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is * needed here.
*/
cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]),
HCLGE_CFG_TX_SPARE_BUF_SIZE_M,
HCLGE_CFG_TX_SPARE_BUF_SIZE_S);
cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT;
}
/* hclge_get_cfg: query the static parameter from flash * @hdev: pointer to struct hclge_dev * @hcfg: the config structure to be getted
*/ staticint hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
{ struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; struct hclge_cfg_param_cmd *req; unsignedint i; int ret;
for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
u32 offset = 0;
req = (struct hclge_cfg_param_cmd *)desc[i].data;
hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, true);
hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); /* Len should be united by 4 bytes when send to hardware */
hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
req->offset = cpu_to_le32(offset);
}
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); if (ret) {
dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret); return ret;
}
staticint hclge_query_dev_specs(struct hclge_dev *hdev)
{ struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM]; int ret; int i;
ret = hclge_query_mac_stats_num(hdev); if (ret) return ret;
/* set default specifications as devices lower than version V3 do not * support querying specifications from firmware.
*/ if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
hclge_set_default_dev_specs(hdev); return 0;
}
for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
}
hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM); if (ret) return ret;
/* need an extended offset to configure queues >= * HCLGE_TQP_MAX_SIZE_DEV_V2
*/ if (i < HCLGE_TQP_MAX_SIZE_DEV_V2)
tqp->q.io_base = hdev->hw.hw.io_base +
HCLGE_TQP_REG_OFFSET +
i * HCLGE_TQP_REG_SIZE; else
tqp->q.io_base = hdev->hw.hw.io_base +
HCLGE_TQP_REG_OFFSET +
HCLGE_TQP_EXT_REG_OFFSET +
(i - HCLGE_TQP_MAX_SIZE_DEV_V2) *
HCLGE_TQP_REG_SIZE;
/* when device supports tx push and has device memory, * the queue can execute push mode or doorbell mode on * device memory.
*/ if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
tqp->q.mem_base = hdev->hw.hw.mem_base +
HCLGE_TQP_MEM_OFFSET(hdev, i);
/* ensure one to one mapping between irq and queue at default */
kinfo->rss_size = min_t(u16, kinfo->rss_size,
(hdev->num_nic_msi - 1) / hdev->tm_info.num_tc);
/* We need to alloc a vport for main NIC of PF */
num_vport = hdev->num_req_vfs + 1;
if (hdev->num_tqps < num_vport) {
dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)",
hdev->num_tqps, num_vport); return -EINVAL;
}
/* Alloc the same number of TQPs for every vport */
tqp_per_vport = hdev->num_tqps / num_vport;
tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
if (i == 0)
ret = hclge_vport_setup(vport, tqp_main_vport); else
ret = hclge_vport_setup(vport, tqp_per_vport); if (ret) {
dev_err(&pdev->dev, "vport setup failed for vport %d, %d\n",
i, ret); return ret;
}
vport++;
}
return 0;
}
staticint hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, struct hclge_pkt_buf_alloc *buf_alloc)
{ /* TX buffer size is unit by 128 byte */ #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) struct hclge_tx_buff_alloc_cmd *req; struct hclge_desc desc; int ret;
u8 i;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) if (hdev->hw_tc_map & BIT(i))
cnt++; return cnt;
}
/* Get the number of pfc enabled TCs, which have private buffer */ staticint hclge_get_pfc_priv_num(struct hclge_dev *hdev, struct hclge_pkt_buf_alloc *buf_alloc)
{ struct hclge_priv_buf *priv; unsignedint i; int cnt = 0;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
priv = &buf_alloc->priv_buf[i]; if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
priv->enable)
cnt++;
}
return cnt;
}
/* Get the number of pfc disabled TCs, which have private buffer */ staticint hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, struct hclge_pkt_buf_alloc *buf_alloc)
{ struct hclge_priv_buf *priv; unsignedint i; int cnt = 0;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
priv = &buf_alloc->priv_buf[i]; if (hdev->hw_tc_map & BIT(i) &&
!(hdev->tm_info.hw_pfc_map & BIT(i)) &&
priv->enable)
cnt++;
}
/* let the last to be cleared first */ for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; unsignedint mask = BIT((unsignedint)i);
/* let the last to be cleared first */ for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; unsignedint mask = BIT((unsignedint)i);
if (hdev->hw_tc_map & mask &&
hdev->tm_info.hw_pfc_map & mask) { /* Reduce the number of pfc TC with private buffer */
priv->wl.low = 0;
priv->enable = 0;
priv->wl.high = 0;
priv->buf_size = 0;
pfc_priv_num--;
}
if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
pfc_priv_num == 0) break;
}
/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs * @hdev: pointer to struct hclge_dev * @buf_alloc: pointer to buffer calculation data * @return: 0: calculate successful, negative: fail
*/ staticint hclge_rx_buffer_calc(struct hclge_dev *hdev, struct hclge_pkt_buf_alloc *buf_alloc)
{ /* When DCB is not supported, rx private buffer is not allocated. */ if (!hnae3_dev_dcb_supported(hdev)) {
u32 rx_all = hdev->pkt_buf_size;
rx_all -= hclge_get_tx_buff_alloced(buf_alloc); if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) return -ENOMEM;
return 0;
}
if (hclge_only_alloc_priv_buff(hdev, buf_alloc)) return 0;
if (hclge_rx_buf_calc_all(hdev, true, buf_alloc)) return 0;
/* try to decrease the buffer size */ if (hclge_rx_buf_calc_all(hdev, false, buf_alloc)) return 0;
if (hclge_drop_nopfc_buf_till_fit(hdev, buf_alloc)) return 0;
if (hclge_drop_pfc_buf_till_fit(hdev, buf_alloc)) return 0;
return -ENOMEM;
}
staticint hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, struct hclge_pkt_buf_alloc *buf_alloc)
{ struct hclge_rx_priv_buff_cmd *req; struct hclge_desc desc; int ret; int i;
ret = hclge_cmd_send(&hdev->hw, &desc, 1); if (ret)
dev_err(&hdev->pdev->dev, "rx private buffer alloc cmd failed %d\n", ret);
return ret;
}
staticint hclge_rx_priv_wl_config(struct hclge_dev *hdev, struct hclge_pkt_buf_alloc *buf_alloc)
{ struct hclge_rx_priv_wl_buf *req; struct hclge_priv_buf *priv; struct hclge_desc desc[2]; int i, j; int ret;
for (i = 0; i < 2; i++) {
hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, false);
req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
/* The first descriptor set the NEXT bit to 1 */ if (i == 0)
desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); else
desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
/* Send 2 descriptor at one time */
ret = hclge_cmd_send(&hdev->hw, desc, 2); if (ret)
dev_err(&hdev->pdev->dev, "rx private waterline config cmd failed %d\n",
ret); return ret;
}
staticint hclge_common_thrd_config(struct hclge_dev *hdev, struct hclge_pkt_buf_alloc *buf_alloc)
{ struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; struct hclge_rx_com_thrd *req; struct hclge_desc desc[2]; struct hclge_tc_thrd *tc; int i, j; int ret;
for (i = 0; i < 2; i++) {
hclge_cmd_setup_basic_desc(&desc[i],
HCLGE_OPC_RX_COM_THRD_ALLOC, false);
req = (struct hclge_rx_com_thrd *)desc[i].data;
/* The first descriptor set the NEXT bit to 1 */ if (i == 0)
desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT); else
desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
ret = hclge_cmd_send(&hdev->hw, &desc, 1); if (ret)
dev_err(&hdev->pdev->dev, "common waterline config cmd failed %d\n", ret);
return ret;
}
int hclge_buffer_alloc(struct hclge_dev *hdev)
{ struct hclge_pkt_buf_alloc *pkt_buf; int ret;
pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); if (!pkt_buf) return -ENOMEM;
ret = hclge_tx_buffer_calc(hdev, pkt_buf); if (ret) {
dev_err(&hdev->pdev->dev, "could not calc tx buffer size for all TCs %d\n", ret); goto out;
}
ret = hclge_tx_buffer_alloc(hdev, pkt_buf); if (ret) {
dev_err(&hdev->pdev->dev, "could not alloc tx buffers %d\n", ret); goto out;
}
ret = hclge_rx_buffer_calc(hdev, pkt_buf); if (ret) {
dev_err(&hdev->pdev->dev, "could not calc rx priv buffer size for all TCs %d\n",
ret); goto out;
}
ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); if (ret) {
dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
ret); goto out;
}
if (hnae3_dev_dcb_supported(hdev)) {
ret = hclge_rx_priv_wl_config(hdev, pkt_buf); if (ret) {
dev_err(&hdev->pdev->dev, "could not configure rx private waterline %d\n",
ret); goto out;
}
ret = hclge_common_thrd_config(hdev, pkt_buf); if (ret) {
dev_err(&hdev->pdev->dev, "could not configure common threshold %d\n",
ret); goto out;
}
}
ret = hclge_common_wl_config(hdev, pkt_buf); if (ret)
dev_err(&hdev->pdev->dev, "could not configure common waterline %d\n", ret);
if (!hdev->hw.mac.support_autoneg) { if (enable) {
dev_err(&hdev->pdev->dev, "autoneg is not supported by current port\n"); return -EOPNOTSUPP;
} else { return 0;
}
}
for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) {
hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS, true); if (i != (HCLGE_FEC_STATS_CMD_NUM - 1))
desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
}
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM); if (ret) return ret;
switch (fec_mode) { case BIT(HNAE3_FEC_RS): case BIT(HNAE3_FEC_LLRS):
hclge_get_fec_stats_total(hdev, fec_stats); break; case BIT(HNAE3_FEC_BASER):
hclge_get_fec_stats_lanes(hdev, fec_stats); break; default:
dev_err(&hdev->pdev->dev, "fec stats is not supported by current fec mode(0x%x)\n",
fec_mode); break;
}
}
if (!test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
hdev->hw.mac.duplex = HCLGE_MAC_FULL;
if (hdev->hw.mac.support_autoneg) {
ret = hclge_set_autoneg_en(hdev, hdev->hw.mac.autoneg); if (ret) return ret;
}
if (!hdev->hw.mac.autoneg) {
ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.req_speed,
hdev->hw.mac.req_duplex,
hdev->hw.mac.lane_num); if (ret) return ret;
}
mac->link = 0;
if (mac->user_fec_mode & BIT(HNAE3_FEC_USER_DEF)) {
ret = hclge_set_fec_hw(hdev, mac->user_fec_mode); if (ret) return ret;
}
ret = hclge_set_mac_mtu(hdev, hdev->mps); if (ret) {
dev_err(&hdev->pdev->dev, "set mtu failed ret=%d\n", ret); return ret;
}
ret = hclge_set_default_loopback(hdev); if (ret) return ret;
ret = hclge_buffer_alloc(hdev); if (ret)
dev_err(&hdev->pdev->dev, "allocate buffer fail, ret=%d\n", ret);
/* firmware can not identify back plane type, the media type * read from configuration can help deal it
*/ if (mac->media_type == HNAE3_MEDIA_TYPE_BACKPLANE &&
mac->module_type == HNAE3_MODULE_TYPE_UNKNOWN)
mac->module_type = HNAE3_MODULE_TYPE_KR; elseif (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
mac->module_type = HNAE3_MODULE_TYPE_TP;
ret = hclge_cmd_send(&hdev->hw, &desc, 1); if (ret == -EOPNOTSUPP) {
dev_warn(&hdev->pdev->dev, "IMP does not support get SFP info %d\n", ret); return ret;
} elseif (ret) {
dev_err(&hdev->pdev->dev, "get sfp info failed %d\n", ret); return ret;
}
/* In some case, mac speed get from IMP may be 0, it shouldn't be * set to mac->speed.
*/ if (!le32_to_cpu(resp->speed)) return 0;
mac->speed = le32_to_cpu(resp->speed); /* if resp->speed_ability is 0, it means it's an old version * firmware, do not update these params
*/ if (resp->speed_ability) {
mac->module_type = le32_to_cpu(resp->module_type);
mac->speed_ability = le32_to_cpu(resp->speed_ability);
mac->autoneg = resp->autoneg;
mac->support_autoneg = resp->autoneg_ability;
mac->speed_type = QUERY_ACTIVE_SPEED;
mac->lane_num = resp->lane_num; if (!resp->active_fec)
mac->fec_mode = 0; else
mac->fec_mode = BIT(resp->active_fec);
mac->fec_ability = resp->fec_ability;
} else {
mac->speed_type = QUERY_SFP_SPEED;
}
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); if (ret) {
dev_err(&hdev->pdev->dev, "failed to get phy link ksetting, ret = %d.\n", ret); return ret;
}
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM); if (ret) {
dev_err(&hdev->pdev->dev, "failed to set phy link ksettings, ret = %d.\n", ret); return ret;
}
struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf)
{ if (!pci_num_vf(hdev->pdev)) {
dev_err(&hdev->pdev->dev, "SRIOV is disabled, can not get vport(%d) info.\n", vf); return NULL;
}
if (vf < 0 || vf >= pci_num_vf(hdev->pdev)) {
dev_err(&hdev->pdev->dev, "vf id(%d) is out of range(0 <= vfid < %d)\n",
vf, pci_num_vf(hdev->pdev)); return NULL;
}
/* VF start from 1 in vport */
vf += HCLGE_VF_VPORT_START_NUM; return &hdev->vport[vf];
}
/* return success directly if the VF is unalive, VF will * query link state itself when it starts work.
*/ if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) return 0;
ret = hclge_push_vf_link_status(vport); if (ret) {
vport->vf_info.link_state = link_state_old;
dev_err(&hdev->pdev->dev, "failed to push vf%d link status, ret = %d\n", vf, ret);
}
return ret;
}
staticvoid hclge_set_reset_pending(struct hclge_dev *hdev, enum hnae3_reset_type reset_type)
{ /* When an incorrect reset type is executed, the get_reset_level * function generates the HNAE3_NONE_RESET flag. As a result, this * type do not need to pending.
*/ if (reset_type != HNAE3_NONE_RESET)
set_bit(reset_type, &hdev->reset_pending);
}
/* fetch the events from their corresponding regs */
cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
hw_err_src_reg = hclge_read_dev(&hdev->hw,
HCLGE_RAS_PF_OTHER_INT_STS_REG);
/* Assumption: If by any chance reset and mailbox events are reported * together then we will only process reset event in this go and will * defer the processing of the mailbox events. Since, we would have not * cleared RX CMDQ event this time we would receive again another * interrupt from H/W just for the mailbox. * * check for vector0 reset event sources
*/ if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
hclge_set_reset_pending(hdev, HNAE3_IMP_RESET);
set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
*clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
hdev->rst_stats.imp_rst_cnt++; return HCLGE_VECTOR0_EVENT_RST;
}
switch (event_type) { case HCLGE_VECTOR0_EVENT_PTP: case HCLGE_VECTOR0_EVENT_RST: if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))
mdelay(HCLGE_IMP_RESET_DELAY);
/* vector 0 interrupt is shared with reset and mailbox source events. */ switch (event_cause) { case HCLGE_VECTOR0_EVENT_ERR:
hclge_errhand_task_schedule(hdev); break; case HCLGE_VECTOR0_EVENT_RST:
hclge_reset_task_schedule(hdev); break; case HCLGE_VECTOR0_EVENT_PTP:
spin_lock_irqsave(&hdev->ptp->lock, flags);
hclge_ptp_clean_tx_hwts(hdev);
spin_unlock_irqrestore(&hdev->ptp->lock, flags); break; case HCLGE_VECTOR0_EVENT_MBX: /* If we are here then, * 1. Either we are not handling any mbx task and we are not * scheduled as well * OR * 2. We could be handling a mbx task but nothing more is * scheduled. * In both cases, we should schedule mbx task as there are more * mbx messages reported by this interrupt.
*/
hclge_mbx_task_schedule(hdev); break; default:
dev_warn(&hdev->pdev->dev, "received unknown or unhandled event of vector0\n"); break;
}
/* Enable interrupt if it is not caused by reset event or error event */ if (event_cause == HCLGE_VECTOR0_EVENT_PTP ||
event_cause == HCLGE_VECTOR0_EVENT_MBX ||
event_cause == HCLGE_VECTOR0_EVENT_OTHER)
hclge_enable_vector(&hdev->misc_vector, true);
return IRQ_HANDLED;
}
staticvoid hclge_free_vector(struct hclge_dev *hdev, int vector_id)
{ if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
dev_warn(&hdev->pdev->dev, "vector(vector_id %d) has been freed.\n", vector_id); return;
}
staticint hclge_misc_irq_init(struct hclge_dev *hdev)
{ int ret;
hclge_get_misc_vector(hdev);
/* this would be explicitly freed in the end */
snprintf(hdev->misc_vector.name, HNAE3_INT_NAME_LEN, "%s-misc-%s",
HCLGE_NAME, pci_name(hdev->pdev));
ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
IRQF_NO_AUTOEN, hdev->misc_vector.name, hdev); if (ret) {
hclge_free_vector(hdev, 0);
dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
hdev->misc_vector.vector_irq);
}
/* Inform VF to process the reset. * hclge_inform_reset_assert_to_vf may fail if VF * driver is not loaded.
*/
ret = hclge_inform_reset_assert_to_vf(vport); if (ret)
dev_warn(&hdev->pdev->dev, "inform reset to vf(%u) failed %d!\n",
vport->vport_id - HCLGE_VF_VPORT_START_NUM,
ret);
}
if (time_is_before_jiffies(hdev->last_mbx_scheduled +
HCLGE_MBX_SCHED_TIMEOUT))
dev_warn(&hdev->pdev->dev, "mbx service task is scheduled after %ums on cpu%u!\n",
jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled),
smp_processor_id());
do { /* vf need to down netdev by mbx during PF or FLR reset */
hclge_mailbox_service_task(hdev);
ret = hclge_cmd_send(&hdev->hw, &desc, 1); /* for compatible with old firmware, wait * 100 ms for VF to stop IO
*/ if (ret == -EOPNOTSUPP) {
msleep(HCLGE_RESET_SYNC_TIME); return;
} elseif (ret) {
dev_warn(&hdev->pdev->dev, "sync with VF fail %d!\n",
ret);
return;
} else if (req->all_vf_ready) {
return;
}
msleep(HCLGE_PF_RESET_SYNC_TIME);
hclge_comm_cmd_reuse_desc(&desc, true);
} while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n");
}
switch (hdev->reset_type) {
case HNAE3_IMP_RESET:
clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
break;
case HNAE3_GLOBAL_RESET:
clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
break;
default:
break;
}
if (!clearval)
return;
/* For revision 0x20, the reset interrupt source
* can only be cleared after hardware reset done
*/
if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG,
clearval);
static int hclge_func_reset_notify_vf(struct hclge_dev *hdev)
{
int ret;
ret = hclge_set_all_vf_rst(hdev, true);
if (ret)
return ret;
hclge_func_reset_sync_vf(hdev);
return 0;
}
static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
{
u32 reg_val;
int ret = 0;
switch (hdev->reset_type) {
case HNAE3_FUNC_RESET:
ret = hclge_func_reset_notify_vf(hdev);
if (ret)
return ret;
ret = hclge_func_reset_cmd(hdev, 0);
if (ret) {
dev_err(&hdev->pdev->dev,
"asserting function reset fail %d!\n", ret);
return ret;
}
/* After performaning pf reset, it is not necessary to do the
* mailbox handling or send any command to firmware, because
* any mailbox handling or command to firmware is only valid
* after hclge_comm_cmd_init is called.
*/
set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
hdev->rst_stats.pf_rst_cnt++;
break;
case HNAE3_FLR_RESET:
ret = hclge_func_reset_notify_vf(hdev);
if (ret)
return ret;
break;
case HNAE3_IMP_RESET:
hclge_handle_imp_error(hdev);
reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
break;
default:
break;
}
/* inform hardware that preparatory work is done */
msleep(HCLGE_RESET_SYNC_TIME);
hclge_reset_handshake(hdev, true);
dev_info(&hdev->pdev->dev, "prepare wait ok\n");
/* reset request will not be set during reset, so clear
* pending reset request to avoid unnecessary reset
* caused by the same reason.
*/
hclge_get_reset_level(ae_dev, &hdev->reset_request);
/* if default_reset_request has a higher level reset request,
* it should be handled as soon as possible. since some errors
* need this kind of reset to fix.
*/
reset_level = hclge_get_reset_level(ae_dev,
&hdev->default_reset_request);
if (reset_level != HNAE3_NONE_RESET)
set_bit(reset_level, &hdev->reset_request);
}
static int hclge_set_rst_done(struct hclge_dev *hdev)
{
struct hclge_pf_rst_done_cmd *req;
struct hclge_desc desc;
int ret;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
/* To be compatible with the old firmware, which does not support
* command HCLGE_OPC_PF_RST_DONE, just print a warning and
* return success
*/
if (ret == -EOPNOTSUPP) {
dev_warn(&hdev->pdev->dev,
"current firmware does not support command(0x%x)!\n",
HCLGE_OPC_PF_RST_DONE);
return 0;
} else if (ret) {
dev_err(&hdev->pdev->dev, "assert PF reset done fail %d!\n",
ret);
}
return ret;
}
static int hclge_reset_prepare_up(struct hclge_dev *hdev)
{
int ret = 0;
switch (hdev->reset_type) {
case HNAE3_FUNC_RESET:
case HNAE3_FLR_RESET:
ret = hclge_set_all_vf_rst(hdev, false);
break;
case HNAE3_GLOBAL_RESET:
case HNAE3_IMP_RESET:
ret = hclge_set_rst_done(hdev);
break;
default:
break;
}
/* clear up the handshake status after re-initialize done */
hclge_reset_handshake(hdev, false);
return ret;
}
static int hclge_reset_stack(struct hclge_dev *hdev)
{
int ret;
ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
if (ret)
return ret;
ret = hclge_reset_ae_dev(hdev->ae_dev);
if (ret)
return ret;
static int hclge_reset_prepare(struct hclge_dev *hdev)
{
int ret;
hdev->rst_stats.reset_cnt++;
/* perform reset of the stack & ae device for a client */
ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
if (ret)
return ret;
rtnl_lock();
ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
rtnl_unlock();
if (ret)
return ret;
return hclge_reset_prepare_wait(hdev);
}
static int hclge_reset_rebuild(struct hclge_dev *hdev)
{
int ret;
hdev->rst_stats.hw_reset_done_cnt++;
ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
if (ret)
return ret;
rtnl_lock();
ret = hclge_reset_stack(hdev);
rtnl_unlock();
if (ret)
return ret;
hclge_clear_reset_cause(hdev);
ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
/* ignore RoCE notify error if it fails HCLGE_RESET_MAX_FAIL_CNT - 1
* times
*/
if (ret &&
hdev->rst_stats.reset_fail_cnt < HCLGE_RESET_MAX_FAIL_CNT - 1)
return ret;
ret = hclge_reset_prepare_up(hdev);
if (ret)
return ret;
rtnl_lock();
ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
rtnl_unlock();
if (ret)
return ret;
ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
if (ret)
return ret;
/* We might end up getting called broadly because of 2 below cases:
* 1. Recoverable error was conveyed through APEI and only way to bring
* normalcy is to reset.
* 2. A new reset request from the stack due to timeout
*
* check if this is a new reset request and we are not here just because
* last reset attempt did not succeed and watchdog hit us again. We will
* know this if last reset request did not occur very recently (watchdog
* timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
* In case of new request we reset the "reset level" to PF reset.
* And if it is a repeat reset request of the most recent one then we
* want to make sure we throttle the reset request. Therefore, we will
* not allow it again before 3*HZ times.
*/
/* if default_reset_request has no value, it means that this reset
* request has already be handled, so just return here
*/
if (!hdev->default_reset_request)
return;
dev_info(&hdev->pdev->dev,
"triggering reset in reset timer\n");
hclge_reset_event(hdev->pdev, NULL);
}
/* check if there is any ongoing reset in the hardware. This status can
* be checked from reset_pending. If there is then, we need to wait for
* hardware to complete reset.
* a. If we are able to figure out in reasonable time that hardware
* has fully resetted then, we can proceed with driver, client
* reset.
* b. else, we can come back later to check this status so re-sched
* now.
*/
hdev->last_reset_time = jiffies;
hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending);
if (hdev->reset_type != HNAE3_NONE_RESET)
hclge_reset(hdev);
/* check if we got any *new* reset requests to be honored */
hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request);
if (hdev->reset_type != HNAE3_NONE_RESET)
hclge_do_reset(hdev);
msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
if (hclge_handle_hw_msix_error
(hdev, &hdev->default_reset_request))
dev_info(dev, "received msix interrupt 0x%x\n",
msix_sts_reg);
}
hclge_handle_hw_ras_error(ae_dev);
hclge_handle_err_reset_request(hdev);
}
static void hclge_errhand_service_task(struct hclge_dev *hdev)
{
if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
return;
if (hnae3_dev_ras_imp_supported(hdev))
hclge_handle_err_recovery(hdev);
else
hclge_misc_err_recovery(hdev);
}
static void hclge_reset_service_task(struct hclge_dev *hdev)
{
if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
return;
if (time_is_before_jiffies(hdev->last_rst_scheduled +
HCLGE_RESET_SCHED_TIMEOUT))
dev_warn(&hdev->pdev->dev,
"reset service task is scheduled after %ums on cpu%u!\n",
jiffies_to_msecs(jiffies - hdev->last_rst_scheduled),
smp_processor_id());
if (test_bit(HCLGE_STATE_RST_FAIL, &hdev->state))
return;
/* Always handle the link updating to make sure link state is
* updated when it is triggered by mbx.
*/
hclge_update_link_status(hdev);
hclge_sync_mac_table(hdev);
hclge_sync_promisc_mode(hdev);
hclge_sync_fd_table(hdev);
if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
delta = jiffies - hdev->last_serv_processed;
/* to prevent concurrence with the irq handler */
spin_lock_irqsave(&hdev->ptp->lock, flags);
/* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq
* handler may handle it just before spin_lock_irqsave().
*/
if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state))
hclge_ptp_clean_tx_hwts(hdev);
/* Handle error recovery, reset and mbx again in case periodical task
* delays the handling by calling hclge_task_schedule() in
* hclge_periodic_service_task().
*/
hclge_errhand_service_task(hdev);
hclge_reset_service_task(hdev);
hclge_mailbox_service_task(hdev);
}
struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
{
/* VF handle has no client */
if (!handle->client)
return container_of(handle, struct hclge_vport, nic);
else if (handle->client->type == HNAE3_CLIENT_ROCE)
return container_of(handle, struct hclge_vport, roce);
else
return container_of(handle, struct hclge_vport, nic);
}
ret = hclge_comm_set_rss_hash_key(rss_cfg, &hdev->hw.hw, key, hfunc);
if (ret) {
dev_err(&hdev->pdev->dev, "invalid hfunc type %u\n", hfunc);
return ret;
}
/* Update the shadow RSS table with user specified qids */
for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
rss_cfg->rss_indirection_tbl[i] = indir[i];
/* Update the hardware */
return hclge_comm_set_rss_indir_table(ae_dev, &hdev->hw.hw,
rss_cfg->rss_indirection_tbl);
}
ret = hclge_comm_set_rss_tuple(hdev->ae_dev, &hdev->hw.hw,
&hdev->rss_cfg, nfc);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to set rss tuple, ret = %d.\n", ret);
return ret;
}
return 0;
}
static int hclge_get_rss_tuple(struct hnae3_handle *handle,
struct ethtool_rxfh_fields *nfc)
{
struct hclge_vport *vport = hclge_get_vport(handle);
u8 tuple_sets;
int ret;
nfc->data = 0;
ret = hclge_comm_get_rss_tuple(&vport->back->rss_cfg, nfc->flow_type,
&tuple_sets);
if (ret || !tuple_sets)
return ret;
tc_info = &vport->nic.kinfo.tc_info;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
rss_size = tc_info->tqp_count[i];
tc_valid[i] = 0;
if (!(hdev->hw_tc_map & BIT(i)))
continue;
/* tc_size set to hardware is the log2 of roundup power of two
* of rss_size, the acutal queue size is limited by indirection
* table.
*/
if (rss_size > ae_dev->dev_specs.rss_ind_tbl_size ||
rss_size == 0) {
dev_err(&hdev->pdev->dev,
"Configure rss tc size failed, invalid TC_SIZE = %u\n",
rss_size);
return -EINVAL;
}
static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, int vector,
struct hnae3_ring_chain_node *ring_chain)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
int vector_id, ret;
if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
return 0;
vector_id = hclge_get_vector_index(hdev, vector);
if (vector_id < 0) {
dev_err(&handle->pdev->dev,
"Get vector index fail. ret =%d\n", vector_id);
return vector_id;
}
ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
if (ret)
dev_err(&handle->pdev->dev,
"Unmap ring from vector fail. vectorid=%d, ret =%d\n",
vector_id, ret);
/* For device whose version below V2, if broadcast promisc enabled,
* vlan filter is always bypassed. So broadcast promisc should be
* disabled until user enable promisc mode
*/
if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false;
static void hclge_update_fd_rule_node(struct hclge_dev *hdev,
struct hclge_fd_rule *old_rule,
struct hclge_fd_rule *new_rule,
enum HCLGE_FD_NODE_STATE state)
{
switch (state) {
case HCLGE_FD_TO_ADD:
case HCLGE_FD_ACTIVE:
/* 1) if the new state is TO_ADD, just replace the old rule
* with the same location, no matter its state, because the
* new rule will be configured to the hardware.
* 2) if the new state is ACTIVE, it means the new rule
* has been configured to the hardware, so just replace
* the old rule node with the same location.
* 3) for it doesn't add a new node to the list, so it's
* unnecessary to update the rule number and fd_bmap.
*/
new_rule->rule_node.next = old_rule->rule_node.next;
new_rule->rule_node.pprev = old_rule->rule_node.pprev;
memcpy(old_rule, new_rule, sizeof(*old_rule));
kfree(new_rule);
break;
case HCLGE_FD_DELETED:
hclge_fd_dec_rule_cnt(hdev, old_rule->location);
hclge_fd_free_node(hdev, old_rule);
break;
case HCLGE_FD_TO_DEL:
/* if new request is TO_DEL, and old rule is existent
* 1) the state of old rule is TO_DEL, we need do nothing,
* because we delete rule by location, other rule content
* is unncessary.
* 2) the state of old rule is ACTIVE, we need to change its
* state to TO_DEL, so the rule will be deleted when periodic
* task being scheduled.
* 3) the state of old rule is TO_ADD, it means the rule hasn't
* been added to hardware, so we just delete the rule node from
* fd_rule_list directly.
*/
if (old_rule->state == HCLGE_FD_TO_ADD) {
hclge_fd_dec_rule_cnt(hdev, old_rule->location);
hclge_fd_free_node(hdev, old_rule);
return;
}
old_rule->state = HCLGE_FD_TO_DEL;
break;
}
}
hlist_for_each_entry_safe(rule, node, hlist, rule_node) {
if (rule->location == location)
return rule;
else if (rule->location > location)
return NULL;
/* record the parent node, use to keep the nodes in fd_rule_list
* in ascend order.
*/
*parent = rule;
}
return NULL;
}
/* insert fd rule node in ascend order according to rule->location */
static void hclge_fd_insert_rule_node(struct hlist_head *hlist,
struct hclge_fd_rule *rule,
struct hclge_fd_rule *parent)
{
INIT_HLIST_NODE(&rule->rule_node);
if (parent)
hlist_add_behind(&rule->rule_node, &parent->rule_node);
else
hlist_add_head(&rule->rule_node, hlist);
}
static int hclge_fd_set_user_def_cmd(struct hclge_dev *hdev,
struct hclge_fd_user_def_cfg *cfg)
{
struct hclge_fd_user_def_cfg_cmd *req;
struct hclge_desc desc;
u16 data = 0;
int ret;
/* for valid layer is start from 1, so need minus 1 to get the cfg */
cfg = &hdev->fd_cfg.user_def_cfg[rule->ep.user_def.layer - 1];
info = &rule->ep.user_def;
if (!cfg->ref_cnt || cfg->offset == info->offset)
return 0;
if (cfg->ref_cnt > 1)
goto error;
fd_rule = hclge_find_fd_rule(hlist, rule->location, &parent);
if (fd_rule) {
old_info = &fd_rule->ep.user_def;
if (info->layer == old_info->layer)
return 0;
}
error:
dev_err(&hdev->pdev->dev,
"No available offset for layer%d fd rule, each layer only support one user def offset.\n",
info->layer + 1);
return -ENOSPC;
}
/* it's unlikely to fail here, because we have checked the rule
* exist before.
*/
if (unlikely(state == HCLGE_FD_TO_DEL || state == HCLGE_FD_DELETED)) {
dev_warn(&hdev->pdev->dev,
"failed to delete fd rule %u, it's inexistent\n",
location);
return;
}
/* If use max 400bit key, we can support tuples for ether type */
if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
key_cfg->tuple_active |=
BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
key_cfg->tuple_active |= HCLGE_FD_TUPLE_USER_DEF_TUPLES;
}
/* roce_type is used to filter roce frames
* dst_vport is used to specify the rule
*/
key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
ret = hclge_get_fd_allocation(hdev,
&hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
&hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
&hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
&hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
if (ret)
return ret;
/* A complete key is combined with meta data key and tuple key.
* Meta data key is stored at the MSB region, and tuple key is stored at
* the LSB region, unused bits will be filled 0.
*/
static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
struct hclge_fd_rule *rule)
{
struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
u8 *cur_key_x, *cur_key_y;
u8 meta_data_region;
u8 tuple_size;
int ret;
u32 i;
if (is_zero_ether_addr(spec->h_source))
*unused_tuple |= BIT(INNER_SRC_MAC);
if (is_zero_ether_addr(spec->h_dest))
*unused_tuple |= BIT(INNER_DST_MAC);
if (!spec->h_proto)
*unused_tuple |= BIT(INNER_ETH_TYPE);
return 0;
}
static int hclge_fd_check_ext_tuple(struct hclge_dev *hdev,
struct ethtool_rx_flow_spec *fs,
u32 *unused_tuple)
{
if (fs->flow_type & FLOW_EXT) {
if (fs->h_ext.vlan_etype) {
dev_err(&hdev->pdev->dev, "vlan-etype is not supported!\n");
return -EOPNOTSUPP;
}
if (!fs->h_ext.vlan_tci)
*unused_tuple |= BIT(INNER_VLAN_TAG_FST);
if (fs->m_ext.vlan_tci &&
be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID) {
dev_err(&hdev->pdev->dev,
"failed to config vlan_tci, invalid vlan_tci: %u, max is %d.\n",
ntohs(fs->h_ext.vlan_tci), VLAN_N_VID - 1);
return -EINVAL;
}
} else {
*unused_tuple |= BIT(INNER_VLAN_TAG_FST);
}
if (fs->flow_type & FLOW_MAC_EXT) {
if (hdev->fd_cfg.fd_mode !=
HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
dev_err(&hdev->pdev->dev,
"FLOW_MAC_EXT is not supported in current fd mode!\n");
return -EOPNOTSUPP;
}
if (is_zero_ether_addr(fs->h_ext.h_dest))
*unused_tuple |= BIT(INNER_DST_MAC);
else
*unused_tuple &= ~BIT(INNER_DST_MAC);
}
return 0;
}
static int hclge_fd_get_user_def_layer(u32 flow_type, u32 *unused_tuple,
struct hclge_fd_user_def_info *info)
{
switch (flow_type) {
case ETHER_FLOW:
info->layer = HCLGE_FD_USER_DEF_L2;
*unused_tuple &= ~BIT(INNER_L2_RSV);
break;
case IP_USER_FLOW:
case IPV6_USER_FLOW:
info->layer = HCLGE_FD_USER_DEF_L3;
*unused_tuple &= ~BIT(INNER_L3_RSV);
break;
case TCP_V4_FLOW:
case UDP_V4_FLOW:
case TCP_V6_FLOW:
case UDP_V6_FLOW:
info->layer = HCLGE_FD_USER_DEF_L4;
*unused_tuple &= ~BIT(INNER_L4_RSV);
break;
default:
return -EOPNOTSUPP;
}
if (!(fs->flow_type & FLOW_EXT) || hclge_fd_is_user_def_all_masked(fs))
return 0;
/* user-def data from ethtool is 64 bit value, the bit0~15 is used
* for data, and bit32~47 is used for offset.
*/
data = be32_to_cpu(fs->h_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
data_mask = be32_to_cpu(fs->m_ext.data[1]) & HCLGE_FD_USER_DEF_DATA;
offset = be32_to_cpu(fs->h_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
offset_mask = be32_to_cpu(fs->m_ext.data[0]) & HCLGE_FD_USER_DEF_OFFSET;
if (!(tuple_active & HCLGE_FD_TUPLE_USER_DEF_TUPLES)) {
dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
return -EOPNOTSUPP;
}
if (offset > HCLGE_FD_MAX_USER_DEF_OFFSET) {
dev_err(&hdev->pdev->dev,
"user-def offset[%u] should be no more than %u\n",
offset, HCLGE_FD_MAX_USER_DEF_OFFSET);
return -EINVAL;
}
if (offset_mask != HCLGE_FD_USER_DEF_OFFSET_UNMASK) {
dev_err(&hdev->pdev->dev, "user-def offset can't be masked\n");
return -EINVAL;
}
ret = hclge_fd_get_user_def_layer(flow_type, unused_tuple, info);
if (ret) {
dev_err(&hdev->pdev->dev,
"unsupported flow type for user-def bytes, ret = %d\n",
ret);
return ret;
}
static int hclge_fd_check_spec(struct hclge_dev *hdev,
struct ethtool_rx_flow_spec *fs,
u32 *unused_tuple,
struct hclge_fd_user_def_info *info)
{
u32 flow_type;
int ret;
if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
dev_err(&hdev->pdev->dev,
"failed to config fd rules, invalid rule location: %u, max is %u\n.",
fs->location,
hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1] - 1);
return -EINVAL;
}
ret = hclge_fd_parse_user_def_field(hdev, fs, unused_tuple, info);
if (ret)
return ret;
flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
switch (flow_type) {
case SCTP_V4_FLOW:
case TCP_V4_FLOW:
case UDP_V4_FLOW:
ret = hclge_fd_check_tcpip4_tuple(&fs->h_u.tcp_ip4_spec,
unused_tuple);
break;
case IP_USER_FLOW:
ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec,
unused_tuple);
break;
case SCTP_V6_FLOW:
case TCP_V6_FLOW:
case UDP_V6_FLOW:
ret = hclge_fd_check_tcpip6_tuple(&fs->h_u.tcp_ip6_spec,
unused_tuple);
break;
case IPV6_USER_FLOW:
ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec,
unused_tuple);
break;
case ETHER_FLOW:
if (hdev->fd_cfg.fd_mode !=
HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
dev_err(&hdev->pdev->dev,
"ETHER_FLOW is not supported in current fd mode!\n");
return -EOPNOTSUPP;
}
ret = hclge_fd_check_ether_tuple(&fs->h_u.ether_spec,
unused_tuple);
break;
default:
dev_err(&hdev->pdev->dev,
"unsupported protocol type, protocol type = %#x\n",
flow_type);
return -EOPNOTSUPP;
}
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to check flow union tuple, ret = %d\n",
ret);
return ret;
}
/* To keep consistent with user's configuration, minus 1 when
* printing 'vf', because vf id from ethtool is added 1 for vf.
*/
if (vf > hdev->num_req_vfs) {
dev_err(&hdev->pdev->dev,
"Error: vf id (%u) should be less than %u\n",
vf - 1U, hdev->num_req_vfs);
return -EINVAL;
}
/* Return ok here, because reset error handling will check this
* return value. If error is returned here, the reset process will
* fail.
*/
if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
return 0;
/* if fd is disabled, should not restore it when reset */
if (!hdev->fd_en)
return 0;
fs->flow_type = rule->flow_type;
switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
case SCTP_V4_FLOW:
case TCP_V4_FLOW:
case UDP_V4_FLOW:
hclge_fd_get_tcpip4_info(rule, &fs->h_u.tcp_ip4_spec,
&fs->m_u.tcp_ip4_spec);
break;
case IP_USER_FLOW:
hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec,
&fs->m_u.usr_ip4_spec);
break;
case SCTP_V6_FLOW:
case TCP_V6_FLOW:
case UDP_V6_FLOW:
hclge_fd_get_tcpip6_info(rule, &fs->h_u.tcp_ip6_spec,
&fs->m_u.tcp_ip6_spec);
break;
case IPV6_USER_FLOW:
hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec,
&fs->m_u.usr_ip6_spec);
break;
/* The flow type of fd rule has been checked before adding in to rule
* list. As other flow types have been handled, it must be ETHER_FLOW
* for the default case
*/
default:
hclge_fd_get_ether_info(rule, &fs->h_u.ether_spec,
&fs->m_u.ether_spec);
break;
}
if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
return -EOPNOTSUPP;
/* when there is already fd rule existed add by user,
* arfs should not work
*/
spin_lock_bh(&hdev->fd_rule_lock);
if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE &&
hdev->fd_active_type != HCLGE_FD_RULE_NONE) {
spin_unlock_bh(&hdev->fd_rule_lock);
return -EOPNOTSUPP;
}
hclge_fd_get_flow_tuples(fkeys, &new_tuples);
/* check is there flow director filter existed for this flow,
* if not, create a new filter for it;
* if filter exist with different queue id, modify the filter;
* if filter exist with same queue id, do nothing
*/
rule = hclge_fd_search_flow_keys(hdev, &new_tuples);
if (!rule) {
bit_id = find_first_zero_bit(hdev->fd_bmap, MAX_FD_FILTER_NUM);
if (bit_id >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]) {
spin_unlock_bh(&hdev->fd_rule_lock);
return -ENOSPC;
}
/* make sure being called after lock up with fd_rule_lock */
static int hclge_clear_arfs_rules(struct hclge_dev *hdev)
{
#ifdef CONFIG_RFS_ACCEL
struct hclge_fd_rule *rule;
struct hlist_node *node;
int ret;
if (hdev->fd_active_type != HCLGE_FD_ARFS_ACTIVE)
return 0;
hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
switch (rule->state) {
case HCLGE_FD_TO_DEL:
case HCLGE_FD_ACTIVE:
ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
rule->location, NULL, false);
if (ret)
return ret;
fallthrough;
case HCLGE_FD_TO_ADD:
hclge_fd_dec_rule_cnt(hdev, rule->location);
hlist_del(&rule->rule_node);
kfree(rule);
break;
default:
break;
}
}
hclge_sync_fd_state(hdev);
ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true, rule->location,
NULL, false);
if (ret) {
/* if tcam config fail, set rule state to TO_DEL,
* so the rule will be deleted when periodic
* task being scheduled.
*/
hclge_update_fd_list(hdev, HCLGE_FD_TO_DEL, rule->location, NULL);
set_bit(HCLGE_STATE_FD_TBL_CHANGED, &hdev->state);
spin_unlock_bh(&hdev->fd_rule_lock);
return ret;
}
static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
{
struct hclge_config_mac_mode_cmd *req;
struct hclge_desc desc;
u32 loop_en;
int ret;
req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
/* 1 Read out the MAC mode config at first */
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"mac loopback get fail, ret =%d.\n", ret);
return ret;
}
/* 2 Then setup the loopback flag */
loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
/* 3 Config mac work mode with loopback flag
* and its original configure parameters
*/
hclge_comm_cmd_reuse_desc(&desc, false);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
dev_err(&hdev->pdev->dev,
"mac loopback set fail, ret =%d.\n", ret);
return ret;
}
for (i = 0; i < handle->kinfo.num_tqps; i++) {
ret = hclge_tqp_enable_cmd_send(hdev, i, 0, enable);
if (ret)
return ret;
}
return 0;
}
static int hclge_set_loopback(struct hnae3_handle *handle,
enum hnae3_loop loop_mode, bool en)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
int ret = 0;
/* Loopback can be enabled in three places: SSU, MAC, and serdes. By
* default, SSU loopback is enabled, so if the SMAC and the DMAC are
* the same, the packets are looped back in the SSU. If SSU loopback
* is disabled, packets can reach MAC even if SMAC is the same as DMAC.
*/
if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B);
ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param,
HCLGE_SWITCH_ALW_LPBK_MASK);
if (ret)
return ret;
}
switch (loop_mode) {
case HNAE3_LOOP_APP:
ret = hclge_set_app_loopback(hdev, en);
break;
case HNAE3_LOOP_SERIAL_SERDES:
case HNAE3_LOOP_PARALLEL_SERDES:
ret = hclge_set_common_loopback(hdev, en, loop_mode);
break;
case HNAE3_LOOP_PHY:
ret = hclge_set_phy_loopback(hdev, en);
break;
case HNAE3_LOOP_EXTERNAL:
break;
default:
ret = -ENOTSUPP;
dev_err(&hdev->pdev->dev,
"loop_mode %d is not supported\n", loop_mode);
break;
}
if (ret)
return ret;
ret = hclge_tqp_enable(handle, en);
if (ret)
dev_err(&hdev->pdev->dev, "failed to %s tqp in loopback, ret = %d\n",
str_enable_disable(en), ret);
return ret;
}
static int hclge_set_default_loopback(struct hclge_dev *hdev)
{
int ret;
ret = hclge_set_app_loopback(hdev, false);
if (ret)
return ret;
ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES);
if (ret)
return ret;
/* If it is not PF reset or FLR, the firmware will disable the MAC,
* so it only need to stop phy here.
*/
if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,
HCLGE_PFC_DISABLE);
if (hdev->reset_type != HNAE3_FUNC_RESET &&
hdev->reset_type != HNAE3_FLR_RESET) {
hclge_mac_stop_phy(hdev);
hclge_update_link_status(hdev);
return;
}
}
hclge_reset_tqp(handle);
hclge_config_mac_tnl_int(hdev, false);
/* Mac disable */
hclge_cfg_mac_mode(hdev, false);
list_for_each_entry_safe(mac_node, tmp, list, node)
if (ether_addr_equal(mac_addr, mac_node->mac_addr))
return mac_node;
return NULL;
}
static void hclge_update_mac_node(struct hclge_mac_node *mac_node,
enum HCLGE_MAC_NODE_STATE state)
{
switch (state) {
/* from set_rx_mode or tmp_add_list */
case HCLGE_MAC_TO_ADD:
if (mac_node->state == HCLGE_MAC_TO_DEL)
mac_node->state = HCLGE_MAC_ACTIVE;
break;
/* only from set_rx_mode */
case HCLGE_MAC_TO_DEL:
if (mac_node->state == HCLGE_MAC_TO_ADD) {
list_del(&mac_node->node);
kfree(mac_node);
} else {
mac_node->state = HCLGE_MAC_TO_DEL;
}
break;
/* only from tmp_add_list, the mac_node->state won't be
* ACTIVE.
*/
case HCLGE_MAC_ACTIVE:
if (mac_node->state == HCLGE_MAC_TO_ADD)
mac_node->state = HCLGE_MAC_ACTIVE;
list = (mac_type == HCLGE_MAC_ADDR_UC) ?
&vport->uc_mac_list : &vport->mc_mac_list;
spin_lock_bh(&vport->mac_list_lock);
/* if the mac addr is already in the mac list, no need to add a new
* one into it, just check the mac addr state, convert it to a new
* state, or just remove it, or do nothing.
*/
mac_node = hclge_find_mac_node(list, addr);
if (mac_node) {
hclge_update_mac_node(mac_node, state);
spin_unlock_bh(&vport->mac_list_lock);
set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE, &vport->state);
return 0;
}
/* if this address is never added, unnecessary to delete */
if (state == HCLGE_MAC_TO_DEL) {
spin_unlock_bh(&vport->mac_list_lock);
hnae3_format_mac_addr(format_mac_addr, addr);
dev_err(&hdev->pdev->dev,
"failed to delete address %s from mac list\n",
format_mac_addr);
return -ENOENT;
}
/* Lookup the mac address in the mac_vlan table, and add
* it if the entry is inexistent. Repeated unicast entry
* is not allowed in the mac vlan table.
*/
ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
if (ret == -ENOENT) {
mutex_lock(&hdev->vport_lock);
if (!hclge_is_umv_space_full(vport, false)) {
ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
if (!ret)
hclge_update_umv_space(vport, false);
mutex_unlock(&hdev->vport_lock);
return ret;
}
mutex_unlock(&hdev->vport_lock);
if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_UPE))
dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
hdev->priv_umv_size);
return -ENOSPC;
}
/* check if we just hit the duplicate */
if (!ret)
return -EEXIST;
/* mac addr check */
if (!is_multicast_ether_addr(addr)) {
hnae3_format_mac_addr(format_mac_addr, addr);
dev_err(&hdev->pdev->dev,
"Add mc mac err! invalid mac:%s.\n",
format_mac_addr);
return -EINVAL;
}
memset(&req, 0, sizeof(req));
hclge_prepare_mac_addr(&req, addr, true);
status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
if (status) {
if (hnae3_ae_dev_mc_mac_mng_supported(hdev->ae_dev) &&
hdev->used_mc_mac_num >=
hdev->ae_dev->dev_specs.mc_mac_size)
goto err_no_space;
is_new_addr = true;
/* This mac addr do not exist, add new entry for it */
memset(desc[0].data, 0, sizeof(desc[0].data));
memset(desc[1].data, 0, sizeof(desc[0].data));
memset(desc[2].data, 0, sizeof(desc[0].data));
}
status = hclge_update_desc_vfid(desc, vport->vport_id, false);
if (status)
return status;
status = hclge_add_mac_vlan_tbl(vport, &req, desc);
if (status == -ENOSPC)
goto err_no_space;
else if (!status && is_new_addr)
hdev->used_mc_mac_num++;
return status;
err_no_space:
/* if already overflow, not to print each time */
if (!(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) {
vport->overflow_promisc_flags |= HNAE3_OVERFLOW_MPE;
dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
}
/* mac addr check */
if (!is_multicast_ether_addr(addr)) {
hnae3_format_mac_addr(format_mac_addr, addr);
dev_dbg(&hdev->pdev->dev,
"Remove mc mac err! invalid mac:%s.\n",
format_mac_addr);
return -EINVAL;
}
memset(&req, 0, sizeof(req));
hclge_prepare_mac_addr(&req, addr, true);
status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
if (!status) {
/* This mac addr exist, remove this handle's VFID for it */
status = hclge_update_desc_vfid(desc, vport->vport_id, true);
if (status)
return status;
if (hclge_is_all_function_id_zero(desc)) {
/* All the vfid is zero, so need to delete this entry */
status = hclge_remove_mac_vlan_tbl(vport, &req);
if (!status)
hdev->used_mc_mac_num--;
} else {
/* Not all the vfid is zero, update the vfid */
status = hclge_add_mac_vlan_tbl(vport, &req, desc);
}
} else if (status == -ENOENT) {
status = 0;
}
list_for_each_entry_safe(mac_node, tmp, list, node) {
ret = sync(vport, mac_node->mac_addr);
if (!ret) {
mac_node->state = HCLGE_MAC_ACTIVE;
} else {
set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
&vport->state);
/* If one unicast mac address is existing in hardware,
* we need to try whether other unicast mac addresses
* are new addresses that can be added.
* Multicast mac address can be reusable, even though
* there is no space to add new multicast mac address,
* we should check whether other mac addresses are
* existing in hardware for reuse.
*/
if ((mac_type == HCLGE_MAC_ADDR_UC && ret != -EEXIST) ||
(mac_type == HCLGE_MAC_ADDR_MC && ret != -ENOSPC))
break;
}
}
}
/* if the mac address from tmp_add_list is not in the
* uc/mc_mac_list, it means have received a TO_DEL request
* during the time window of adding the mac address into mac
* table. if mac_node state is ACTIVE, then change it to TO_DEL,
* then it will be removed at next time. else it must be TO_ADD,
* this address hasn't been added into mac table,
* so just remove the mac node.
*/
new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
if (new_node) {
hclge_update_mac_node(new_node, mac_node->state);
list_del(&mac_node->node);
kfree(mac_node);
} else if (mac_node->state == HCLGE_MAC_ACTIVE) {
mac_node->state = HCLGE_MAC_TO_DEL;
list_move_tail(&mac_node->node, mac_list);
} else {
list_del(&mac_node->node);
kfree(mac_node);
}
}
list_for_each_entry_safe(mac_node, tmp, del_list, node) {
new_node = hclge_find_mac_node(mac_list, mac_node->mac_addr);
if (new_node) {
/* If the mac addr exists in the mac list, it means
* received a new TO_ADD request during the time window
* of configuring the mac address. For the mac node
* state is TO_ADD, and the address is already in the
* in the hardware(due to delete fail), so we just need
* to change the mac node state to ACTIVE.
*/
new_node->state = HCLGE_MAC_ACTIVE;
list_del(&mac_node->node);
kfree(mac_node);
} else {
list_move_tail(&mac_node->node, mac_list);
}
}
}
/* move the mac addr to the tmp_add_list and tmp_del_list, then
* we can add/delete these mac addr outside the spin lock
*/
list = (mac_type == HCLGE_MAC_ADDR_UC) ?
&vport->uc_mac_list : &vport->mc_mac_list;
/* delete first, in order to get max mac table space for adding */
hclge_unsync_vport_mac_list(vport, &tmp_del_list, mac_type);
hclge_sync_vport_mac_list(vport, &tmp_add_list, mac_type);
/* if some mac addresses were added/deleted fail, move back to the
* mac_list, and retry at next time.
*/
spin_lock_bh(&vport->mac_list_lock);
list_for_each_entry_safe(mac_cfg, tmp, tmp_del_list, node) {
ret = unsync(vport, mac_cfg->mac_addr);
if (!ret || ret == -ENOENT) {
/* clear all mac addr from hardware, but remain these
* mac addr in the mac list, and restore them after
* vf reset finished.
*/
if (!is_del_list &&
mac_cfg->state == HCLGE_MAC_ACTIVE) {
mac_cfg->state = HCLGE_MAC_TO_ADD;
} else {
list_del(&mac_cfg->node);
kfree(mac_cfg);
}
} else if (is_del_list) {
mac_cfg->state = HCLGE_MAC_TO_DEL;
}
}
}
if (!list_empty(&tmp_del_list))
dev_warn(&hdev->pdev->dev,
"uninit %s mac list for vport %u not completely.\n",
mac_type == HCLGE_MAC_ADDR_UC ? "uc" : "mc",
vport->vport_id);
vport = hclge_get_vf_vport(hdev, vf);
if (!vport)
return -EINVAL;
hnae3_format_mac_addr(format_mac_addr, mac_addr);
if (ether_addr_equal(mac_addr, vport->vf_info.mac)) {
dev_info(&hdev->pdev->dev,
"Specified MAC(=%s) is same as before, no change committed!\n",
format_mac_addr);
return 0;
}
ether_addr_copy(vport->vf_info.mac, mac_addr);
/* there is a timewindow for PF to know VF unalive, it may
* cause send mailbox fail, but it doesn't matter, VF will
* query it when reinit.
*/
if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {
dev_info(&hdev->pdev->dev,
"MAC of VF %d has been set to %s, and it will be reinitialized!\n",
vf, format_mac_addr);
(void)hclge_inform_reset_assert_to_vf(vport);
return 0;
}
dev_info(&hdev->pdev->dev,
"MAC of VF %d has been set to %s, will be active after VF reset\n",
vf, format_mac_addr);
return 0;
}
static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
const struct hclge_mac_mgr_tbl_entry_cmd *req)
{
struct hclge_desc desc;
u8 resp_code;
u16 retval;
int ret;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"add mac ethertype failed for cmd_send, ret =%d.\n",
ret);
return ret;
}
static int init_mgr_tbl(struct hclge_dev *hdev)
{
int ret;
u32 i;
for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
if (ret) {
dev_err(&hdev->pdev->dev,
"add mac ethertype failed, ret =%d.\n",
ret);
return ret;
}
}
/* make sure the new addr is in the list head, avoid dev
* addr may be not re-added into mac table for the umv space
* limitation after global/imp reset which will clear mac
* table by hardware.
*/
list_move(&new_node->node, list);
}
if (old_addr && !ether_addr_equal(old_addr, new_addr)) {
old_node = hclge_find_mac_node(list, old_addr);
if (old_node) {
if (old_node->state == HCLGE_MAC_TO_ADD) {
list_del(&old_node->node);
kfree(old_node);
} else {
old_node->state = HCLGE_MAC_TO_DEL;
}
}
}
/* mac addr check */
if (is_zero_ether_addr(new_addr) ||
is_broadcast_ether_addr(new_addr) ||
is_multicast_ether_addr(new_addr)) {
hnae3_format_mac_addr(format_mac_addr, new_addr);
dev_err(&hdev->pdev->dev,
"change uc mac err! invalid mac: %s.\n",
format_mac_addr);
return -EINVAL;
}
ret = hclge_pause_addr_cfg(hdev, new_addr);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to configure mac pause address, ret = %d\n",
ret);
return ret;
}
if (!is_first)
old_addr = hdev->hw.mac.mac_addr;
spin_lock_bh(&vport->mac_list_lock);
ret = hclge_update_mac_node_for_dev_addr(vport, old_addr, new_addr);
if (ret) {
hnae3_format_mac_addr(format_mac_addr, new_addr);
dev_err(&hdev->pdev->dev,
"failed to change the mac addr:%s, ret = %d\n",
format_mac_addr, ret);
spin_unlock_bh(&vport->mac_list_lock);
if (!is_first)
hclge_pause_addr_cfg(hdev, old_addr);
return ret;
}
/* we must update dev addr with spin lock protect, preventing dev addr
* being removed by set_rx_mode path.
*/
ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
spin_unlock_bh(&vport->mac_list_lock);
hclge_task_schedule(hdev, 0);
return 0;
}
static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd)
{
struct mii_ioctl_data *data = if_mii(ifr);
if (!hnae3_dev_phy_imp_supported(hdev))
return -EOPNOTSUPP;
switch (cmd) {
case SIOCGMIIPHY:
data->phy_id = hdev->hw.mac.phy_addr;
/* this command reads phy id and register at the same time */
fallthrough;
case SIOCGMIIREG:
return hclge_read_phy_reg(hdev, data->reg_num, &data->val_out);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
dev_err(&hdev->pdev->dev,
"failed to set vport%u port vlan filter bypass state, ret = %d.\n",
vf_id, ret);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev, "failed to get vport%u vlan filter config, ret = %d.\n",
vf_id, ret);
return ret;
}
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
dev_err(&hdev->pdev->dev, "failed to set vport%u vlan filter, ret = %d.\n",
vf_id, ret);
return ret;
}
static int hclge_set_vport_vlan_filter(struct hclge_vport *vport, bool enable)
{
struct hclge_dev *hdev = vport->back;
struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
int ret;
if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
HCLGE_FILTER_FE_EGRESS_V1_B,
enable, vport->vport_id);
ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
HCLGE_FILTER_FE_EGRESS, enable,
vport->vport_id);
if (ret)
return ret;
if (test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps)) {
ret = hclge_set_port_vlan_filter_bypass(hdev, vport->vport_id,
!enable);
} else if (!vport->vport_id) {
if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
enable = false;
ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
HCLGE_FILTER_FE_INGRESS,
enable, 0);
}
if (!is_kill) {
#define HCLGE_VF_VLAN_NO_ENTRY 2
if (!req->resp_code || req->resp_code == 1)
return 0;
if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
set_bit(vfid, hdev->vf_vlan_full);
dev_warn(&hdev->pdev->dev,
"vf vlan table is full, vf vlan filter is disabled\n");
return 0;
}
dev_err(&hdev->pdev->dev,
"Add vf vlan filter fail, ret =%u.\n",
req->resp_code);
} else {
#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
if (!req->resp_code)
return 0;
/* vf vlan filter is disabled when vf vlan table is full,
* then new vlan id will not be added into vf vlan table.
* Just return 0 without warning, avoid massive verbose
* print logs when unload.
*/
if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND)
return 0;
dev_err(&hdev->pdev->dev,
"Kill vf vlan filter fail, ret =%u.\n",
req->resp_code);
}
/* if vf vlan table is full, firmware will close vf vlan filter, it
* is unable and unnecessary to add new vlan id to vf vlan filter.
* If spoof check is enable, and vf vlan is full, it shouldn't add
* new vlan, because tx packets with these vlan id will be dropped.
*/
if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) {
if (vport->vf_info.spoofchk && vlan) {
dev_err(&hdev->pdev->dev,
"Can't add vlan due to spoof check is on and vf vlan table is full\n");
return -EPERM;
}
return 0;
}
ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc);
if (ret)
return ret;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret)
dev_err(&hdev->pdev->dev,
"port vlan command, send fail, ret =%d.\n", ret);
return ret;
}
static bool hclge_need_update_port_vlan(struct hclge_dev *hdev, u16 vport_id,
u16 vlan_id, bool is_kill)
{
/* vlan 0 may be added twice when 8021q module is enabled */
if (!is_kill && !vlan_id &&
test_bit(vport_id, hdev->vlan_table[vlan_id]))
return false;
if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
dev_warn(&hdev->pdev->dev,
"Add port vlan failed, vport %u is already in vlan %u\n",
vport_id, vlan_id);
return false;
}
if (is_kill &&
!test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
dev_warn(&hdev->pdev->dev,
"Delete port vlan failed, vport %u is not in vlan %u\n",
vport_id, vlan_id);
return false;
}
return true;
}
static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
u16 vport_id, u16 vlan_id,
bool is_kill)
{
u16 vport_idx, vport_num = 0;
int ret;
if (is_kill && !vlan_id)
return 0;
if (vlan_id >= VLAN_N_VID)
return -EINVAL;
ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id);
if (ret) {
dev_err(&hdev->pdev->dev,
"Set %u vport vlan filter config fail, ret =%d.\n",
vport_id, ret);
return ret;
}
if (!hclge_need_update_port_vlan(hdev, vport_id, vlan_id, is_kill))
return 0;
/* accept_tag2 and accept_untag2 are not supported on
* pdev revision(0x20), new revision support them,
* this two fields can not be configured by user.
*/
vport->txvlan_cfg.accept_tag2 = true;
vport->txvlan_cfg.accept_untag2 = true;
vport->txvlan_cfg.insert_tag2_en = false;
vport->txvlan_cfg.default_tag2 = 0;
vport->txvlan_cfg.tag_shift_mode_en = true;
status = hclge_cmd_send(&hdev->hw, &desc, 1);
if (status)
dev_err(&hdev->pdev->dev,
"Send txvlan protocol type command fail, ret =%d\n",
status);
return status;
}
static int hclge_init_vlan_filter(struct hclge_dev *hdev)
{
struct hclge_vport *vport;
bool enable = true;
int ret;
int i;
if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
HCLGE_FILTER_FE_EGRESS_V1_B,
true, 0);
/* for revision 0x21, vf vlan filter is per function */
for (i = 0; i < hdev->num_alloc_vport; i++) {
vport = &hdev->vport[i];
ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
HCLGE_FILTER_FE_EGRESS, true,
vport->vport_id);
if (ret)
return ret;
vport->cur_vlan_fltr_en = true;
}
if (test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, hdev->ae_dev->caps) &&
!test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps))
enable = false;
if (vport->port_base_vlan_cfg.state == HNAE3_PORT_BASE_VLAN_DISABLE) {
list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
vport->vport_id,
vlan->vlan_id, false);
if (ret)
break;
vlan->hd_tbl_status = true;
}
}
mutex_unlock(&hdev->vport_lock);
}
/* For global reset and imp reset, hardware will clear the mac table,
* so we change the mac address state from ACTIVE to TO_ADD, then they
* can be restored in the service task after reset complete. Furtherly,
* the mac addresses with state TO_DEL or DEL_FAIL are unnecessary to
* be restored after reset, so just remove these mac nodes from mac_list.
*/
static void hclge_mac_node_convert_for_reset(struct list_head *list)
{
struct hclge_mac_node *mac_node, *tmp;
static int hclge_modify_port_base_vlan_tag(struct hclge_vport *vport,
struct hclge_vlan_info *new_info,
struct hclge_vlan_info *old_info)
{
struct hclge_dev *hdev = vport->back;
int ret;
/* add new VLAN tag */
ret = hclge_set_vlan_filter_hw(hdev, htons(new_info->vlan_proto),
vport->vport_id, new_info->vlan_tag,
false);
if (ret)
return ret;
vport->port_base_vlan_cfg.tbl_sta = false;
/* remove old VLAN tag */
if (old_info->vlan_tag == 0)
ret = hclge_set_vf_vlan_common(hdev, vport->vport_id,
true, 0);
else
ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
vport->vport_id,
old_info->vlan_tag, true);
if (ret)
dev_err(&hdev->pdev->dev,
"failed to clear vport%u port base vlan %u, ret = %d.\n",
vport->vport_id, old_info->vlan_tag, ret);
return ret;
}
int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
struct hclge_vlan_info *vlan_info)
{
struct hnae3_handle *nic = &vport->nic;
struct hclge_vlan_info *old_vlan_info;
int ret;
ret = hclge_vlan_offload_cfg(vport, state, vlan_info->vlan_tag,
vlan_info->qos);
if (ret)
return ret;
if (!hclge_need_update_vlan_filter(vlan_info, old_vlan_info))
goto out;
if (state == HNAE3_PORT_BASE_VLAN_MODIFY)
ret = hclge_modify_port_base_vlan_tag(vport, vlan_info,
old_vlan_info);
else
ret = hclge_update_vlan_filter_entries(vport, state, vlan_info,
old_vlan_info);
if (ret)
return ret;
if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
return -EOPNOTSUPP;
vport = hclge_get_vf_vport(hdev, vfid);
if (!vport)
return -EINVAL;
/* qos is a 3 bits value, so can not be bigger than 7 */
if (vlan > VLAN_N_VID - 1 || qos > 7)
return -EINVAL;
if (proto != htons(ETH_P_8021Q))
return -EPROTONOSUPPORT;
state = hclge_get_port_base_vlan_state(vport,
vport->port_base_vlan_cfg.state,
vlan, qos);
if (state == HNAE3_PORT_BASE_VLAN_NOCHANGE)
return 0;
ret = hclge_update_port_base_vlan_cfg(vport, state, &vlan_info);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to update port base vlan for vf %d, ret = %d\n",
vfid, ret);
return ret;
}
/* there is a timewindow for PF to know VF unalive, it may
* cause send mailbox fail, but it doesn't matter, VF will
* query it when reinit.
* for DEVICE_VERSION_V3, vf doesn't need to know about the port based
* VLAN state.
*/
if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
(void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
vport->vport_id,
state,
&vlan_info);
else
set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
&vport->need_notify);
}
return 0;
}
static void hclge_clear_vf_vlan(struct hclge_dev *hdev)
{
struct hclge_vlan_info *vlan_info;
struct hclge_vport *vport;
int ret;
int vf;
/* clear port base vlan for all vf */
for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
vport = &hdev->vport[vf];
vlan_info = &vport->port_base_vlan_cfg.vlan_info;
ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
vport->vport_id,
vlan_info->vlan_tag, true);
if (ret)
dev_err(&hdev->pdev->dev,
"failed to clear vf vlan for vf%d, ret = %d\n",
vf - HCLGE_VF_VPORT_START_NUM, ret);
}
}
int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
u16 vlan_id, bool is_kill)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
bool writen_to_tbl = false;
int ret = 0;
/* When device is resetting or reset failed, firmware is unable to
* handle mailbox. Just record the vlan id, and remove it after
* reset finished.
*/
mutex_lock(&hdev->vport_lock);
if ((test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
test_bit(HCLGE_STATE_RST_FAIL, &hdev->state)) && is_kill) {
set_bit(vlan_id, vport->vlan_del_fail_bmap);
mutex_unlock(&hdev->vport_lock);
return -EBUSY;
} else if (!is_kill && test_bit(vlan_id, vport->vlan_del_fail_bmap)) {
clear_bit(vlan_id, vport->vlan_del_fail_bmap);
}
mutex_unlock(&hdev->vport_lock);
/* when port base vlan enabled, we use port base vlan as the vlan
* filter entry. In this case, we don't update vlan filter table
* when user add new vlan or remove exist vlan, just update the vport
* vlan list. The vlan id in vlan list will be writen in vlan filter
* table until port base vlan disabled
*/
if (handle->port_base_vlan_state == HNAE3_PORT_BASE_VLAN_DISABLE) {
ret = hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id,
vlan_id, is_kill);
writen_to_tbl = true;
}
if (!ret) {
if (!is_kill) {
hclge_add_vport_vlan_table(vport, vlan_id,
writen_to_tbl);
} else if (is_kill && vlan_id != 0) {
mutex_lock(&hdev->vport_lock);
hclge_rm_vport_vlan_table(vport, vlan_id, false);
mutex_unlock(&hdev->vport_lock);
}
} else if (is_kill) {
/* when remove hw vlan filter failed, record the vlan id,
* and try to remove it from hw later, to be consistence
* with stack
*/
mutex_lock(&hdev->vport_lock);
set_bit(vlan_id, vport->vlan_del_fail_bmap);
mutex_unlock(&hdev->vport_lock);
}
for (i = 0; i < hdev->num_alloc_vport; i++) {
vport = &hdev->vport[i];
if (!test_and_clear_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
&vport->state))
continue;
mutex_lock(&hdev->vport_lock);
ret = __hclge_enable_vport_vlan_filter(vport,
vport->req_vlan_fltr_en);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to sync vlan filter state for vport%u, ret = %d\n",
vport->vport_id, ret);
set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
&vport->state);
mutex_unlock(&hdev->vport_lock);
return;
}
mutex_unlock(&hdev->vport_lock);
}
}
mutex_lock(&hdev->vport_lock);
/* start from vport 1 for PF is always alive */
for (i = 0; i < hdev->num_alloc_vport; i++) {
struct hclge_vport *vport = &hdev->vport[i];
vlan_id = find_first_bit(vport->vlan_del_fail_bmap,
VLAN_N_VID);
while (vlan_id != VLAN_N_VID) {
ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
vport->vport_id, vlan_id,
true);
if (ret && ret != -EINVAL) {
mutex_unlock(&hdev->vport_lock);
return;
}
max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
mutex_lock(&hdev->vport_lock);
/* VF's mps must fit within hdev->mps */
if (vport->vport_id && (u32)max_frm_size > hdev->mps) {
mutex_unlock(&hdev->vport_lock);
return -EINVAL;
} else if (vport->vport_id) {
vport->mps = max_frm_size;
mutex_unlock(&hdev->vport_lock);
return 0;
}
/* PF's mps must be greater then VF's mps */
for (i = 1; i < hdev->num_alloc_vport; i++)
if ((u32)max_frm_size < hdev->vport[i].mps) {
dev_err(&hdev->pdev->dev,
"failed to set pf mtu for less than vport %d, mps = %u.\n",
i, hdev->vport[i].mps);
mutex_unlock(&hdev->vport_lock);
return -EINVAL;
}
hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
ret = hclge_set_mac_mtu(hdev, max_frm_size);
if (ret) {
dev_err(&hdev->pdev->dev,
"Change mtu fail, ret =%d\n", ret);
goto out;
}
for (i = 0; i < handle->kinfo.num_tqps; i++) {
queue_gid = hclge_covert_handle_qid_global(handle, i);
ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, true);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to send reset tqp cmd, ret = %d\n",
ret);
return ret;
}
while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
ret = hclge_get_reset_status(hdev, queue_gid,
&reset_status);
if (ret)
return ret;
if (reset_status)
break;
/* Wait for tqp hw reset */
usleep_range(1000, 1200);
}
if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
dev_err(&hdev->pdev->dev,
"wait for tqp hw reset timeout\n");
return -ETIME;
}
ret = hclge_reset_tqp_cmd_send(hdev, queue_gid, false);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to deassert soft reset, ret = %d\n",
ret);
return ret;
}
reset_try_times = 0;
}
return 0;
}
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to send rcb reset cmd, ret = %d\n", ret);
return ret;
}
return_status = req->fun_reset_rcb_return_status;
if (return_status == HCLGE_RESET_RCB_SUCCESS)
return 0;
if (return_status != HCLGE_RESET_RCB_NOT_SUPPORT) {
dev_err(&hdev->pdev->dev, "failed to reset rcb, ret = %u\n",
return_status);
return -EIO;
}
/* if reset rcb cmd is unsupported, we need to send reset tqp cmd
* again to reset all tqps
*/
return hclge_reset_tqp_cmd(handle);
}
int hclge_reset_tqp(struct hnae3_handle *handle)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
int ret;
/* only need to disable PF's tqp */
if (!vport->vport_id) {
ret = hclge_tqp_enable(handle, false);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to disable tqp, ret = %d\n", ret);
return ret;
}
}
if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
dev_info(&hdev->pdev->dev,
"Priority flow control enabled. Cannot set link flow control.\n");
return -EOPNOTSUPP;
}
hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
hclge_record_user_pauseparam(hdev, rx_en, tx_en);
if (!auto_neg || hnae3_dev_phy_imp_supported(hdev))
return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
/* When nic is down, the service task is not running, doesn't update
* the port information per second. Query the port information before
* return the media type, ensure getting the correct media information.
*/
hclge_update_port_info(hdev);
if (media_type)
*media_type = hdev->hw.mac.media_type;
if (module_type)
*module_type = hdev->hw.mac.module_type;
}
if (!hnae3_dev_roce_supported(hdev) || !hdev->roce_client ||
!hdev->nic_client)
return 0;
client = hdev->roce_client;
ret = hclge_init_roce_base_info(vport);
if (ret)
return ret;
rst_cnt = hdev->rst_stats.reset_cnt;
ret = client->ops->init_instance(&vport->roce);
if (ret)
return ret;
set_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
rst_cnt != hdev->rst_stats.reset_cnt) {
ret = -EBUSY;
goto init_roce_err;
}
/* Enable roce ras interrupts */
ret = hclge_config_rocee_ras_interrupt(hdev, true);
if (ret) {
dev_err(&ae_dev->pdev->dev,
"fail(%d) to enable roce ras interrupts\n", ret);
goto init_roce_err;
}
hnae3_set_client_init_flag(client, ae_dev, 1);
return 0;
init_roce_err:
clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
msleep(HCLGE_WAIT_RESET_DONE);
if (hdev->reset_timer.function)
timer_delete_sync(&hdev->reset_timer);
if (hdev->service_task.work.func)
cancel_delayed_work_sync(&hdev->service_task);
}
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
/* This new command is only supported by new firmware, it will
* fail with older firmware. Error value -EOPNOSUPP can only be
* returned by older firmware running this command, to keep code
* backward compatible we will override this value and return
* success.
*/
if (ret && ret != -EOPNOTSUPP) {
dev_err(&hdev->pdev->dev,
"failed to clear hw resource, ret = %d\n", ret);
return ret;
}
return 0;
}
/* Firmware command queue initialize */
ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
if (ret)
goto err_pci_uninit;
/* Firmware command initialize */
hclge_comm_cmd_init_ops(&hdev->hw.hw, &hclge_cmq_ops);
ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
true, hdev->reset_pending);
if (ret)
goto err_cmd_uninit;
ret = hclge_clear_hw_resource(hdev);
if (ret)
goto err_cmd_uninit;
ret = hclge_get_cap(hdev);
if (ret)
goto err_cmd_uninit;
ret = hclge_query_dev_specs(hdev);
if (ret) {
dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n",
ret);
goto err_cmd_uninit;
}
ret = hclge_configure(hdev);
if (ret) {
dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
goto err_cmd_uninit;
}
ret = hclge_init_msi(hdev);
if (ret) {
dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
goto err_cmd_uninit;
}
ret = hclge_misc_irq_init(hdev);
if (ret)
goto err_msi_uninit;
ret = hclge_alloc_tqps(hdev);
if (ret) {
dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
goto err_msi_irq_uninit;
}
ret = hclge_alloc_vport(hdev);
if (ret)
goto err_msi_irq_uninit;
ret = hclge_map_tqp(hdev);
if (ret)
goto err_msi_irq_uninit;
if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
clear_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
if (hnae3_dev_phy_imp_supported(hdev))
ret = hclge_update_tp_port_info(hdev);
else
ret = hclge_mac_mdio_config(hdev);
if (ret)
goto err_msi_irq_uninit;
}
ret = hclge_init_umv_space(hdev);
if (ret)
goto err_mdiobus_unreg;
ret = hclge_mac_init(hdev);
if (ret) {
dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
goto err_mdiobus_unreg;
}
ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
if (ret) {
dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
goto err_mdiobus_unreg;
}
ret = hclge_config_gro(hdev);
if (ret)
goto err_mdiobus_unreg;
ret = hclge_init_vlan_config(hdev);
if (ret) {
dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
goto err_mdiobus_unreg;
}
ret = hclge_tm_schd_init(hdev);
if (ret) {
dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
goto err_mdiobus_unreg;
}
ret = hclge_comm_rss_init_cfg(&hdev->vport->nic, hdev->ae_dev,
&hdev->rss_cfg);
if (ret) {
dev_err(&pdev->dev, "failed to init rss cfg, ret = %d\n", ret);
goto err_mdiobus_unreg;
}
ret = hclge_rss_init_hw(hdev);
if (ret) {
dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
goto err_mdiobus_unreg;
}
ret = init_mgr_tbl(hdev);
if (ret) {
dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
goto err_mdiobus_unreg;
}
ret = hclge_init_fd_config(hdev);
if (ret) {
dev_err(&pdev->dev,
"fd table init fail, ret=%d\n", ret);
goto err_mdiobus_unreg;
}
ret = hclge_ptp_init(hdev);
if (ret)
goto err_mdiobus_unreg;
ret = hclge_update_port_info(hdev);
if (ret)
goto err_ptp_uninit;
/* Log and clear the hw errors those already occurred */
if (hnae3_dev_ras_imp_supported(hdev))
hclge_handle_occurred_error(hdev);
else
hclge_handle_all_hns_hw_errors(ae_dev);
/* request delayed reset for the error recovery because an immediate
* global reset on a PF affecting pending initialization of other PFs
*/
if (ae_dev->hw_err_reset_req) {
enum hnae3_reset_type reset_level;
static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
{
return hclge_config_switch_param(hdev, vf, enable,
HCLGE_SWITCH_ANTI_SPOOF_MASK);
}
static int hclge_set_vlan_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
{
return hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
HCLGE_FILTER_FE_NIC_INGRESS_B,
enable, vf);
}
static int hclge_set_vf_spoofchk_hw(struct hclge_dev *hdev, int vf, bool enable)
{
int ret;
ret = hclge_set_mac_spoofchk(hdev, vf, enable);
if (ret) {
dev_err(&hdev->pdev->dev,
"Set vf %d mac spoof check %s failed, ret=%d\n",
vf, str_on_off(enable), ret);
return ret;
}
ret = hclge_set_vlan_spoofchk(hdev, vf, enable);
if (ret)
dev_err(&hdev->pdev->dev,
"Set vf %d vlan spoof check %s failed, ret=%d\n",
vf, str_on_off(enable), ret);
return ret;
}
static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf,
bool enable)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
u32 new_spoofchk = enable ? 1 : 0;
int ret;
if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
return -EOPNOTSUPP;
vport = hclge_get_vf_vport(hdev, vf);
if (!vport)
return -EINVAL;
if (vport->vf_info.spoofchk == new_spoofchk)
return 0;
if (enable && test_bit(vport->vport_id, hdev->vf_vlan_full))
dev_warn(&hdev->pdev->dev,
"vf %d vlan table is full, enable spoof check may cause its packet send fail\n",
vf);
else if (enable && hclge_is_umv_space_full(vport, true))
dev_warn(&hdev->pdev->dev,
"vf %d mac table is full, enable spoof check may cause its packet send fail\n",
vf);
ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, enable);
if (ret)
return ret;
static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev)
{
struct hclge_vport *vport = hdev->vport;
int ret;
int i;
if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
return 0;
/* resume the vf spoof check state after reset */
for (i = 0; i < hdev->num_alloc_vport; i++) {
ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id,
vport->vf_info.spoofchk);
if (ret)
return ret;
for (i = 0; i < hdev->num_alloc_vport; i++) {
clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
vport++;
}
}
static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
{
struct hclge_dev *hdev = ae_dev->priv;
struct pci_dev *pdev = ae_dev->pdev;
int ret;
set_bit(HCLGE_STATE_DOWN, &hdev->state);
hclge_stats_clear(hdev);
/* NOTE: pf reset needn't to clear or restore pf and vf table entry.
* so here should not clean table in memory.
*/
if (hdev->reset_type == HNAE3_IMP_RESET ||
hdev->reset_type == HNAE3_GLOBAL_RESET) {
memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full));
bitmap_set(hdev->vport_config_block, 0, hdev->num_alloc_vport);
hclge_reset_umv_space(hdev);
}
ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
true, hdev->reset_pending);
if (ret) {
dev_err(&pdev->dev, "Cmd queue init failed\n");
return ret;
}
ret = hclge_map_tqp(hdev);
if (ret) {
dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
return ret;
}
ret = hclge_mac_init(hdev);
if (ret) {
dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
return ret;
}
ret = hclge_tp_port_init(hdev);
if (ret) {
dev_err(&pdev->dev, "failed to init tp port, ret = %d\n",
ret);
return ret;
}
ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
if (ret) {
dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
return ret;
}
ret = hclge_config_gro(hdev);
if (ret)
return ret;
ret = hclge_init_vlan_config(hdev);
if (ret) {
dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
return ret;
}
hclge_reset_tc_config(hdev);
ret = hclge_tm_init_hw(hdev, true);
if (ret) {
dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
return ret;
}
ret = hclge_rss_init_hw(hdev);
if (ret) {
dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
return ret;
}
ret = init_mgr_tbl(hdev);
if (ret) {
dev_err(&pdev->dev,
"failed to reinit manager table, ret = %d\n", ret);
return ret;
}
ret = hclge_init_fd_config(hdev);
if (ret) {
dev_err(&pdev->dev, "fd table init fail, ret=%d\n", ret);
return ret;
}
ret = hclge_ptp_init(hdev);
if (ret)
return ret;
/* Log and clear the hw errors those already occurred */
if (hnae3_dev_ras_imp_supported(hdev))
hclge_handle_occurred_error(hdev);
else
hclge_handle_all_hns_hw_errors(ae_dev);
/* Re-enable the hw error interrupts because
* the interrupts get disabled on global reset.
*/
ret = hclge_config_nic_hw_error(hdev, true);
if (ret) {
dev_err(&pdev->dev,
"fail(%d) to re-enable NIC hw error interrupts\n",
ret);
return ret;
}
if (hdev->roce_client) {
ret = hclge_config_rocee_ras_interrupt(hdev, true);
if (ret) {
dev_err(&pdev->dev,
"fail(%d) to re-enable roce ras interrupts\n",
ret);
return ret;
}
}
hclge_reset_vport_state(hdev);
ret = hclge_reset_vport_spoofchk(hdev);
if (ret)
return ret;
ret = hclge_resume_vf_rate(hdev);
if (ret)
return ret;
hclge_init_rxd_adv_layout(hdev);
ret = hclge_update_wol(hdev);
if (ret)
dev_warn(&pdev->dev,
"failed to update wol config, ret = %d\n", ret);
roundup_size = roundup_pow_of_two(vport->nic.kinfo.rss_size);
roundup_size = ilog2(roundup_size);
/* Set the RSS TC mode according to the new RSS size */
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
tc_valid[i] = 0;
ret = hclge_tm_vport_map_update(hdev);
if (ret) {
dev_err(&hdev->pdev->dev, "tm vport map fail, ret =%d\n", ret);
return ret;
}
ret = hclge_set_rss_tc_mode_cfg(handle);
if (ret)
return ret;
/* RSS indirection table has been configured by user */
if (rxfh_configured)
goto out;
/* Reinitializes the rss indirect table according to the new RSS size */
rss_indir = kcalloc(ae_dev->dev_specs.rss_ind_tbl_size, sizeof(u32),
GFP_KERNEL);
if (!rss_indir)
return -ENOMEM;
for (i = 0; i < ae_dev->dev_specs.rss_ind_tbl_size; i++)
rss_indir[i] = i % kinfo->rss_size;
ret = hclge_set_rss(handle, rss_indir, NULL, 0);
if (ret)
dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
ret);
kfree(rss_indir);
out:
if (!ret)
dev_info(&hdev->pdev->dev,
"Channels changed, rss_size from %u to %u, tqps from %u to %u",
cur_rss_size, kinfo->rss_size,
cur_tqps, kinfo->rss_size * kinfo->tc_info.num_tc);
return ret;
}
static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
{
struct hclge_set_led_state_cmd *req;
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_SFP_EXIST, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to get SFP exist state, ret = %d\n", ret);
return false;
}
existed = le32_to_cpu(desc.data[0]);
return existed != 0;
}
/* need 6 bds(total 140 bytes) in one reading
* return the number of bytes actually read, 0 means read failed.
*/
static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset,
u32 len, u8 *data)
{
struct hclge_desc desc[HCLGE_SFP_INFO_CMD_NUM];
struct hclge_sfp_info_bd0_cmd *sfp_info_bd0;
u16 read_len;
u16 copy_len;
int ret;
int i;
/* setup all 6 bds to read module eeprom info. */
for (i = 0; i < HCLGE_SFP_INFO_CMD_NUM; i++) {
hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_SFP_EEPROM,
true);
/* bd0~bd4 need next flag */
if (i < HCLGE_SFP_INFO_CMD_NUM - 1)
desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
}
if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2)
return -EOPNOTSUPP;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to query link diagnosis info, ret = %d\n", ret);
return ret;
}
/* After disable sriov, VF still has some config and info need clean,
* which configed by PF.
*/
static void hclge_clear_vport_vf_info(struct hclge_vport *vport, int vfid)
{
struct hclge_dev *hdev = vport->back;
struct hclge_vlan_info vlan_info;
int ret;
/* after disable sriov, clean VF rate configured by PF */
ret = hclge_tm_qs_shaper_cfg(vport, 0);
if (ret)
dev_err(&hdev->pdev->dev,
"failed to clean vf%d rate config, ret = %d\n",
vfid, ret);
vlan_info.vlan_tag = 0;
vlan_info.qos = 0;
vlan_info.vlan_proto = ETH_P_8021Q;
ret = hclge_update_port_base_vlan_cfg(vport,
HNAE3_PORT_BASE_VLAN_DISABLE,
&vlan_info);
if (ret)
dev_err(&hdev->pdev->dev,
"failed to clean vf%d port base vlan, ret = %d\n",
vfid, ret);
ret = hclge_set_vf_spoofchk_hw(hdev, vport->vport_id, false);
if (ret)
dev_err(&hdev->pdev->dev,
"failed to clean vf%d spoof config, ret = %d\n",
vfid, ret);
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