/** * e1000e_check_reset_block_generic - Check if PHY reset is blocked * @hw: pointer to the HW structure * * Read the PHY management control register and check whether a PHY reset * is blocked. If a reset is not blocked return 0, otherwise * return E1000_BLK_PHY_RESET (12).
**/
s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
{
u32 manc;
/** * e1000e_get_phy_id - Retrieve the PHY ID and revision * @hw: pointer to the HW structure * * Reads the PHY registers and stores the PHY ID and possibly the PHY * revision in the hardware structure.
**/
s32 e1000e_get_phy_id(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val = 0;
u16 phy_id;
u16 retry_count = 0;
if (!phy->ops.read_reg) return 0;
while (retry_count < 2) {
ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); if (ret_val) return ret_val;
/** * e1000e_read_phy_reg_mdic - Read MDI control register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * * Reads the MDI control register in the PHY at offset and stores the * information read to data.
**/
s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
{
u32 i, mdic = 0, retry_counter, retry_max; struct e1000_phy_info *phy = &hw->phy; bool success;
if (offset > MAX_PHY_REG_ADDRESS) {
e_dbg("PHY Address %d is out of range\n", offset); return -E1000_ERR_PARAM;
}
/* Set up Op-code, Phy Address, and register offset in the MDI * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data.
*/ for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
success = true;
/* Poll the ready bit to see if the MDI read completed * Increasing the time out as testing showed failures with * the lower time out
*/ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
udelay(50);
mdic = er32(MDIC); if (mdic & E1000_MDIC_READY) break;
} if (!(mdic & E1000_MDIC_READY)) {
e_dbg("MDI Read PHY Reg Address %d did not complete\n",
offset);
success = false;
} if (mdic & E1000_MDIC_ERROR) {
e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
success = false;
} if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
e_dbg("MDI Read offset error - requested %d, returned %d\n",
offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
success = false;
}
/* Allow some time after each MDIC transaction to avoid * reading duplicate data in the next MDIC transaction.
*/ if (hw->mac.type == e1000_pch2lan)
udelay(100);
if (success) {
*data = (u16)mdic; return 0;
}
if (retry_counter != retry_max) {
e_dbg("Perform retry on PHY transaction...\n");
mdelay(10);
}
}
return -E1000_ERR_PHY;
}
/** * e1000e_write_phy_reg_mdic - Write MDI control register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write to register at offset * * Writes data to MDI control register in the PHY at offset.
**/
s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
{
u32 i, mdic = 0, retry_counter, retry_max; struct e1000_phy_info *phy = &hw->phy; bool success;
if (offset > MAX_PHY_REG_ADDRESS) {
e_dbg("PHY Address %d is out of range\n", offset); return -E1000_ERR_PARAM;
}
/* Set up Op-code, Phy Address, and register offset in the MDI * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data.
*/ for (retry_counter = 0; retry_counter <= retry_max; retry_counter++) {
success = true;
/* Poll the ready bit to see if the MDI read completed * Increasing the time out as testing showed failures with * the lower time out
*/ for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
udelay(50);
mdic = er32(MDIC); if (mdic & E1000_MDIC_READY) break;
} if (!(mdic & E1000_MDIC_READY)) {
e_dbg("MDI Write PHY Reg Address %d did not complete\n",
offset);
success = false;
} if (mdic & E1000_MDIC_ERROR) {
e_dbg("MDI Write PHY Reg Address %d Error\n", offset);
success = false;
} if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
e_dbg("MDI Write offset error - requested %d, returned %d\n",
offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
success = false;
}
/* Allow some time after each MDIC transaction to avoid * reading duplicate data in the next MDIC transaction.
*/ if (hw->mac.type == e1000_pch2lan)
udelay(100);
if (success) return 0;
if (retry_counter != retry_max) {
e_dbg("Perform retry on PHY transaction...\n");
mdelay(10);
}
}
return -E1000_ERR_PHY;
}
/** * e1000e_read_phy_reg_m88 - Read m88 PHY register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * * Acquires semaphore, if necessary, then reads the PHY register at offset * and storing the retrieved information in data. Release any acquired * semaphores before exiting.
**/
s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
{
s32 ret_val;
ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val;
/** * e1000e_write_phy_reg_m88 - Write m88 PHY register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * * Acquires semaphore, if necessary, then writes the data to PHY register * at the offset. Release any acquired semaphores before exiting.
**/
s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
{
s32 ret_val;
ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val;
/** * e1000_set_page_igp - Set page as on IGP-like PHY(s) * @hw: pointer to the HW structure * @page: page to set (shifted left when necessary) * * Sets PHY page required for PHY register access. Assumes semaphore is * already acquired. Note, this function sets phy.addr to 1 so the caller * must set it appropriately (if necessary) after this function returns.
**/
s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
{
e_dbg("Setting page 0x%x\n", page);
/** * __e1000e_read_phy_reg_igp - Read igp PHY register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * @locked: semaphore has already been acquired or not * * Acquires semaphore, if necessary, then reads the PHY register at offset * and stores the retrieved information in data. Release any acquired * semaphores before exiting.
**/ static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, bool locked)
{
s32 ret_val = 0;
if (!locked) { if (!hw->phy.ops.acquire) return 0;
ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val;
}
if (offset > MAX_PHY_MULTI_PAGE_REG)
ret_val = e1000e_write_phy_reg_mdic(hw,
IGP01E1000_PHY_PAGE_SELECT,
(u16)offset); if (!ret_val)
ret_val = e1000e_read_phy_reg_mdic(hw,
MAX_PHY_REG_ADDRESS & offset,
data); if (!locked)
hw->phy.ops.release(hw);
return ret_val;
}
/** * e1000e_read_phy_reg_igp - Read igp PHY register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * * Acquires semaphore then reads the PHY register at offset and stores the * retrieved information in data. * Release the acquired semaphore before exiting.
**/
s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
{ return __e1000e_read_phy_reg_igp(hw, offset, data, false);
}
/** * e1000e_read_phy_reg_igp_locked - Read igp PHY register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * * Reads the PHY register at offset and stores the retrieved information * in data. Assumes semaphore already acquired.
**/
s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
{ return __e1000e_read_phy_reg_igp(hw, offset, data, true);
}
/** * __e1000e_write_phy_reg_igp - Write igp PHY register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * @locked: semaphore has already been acquired or not * * Acquires semaphore, if necessary, then writes the data to PHY register * at the offset. Release any acquired semaphores before exiting.
**/ static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, bool locked)
{
s32 ret_val = 0;
if (!locked) { if (!hw->phy.ops.acquire) return 0;
ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val;
}
if (offset > MAX_PHY_MULTI_PAGE_REG)
ret_val = e1000e_write_phy_reg_mdic(hw,
IGP01E1000_PHY_PAGE_SELECT,
(u16)offset); if (!ret_val)
ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
offset, data); if (!locked)
hw->phy.ops.release(hw);
return ret_val;
}
/** * e1000e_write_phy_reg_igp - Write igp PHY register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * * Acquires semaphore then writes the data to PHY register * at the offset. Release any acquired semaphores before exiting.
**/
s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
{ return __e1000e_write_phy_reg_igp(hw, offset, data, false);
}
/** * e1000e_write_phy_reg_igp_locked - Write igp PHY register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * * Writes the data to PHY register at the offset. * Assumes semaphore already acquired.
**/
s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
{ return __e1000e_write_phy_reg_igp(hw, offset, data, true);
}
/** * __e1000_read_kmrn_reg - Read kumeran register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * @locked: semaphore has already been acquired or not * * Acquires semaphore, if necessary. Then reads the PHY register at offset * using the kumeran interface. The information retrieved is stored in data. * Release any acquired semaphores before exiting.
**/ static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, bool locked)
{
u32 kmrnctrlsta;
if (!locked) {
s32 ret_val = 0;
if (!hw->phy.ops.acquire) return 0;
ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val;
}
/** * e1000e_read_kmrn_reg - Read kumeran register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * * Acquires semaphore then reads the PHY register at offset using the * kumeran interface. The information retrieved is stored in data. * Release the acquired semaphore before exiting.
**/
s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{ return __e1000_read_kmrn_reg(hw, offset, data, false);
}
/** * e1000e_read_kmrn_reg_locked - Read kumeran register * @hw: pointer to the HW structure * @offset: register offset to be read * @data: pointer to the read data * * Reads the PHY register at offset using the kumeran interface. The * information retrieved is stored in data. * Assumes semaphore already acquired.
**/
s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
{ return __e1000_read_kmrn_reg(hw, offset, data, true);
}
/** * __e1000_write_kmrn_reg - Write kumeran register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * @locked: semaphore has already been acquired or not * * Acquires semaphore, if necessary. Then write the data to PHY register * at the offset using the kumeran interface. Release any acquired semaphores * before exiting.
**/ static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, bool locked)
{
u32 kmrnctrlsta;
if (!locked) {
s32 ret_val = 0;
if (!hw->phy.ops.acquire) return 0;
ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val;
}
/** * e1000e_write_kmrn_reg - Write kumeran register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * * Acquires semaphore then writes the data to the PHY register at the offset * using the kumeran interface. Release the acquired semaphore before exiting.
**/
s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
{ return __e1000_write_kmrn_reg(hw, offset, data, false);
}
/** * e1000e_write_kmrn_reg_locked - Write kumeran register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * * Write the data to PHY register at the offset using the kumeran interface. * Assumes semaphore already acquired.
**/
s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
{ return __e1000_write_kmrn_reg(hw, offset, data, true);
}
/** * e1000_set_master_slave_mode - Setup PHY for Master/slave mode * @hw: pointer to the HW structure * * Sets up Master/slave mode
**/ static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
{
s32 ret_val;
u16 phy_data;
ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); if (ret_val) return ret_val;
/* Set MDI/MDIX mode */
ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); if (ret_val) return ret_val;
phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; /* Options: * 0 - Auto (default) * 1 - MDI mode * 2 - MDI-X mode
*/ switch (hw->phy.mdix) { case 1: break; case 2:
phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; break; case 0: default:
phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; break;
}
ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); if (ret_val) return ret_val;
return e1000_set_master_slave_mode(hw);
}
/** * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link * @hw: pointer to the HW structure * * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock * and downshift values are set also.
**/
s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_data;
/* Enable CRS on Tx. This must be set for half-duplex operation. */
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val;
/* For BM PHY this bit is downshift enable */ if (phy->type != e1000_phy_bm)
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
/* Options: * MDI/MDI-X = 0 (default) * 0 - Auto for all speeds * 1 - MDI mode * 2 - MDI-X mode * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
*/
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
switch (phy->mdix) { case 1:
phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; break; case 2:
phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; break; case 3:
phy_data |= M88E1000_PSCR_AUTO_X_1000T; break; case 0: default:
phy_data |= M88E1000_PSCR_AUTO_X_MODE; break;
}
/* Enable downshift on BM (disabled by default) */ if (phy->type == e1000_phy_bm) { /* For 82574/82583, first disable then enable downshift */ if (phy->id == BME1000_E_PHY_ID_R2) {
phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
phy_data); if (ret_val) return ret_val; /* Commit the changes. */
ret_val = phy->ops.commit(hw); if (ret_val) {
e_dbg("Error committing the PHY changes\n"); return ret_val;
}
}
phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
}
ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); if (ret_val) return ret_val;
if ((phy->type == e1000_phy_m88) &&
(phy->revision < E1000_REVISION_4) &&
(phy->id != BME1000_E_PHY_ID_R2)) { /* Force TX_CLK in the Extended PHY Specific Control Register * to 25MHz clock.
*/
ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val;
phy_data |= M88E1000_EPSCR_TX_CLK_25;
if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) { /* 82573L PHY - set the downshift counter to 5x. */
phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
} else { /* Configure Master and Slave downshift values */
phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
}
ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); if (ret_val) return ret_val;
}
if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { /* Set PHY page 0, register 29 to 0x0003 */
ret_val = e1e_wphy(hw, 29, 0x0003); if (ret_val) return ret_val;
/* Set PHY page 0, register 30 to 0x0000 */
ret_val = e1e_wphy(hw, 30, 0x0000); if (ret_val) return ret_val;
}
/* Commit the changes. */ if (phy->ops.commit) {
ret_val = phy->ops.commit(hw); if (ret_val) {
e_dbg("Error committing the PHY changes\n"); return ret_val;
}
}
if (phy->type == e1000_phy_82578) {
ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val;
/* 82578 PHY - set the downshift count to 1x. */
phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); if (ret_val) return ret_val;
}
return 0;
}
/** * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link * @hw: pointer to the HW structure * * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for * igp PHY's.
**/
s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 data;
ret_val = e1000_phy_hw_reset(hw); if (ret_val) {
e_dbg("Error resetting the PHY.\n"); return ret_val;
}
/* Wait 100ms for MAC to configure PHY from NVM settings, to avoid * timeout issues when LFS is enabled.
*/
msleep(100);
/* disable lplu d0 during driver init */ if (hw->phy.ops.set_d0_lplu_state) {
ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); if (ret_val) {
e_dbg("Error Disabling LPLU D0\n"); return ret_val;
}
} /* Configure mdi-mdix settings */
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); if (ret_val) return ret_val;
data &= ~IGP01E1000_PSCR_AUTO_MDIX;
switch (phy->mdix) { case 1:
data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; break; case 2:
data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; break; case 0: default:
data |= IGP01E1000_PSCR_AUTO_MDIX; break;
}
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); if (ret_val) return ret_val;
/* set auto-master slave resolution settings */ if (hw->mac.autoneg) { /* when autonegotiation advertisement is only 1000Mbps then we * should disable SmartSpeed and enable Auto MasterSlave * resolution as hardware default.
*/ if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { /* Disable SmartSpeed */
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
&data); if (ret_val) return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
data); if (ret_val) return ret_val;
/* Set auto Master/Slave resolution process */
ret_val = e1e_rphy(hw, MII_CTRL1000, &data); if (ret_val) return ret_val;
data &= ~CTL1000_ENABLE_MASTER;
ret_val = e1e_wphy(hw, MII_CTRL1000, data); if (ret_val) return ret_val;
}
ret_val = e1000_set_master_slave_mode(hw);
}
return ret_val;
}
/** * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation * @hw: pointer to the HW structure * * Reads the MII auto-neg advertisement register and/or the 1000T control * register and if the PHY is already setup for auto-negotiation, then * return successful. Otherwise, setup advertisement and flow control to * the appropriate values for the wanted auto-negotiation.
**/ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 mii_autoneg_adv_reg;
u16 mii_1000t_ctrl_reg = 0;
phy->autoneg_advertised &= phy->autoneg_mask;
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg); if (ret_val) return ret_val;
if (phy->autoneg_mask & ADVERTISE_1000_FULL) { /* Read the MII 1000Base-T Control Register (Address 9). */
ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg); if (ret_val) return ret_val;
}
/* Need to parse both autoneg_advertised and fc and set up * the appropriate PHY registers. First we will parse for * autoneg_advertised software override. Since we can advertise * a plethora of combinations, we need to check each bit * individually.
*/
/* First we clear all the 10/100 mb speed bits in the Auto-Neg * Advertisement Register (Address 4) and the 1000 mb speed bits in * the 1000Base-T Control Register (Address 9).
*/
mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
ADVERTISE_100HALF |
ADVERTISE_10FULL | ADVERTISE_10HALF);
mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
/* Do we want to advertise 10 Mb Half Duplex? */ if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
e_dbg("Advertise 10mb Half duplex\n");
mii_autoneg_adv_reg |= ADVERTISE_10HALF;
}
/* Do we want to advertise 10 Mb Full Duplex? */ if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
e_dbg("Advertise 10mb Full duplex\n");
mii_autoneg_adv_reg |= ADVERTISE_10FULL;
}
/* Do we want to advertise 100 Mb Half Duplex? */ if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
e_dbg("Advertise 100mb Half duplex\n");
mii_autoneg_adv_reg |= ADVERTISE_100HALF;
}
/* Do we want to advertise 100 Mb Full Duplex? */ if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
e_dbg("Advertise 100mb Full duplex\n");
mii_autoneg_adv_reg |= ADVERTISE_100FULL;
}
/* We do not allow the Phy to advertise 1000 Mb Half Duplex */ if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
e_dbg("Advertise 1000mb Half duplex request denied!\n");
/* Do we want to advertise 1000 Mb Full Duplex? */ if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
e_dbg("Advertise 1000mb Full duplex\n");
mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
}
/* Check for a software override of the flow control settings, and * setup the PHY advertisement registers accordingly. If * auto-negotiation is enabled, then software will have to set the * "PAUSE" bits to the correct value in the Auto-Negotiation * Advertisement Register (MII_ADVERTISE) and re-start auto- * negotiation. * * The possible values of the "fc" parameter are: * 0: Flow control is completely disabled * 1: Rx flow control is enabled (we can receive pause frames * but not send pause frames). * 2: Tx flow control is enabled (we can send pause frames * but we do not support receiving pause frames). * 3: Both Rx and Tx flow control (symmetric) are enabled. * other: No software override. The flow control configuration * in the EEPROM is used.
*/ switch (hw->fc.current_mode) { case e1000_fc_none: /* Flow control (Rx & Tx) is completely disabled by a * software over-ride.
*/
mii_autoneg_adv_reg &=
~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
phy->autoneg_advertised &=
~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); break; case e1000_fc_rx_pause: /* Rx Flow control is enabled, and Tx Flow control is * disabled, by a software over-ride. * * Since there really isn't a way to advertise that we are * capable of Rx Pause ONLY, we will advertise that we * support both symmetric and asymmetric Rx PAUSE. Later * (in e1000e_config_fc_after_link_up) we will disable the * hw's ability to send PAUSE frames.
*/
mii_autoneg_adv_reg |=
(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
phy->autoneg_advertised |=
(ADVERTISED_Pause | ADVERTISED_Asym_Pause); break; case e1000_fc_tx_pause: /* Tx Flow control is enabled, and Rx Flow control is * disabled, by a software over-ride.
*/
mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
phy->autoneg_advertised |= ADVERTISED_Asym_Pause;
phy->autoneg_advertised &= ~ADVERTISED_Pause; break; case e1000_fc_full: /* Flow control (both Rx and Tx) is enabled by a software * over-ride.
*/
mii_autoneg_adv_reg |=
(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
phy->autoneg_advertised |=
(ADVERTISED_Pause | ADVERTISED_Asym_Pause); break; default:
e_dbg("Flow control param set incorrectly\n"); return -E1000_ERR_CONFIG;
}
ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg); if (ret_val) return ret_val;
if (phy->autoneg_mask & ADVERTISE_1000_FULL)
ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
return ret_val;
}
/** * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link * @hw: pointer to the HW structure * * Performs initial bounds checking on autoneg advertisement parameter, then * configure to advertise the full capability. Setup the PHY to autoneg * and restart the negotiation process between the link partner. If * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
**/ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_ctrl;
/* Perform some bounds checking on the autoneg advertisement * parameter.
*/
phy->autoneg_advertised &= phy->autoneg_mask;
/* If autoneg_advertised is zero, we assume it was not defaulted * by the calling code so we set to advertise full capability.
*/ if (!phy->autoneg_advertised)
phy->autoneg_advertised = phy->autoneg_mask;
e_dbg("Reconfiguring auto-neg advertisement params\n");
ret_val = e1000_phy_setup_autoneg(hw); if (ret_val) {
e_dbg("Error Setting up Auto-Negotiation\n"); return ret_val;
}
e_dbg("Restarting Auto-Neg\n");
/* Restart auto-negotiation by setting the Auto Neg Enable bit and * the Auto Neg Restart bit in the PHY control register.
*/
ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); if (ret_val) return ret_val;
/* Does the user want to wait for Auto-Neg to complete here, or * check at a later time (for example, callback routine).
*/ if (phy->autoneg_wait_to_complete) {
ret_val = e1000_wait_autoneg(hw); if (ret_val) {
e_dbg("Error while waiting for autoneg to complete\n"); return ret_val;
}
}
hw->mac.get_link_status = true;
return ret_val;
}
/** * e1000e_setup_copper_link - Configure copper link settings * @hw: pointer to the HW structure * * Calls the appropriate function to configure the link for auto-neg or forced * speed and duplex. Then we check for link, once link is established calls * to configure collision distance and flow control are called. If link is * not established, we return -E1000_ERR_PHY (-2).
**/
s32 e1000e_setup_copper_link(struct e1000_hw *hw)
{
s32 ret_val; bool link;
if (hw->mac.autoneg) { /* Setup autoneg and flow control advertisement and perform * autonegotiation.
*/
ret_val = e1000_copper_link_autoneg(hw); if (ret_val) return ret_val;
} else { /* PHY will be set to 10H, 10F, 100H or 100F * depending on user settings.
*/
e_dbg("Forcing Speed and Duplex\n");
ret_val = hw->phy.ops.force_speed_duplex(hw); if (ret_val) {
e_dbg("Error Forcing Speed and Duplex\n"); return ret_val;
}
}
/* Check link status. Wait up to 100 microseconds for link to become * valid.
*/
ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
&link); if (ret_val) return ret_val;
if (link) {
e_dbg("Valid link established!!!\n");
hw->mac.ops.config_collision_dist(hw);
ret_val = e1000e_config_fc_after_link_up(hw);
} else {
e_dbg("Unable to establish link!!!\n");
}
return ret_val;
}
/** * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY * @hw: pointer to the HW structure * * Calls the PHY setup function to force speed and duplex. Clears the * auto-crossover to force MDI manually. Waits for link and returns * successful if link up is successful, else -E1000_ERR_PHY (-2).
**/
s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_data; bool link;
ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); if (ret_val) return ret_val;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); if (ret_val) return ret_val;
e_dbg("IGP PSCR: %X\n", phy_data);
udelay(1);
if (phy->autoneg_wait_to_complete) {
e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
100000, &link); if (ret_val) return ret_val;
if (!link)
e_dbg("Link taking longer than expected.\n");
/* Try once more */
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
100000, &link);
}
return ret_val;
}
/** * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY * @hw: pointer to the HW structure * * Calls the PHY setup function to force speed and duplex. Clears the * auto-crossover to force MDI manually. Resets the PHY to commit the * changes. If time expires while waiting for link up, we reset the DSP. * After reset, TX_CLK and CRS on Tx must be set. Return successful upon * successful completion, else return corresponding error code.
**/
s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_data; bool link;
/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI * forced whenever speed and duplex are forced.
*/
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val;
ret_val = e1e_wphy(hw, MII_BMCR, phy_data); if (ret_val) return ret_val;
/* Reset the phy to commit changes. */ if (hw->phy.ops.commit) {
ret_val = hw->phy.ops.commit(hw); if (ret_val) return ret_val;
}
if (phy->autoneg_wait_to_complete) {
e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
100000, &link); if (ret_val) return ret_val;
if (!link) { if (hw->phy.type != e1000_phy_m88) {
e_dbg("Link taking longer than expected.\n");
} else { /* We didn't get link. * Reset the DSP and cross our fingers.
*/
ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
0x001d); if (ret_val) return ret_val;
ret_val = e1000e_phy_reset_dsp(hw); if (ret_val) return ret_val;
}
}
/* Try once more */
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
100000, &link); if (ret_val) return ret_val;
}
if (hw->phy.type != e1000_phy_m88) return 0;
ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val;
/* Resetting the phy means we need to re-force TX_CLK in the * Extended PHY Specific Control Register to 25MHz clock from * the reset value of 2.5MHz.
*/
phy_data |= M88E1000_EPSCR_TX_CLK_25;
ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); if (ret_val) return ret_val;
/* In addition, we must re-enable CRS on Tx for both half and full * duplex.
*/
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val;
/** * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex * @hw: pointer to the HW structure * * Forces the speed and duplex settings of the PHY. * This is a function pointer entry point only called by * PHY setup routines.
**/
s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 data; bool link;
ret_val = e1e_rphy(hw, MII_BMCR, &data); if (ret_val) return ret_val;
e1000e_phy_force_speed_duplex_setup(hw, &data);
ret_val = e1e_wphy(hw, MII_BMCR, data); if (ret_val) return ret_val;
/* Disable MDI-X support for 10/100 */
ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); if (ret_val) return ret_val;
data &= ~IFE_PMC_AUTO_MDIX;
data &= ~IFE_PMC_FORCE_MDIX;
ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); if (ret_val) return ret_val;
e_dbg("IFE PMC: %X\n", data);
udelay(1);
if (phy->autoneg_wait_to_complete) {
e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
100000, &link); if (ret_val) return ret_val;
if (!link)
e_dbg("Link taking longer than expected.\n");
/* Try once more */
ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
100000, &link); if (ret_val) return ret_val;
}
return 0;
}
/** * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex * @hw: pointer to the HW structure * @phy_ctrl: pointer to current value of MII_BMCR * * Forces speed and duplex on the PHY by doing the following: disable flow * control, force speed/duplex on the MAC, disable auto speed detection, * disable auto-negotiation, configure duplex, configure speed, configure * the collision distance, write configuration to CTRL register. The * caller must write to the MII_BMCR register for these settings to * take affect.
**/ void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
{ struct e1000_mac_info *mac = &hw->mac;
u32 ctrl;
/* Turn off flow control when forcing speed/duplex */
hw->fc.current_mode = e1000_fc_none;
/* Force speed/duplex on the mac */
ctrl = er32(CTRL);
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl &= ~E1000_CTRL_SPD_SEL;
/* Disable Auto Speed Detection */
ctrl &= ~E1000_CTRL_ASDE;
/* Disable autoneg on the phy */
*phy_ctrl &= ~BMCR_ANENABLE;
/** * e1000e_set_d3_lplu_state - Sets low power link up state for D3 * @hw: pointer to the HW structure * @active: boolean used to enable/disable lplu * * Success returns 0, Failure returns 1 * * The low power link up (lplu) state is set to the power management level D3 * and SmartSpeed is disabled when active is true, else clear lplu for D3 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU * is used during Dx states where the power conservation is most important. * During driver activity, SmartSpeed should be enabled so performance is * maintained.
**/
s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 data;
ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); if (ret_val) return ret_val;
if (!active) {
data &= ~IGP02E1000_PM_D3_LPLU;
ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); if (ret_val) return ret_val; /* LPLU and SmartSpeed are mutually exclusive. LPLU is used * during Dx states where the power conservation is most * important. During driver activity we should enable * SmartSpeed, so performance is maintained.
*/ if (phy->smart_speed == e1000_smart_speed_on) {
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
&data); if (ret_val) return ret_val;
data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
data); if (ret_val) return ret_val;
} elseif (phy->smart_speed == e1000_smart_speed_off) {
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
&data); if (ret_val) return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
data); if (ret_val) return ret_val;
}
} elseif ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
(phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
(phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
data |= IGP02E1000_PM_D3_LPLU;
ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); if (ret_val) return ret_val;
/* When LPLU is enabled, we should disable SmartSpeed */
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); if (ret_val) return ret_val;
data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
}
return ret_val;
}
/** * e1000e_check_downshift - Checks whether a downshift in speed occurred * @hw: pointer to the HW structure * * Success returns 0, Failure returns 1 * * A downshift is detected by querying the PHY link health.
**/
s32 e1000e_check_downshift(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_data, offset, mask;
switch (phy->type) { case e1000_phy_m88: case e1000_phy_gg82563: case e1000_phy_bm: case e1000_phy_82578:
offset = M88E1000_PHY_SPEC_STATUS;
mask = M88E1000_PSSR_DOWNSHIFT; break; case e1000_phy_igp_2: case e1000_phy_igp_3:
offset = IGP01E1000_PHY_LINK_HEALTH;
mask = IGP01E1000_PLHR_SS_DOWNGRADE; break; default: /* speed downshift not supported */
phy->speed_downgraded = false; return 0;
}
ret_val = e1e_rphy(hw, offset, &phy_data);
if (!ret_val)
phy->speed_downgraded = !!(phy_data & mask);
return ret_val;
}
/** * e1000_check_polarity_m88 - Checks the polarity. * @hw: pointer to the HW structure * * Success returns 0, Failure returns -E1000_ERR_PHY (-2) * * Polarity is determined based on the PHY specific status register.
**/
s32 e1000_check_polarity_m88(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 data;
/** * e1000_check_polarity_igp - Checks the polarity. * @hw: pointer to the HW structure * * Success returns 0, Failure returns -E1000_ERR_PHY (-2) * * Polarity is determined based on the PHY port status register, and the * current speed (since there is no polarity at 100Mbps).
**/
s32 e1000_check_polarity_igp(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 data, offset, mask;
/* Polarity is determined based on the speed of * our connection.
*/
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); if (ret_val) return ret_val;
if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
IGP01E1000_PSSR_SPEED_1000MBPS) {
offset = IGP01E1000_PHY_PCS_INIT_REG;
mask = IGP01E1000_PHY_POLARITY_MASK;
} else { /* This really only applies to 10Mbps since * there is no polarity for 100Mbps (always 0).
*/
offset = IGP01E1000_PHY_PORT_STATUS;
mask = IGP01E1000_PSSR_POLARITY_REVERSED;
}
/** * e1000_wait_autoneg - Wait for auto-neg completion * @hw: pointer to the HW structure * * Waits for auto-negotiation to complete or for the auto-negotiation time * limit to expire, which ever happens first.
**/ static s32 e1000_wait_autoneg(struct e1000_hw *hw)
{
s32 ret_val = 0;
u16 i, phy_status;
/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); if (ret_val) break;
ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); if (ret_val) break; if (phy_status & BMSR_ANEGCOMPLETE) break;
msleep(100);
}
/** * e1000e_phy_has_link_generic - Polls PHY for link * @hw: pointer to the HW structure * @iterations: number of times to poll for link * @usec_interval: delay between polling attempts * @success: pointer to whether polling was successful or not * * Polls the PHY status register for link, 'iterations' number of times.
**/
s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
u32 usec_interval, bool *success)
{
s32 ret_val = 0;
u16 i, phy_status;
*success = false; for (i = 0; i < iterations; i++) { /* Some PHYs require the MII_BMSR register to be read * twice due to the link bit being sticky. No harm doing * it across the board.
*/
ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); if (ret_val) { /* If the first read fails, another entity may have * ownership of the resources, wait and try again to * see if they have relinquished the resources yet.
*/ if (usec_interval >= 1000)
msleep(usec_interval / 1000); else
udelay(usec_interval);
}
ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); if (ret_val) break; if (phy_status & BMSR_LSTATUS) {
*success = true; break;
} if (usec_interval >= 1000)
msleep(usec_interval / 1000); else
udelay(usec_interval);
}
return ret_val;
}
/** * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY * @hw: pointer to the HW structure * * Reads the PHY specific status register to retrieve the cable length * information. The cable length is determined by averaging the minimum and * maximum values to get the "average" cable length. The m88 PHY has four * possible cable length values, which are: * Register Value Cable Length * 0 < 50 meters * 1 50 - 80 meters * 2 80 - 110 meters * 3 110 - 140 meters * 4 > 140 meters
**/
s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_data, index;
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); if (ret_val) return ret_val;
index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);
if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) return -E1000_ERR_PHY;
/** * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY * @hw: pointer to the HW structure * * The automatic gain control (agc) normalizes the amplitude of the * received signal, adjusting for the attenuation produced by the * cable. By reading the AGC registers, which represent the * combination of coarse and fine gain value, the value can be put * into a lookup table to obtain the approximate cable length * for each channel.
**/
s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_data, i, agc_value = 0;
u16 cur_agc_index, max_agc_index = 0;
u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; staticconst u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
IGP02E1000_PHY_AGC_A,
IGP02E1000_PHY_AGC_B,
IGP02E1000_PHY_AGC_C,
IGP02E1000_PHY_AGC_D
};
/* Read the AGC registers for all channels */ for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); if (ret_val) return ret_val;
/* Getting bits 15:9, which represent the combination of * coarse and fine gain values. The result is a number * that can be put into the lookup table to obtain the * approximate cable length.
*/
cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
IGP02E1000_AGC_LENGTH_MASK);
/* Array index bound check. */ if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
(cur_agc_index == 0)) return -E1000_ERR_PHY;
/* Remove min & max AGC values from calculation. */ if (e1000_igp_2_cable_length_table[min_agc_index] >
e1000_igp_2_cable_length_table[cur_agc_index])
min_agc_index = cur_agc_index; if (e1000_igp_2_cable_length_table[max_agc_index] <
e1000_igp_2_cable_length_table[cur_agc_index])
max_agc_index = cur_agc_index;
/** * e1000e_get_phy_info_m88 - Retrieve PHY information * @hw: pointer to the HW structure * * Valid for only copper links. Read the PHY status register (sticky read) * to verify that link is up. Read the PHY special control register to * determine the polarity and 10base-T extended distance. Read the PHY * special status register to determine MDI/MDIx and current speed. If * speed is 1000, then determine cable length, local and remote receiver.
**/
s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 phy_data; bool link;
if (phy->media_type != e1000_media_type_copper) {
e_dbg("Phy info is only valid for copper media\n"); return -E1000_ERR_CONFIG;
}
ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); if (ret_val) return ret_val;
if (!link) {
e_dbg("Phy info is only valid if link is up\n"); return -E1000_ERR_CONFIG;
}
ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val;
/** * e1000e_get_phy_info_igp - Retrieve igp PHY information * @hw: pointer to the HW structure * * Read PHY status to determine if link is up. If link is up, then * set/determine 10base-T extended distance and polarity correction. Read * PHY port status to determine MDI/MDIx and speed. Based on the speed, * determine on the cable length, local and remote receiver.
**/
s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u16 data; bool link;
ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); if (ret_val) return ret_val;
if (!link) {
e_dbg("Phy info is only valid if link is up\n"); return -E1000_ERR_CONFIG;
}
phy->polarity_correction = true;
ret_val = e1000_check_polarity_igp(hw); if (ret_val) return ret_val;
ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); if (ret_val) return ret_val;
phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
IGP01E1000_PSSR_SPEED_1000MBPS) {
ret_val = phy->ops.get_cable_length(hw); if (ret_val) return ret_val;
ret_val = e1e_rphy(hw, MII_STAT1000, &data); if (ret_val) return ret_val;
if (phy->polarity_correction) {
ret_val = e1000_check_polarity_ife(hw); if (ret_val) return ret_val;
} else { /* Polarity is forced */
phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
? e1000_rev_polarity_reversed
: e1000_rev_polarity_normal);
}
ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); if (ret_val) return ret_val;
phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
/* The following parameters are undefined for 10/100 operation. */
phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
phy->local_rx = e1000_1000t_rx_status_undefined;
phy->remote_rx = e1000_1000t_rx_status_undefined;
return 0;
}
/** * e1000e_phy_sw_reset - PHY software reset * @hw: pointer to the HW structure * * Does a software reset of the PHY by reading the PHY control register and * setting/write the control register reset bit to the PHY.
**/
s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
{
s32 ret_val;
u16 phy_ctrl;
ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); if (ret_val) return ret_val;
/** * e1000e_phy_hw_reset_generic - PHY hardware reset * @hw: pointer to the HW structure * * Verify the reset block is not blocking us from resetting. Acquire * semaphore (if necessary) and read/set/write the device control reset * bit in the PHY. Wait the appropriate delay time for the device to * reset and release the semaphore (if necessary).
**/
s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
{ struct e1000_phy_info *phy = &hw->phy;
s32 ret_val;
u32 ctrl;
if (phy->ops.check_reset_block) {
ret_val = phy->ops.check_reset_block(hw); if (ret_val) return 0;
}
ret_val = phy->ops.acquire(hw); if (ret_val) return ret_val;
/** * e1000e_get_cfg_done_generic - Generic configuration done * @hw: pointer to the HW structure * * Generic function to wait 10 milli-seconds for configuration to complete * and return success.
**/
s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
{
mdelay(10);
return 0;
}
/** * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY * @hw: pointer to the HW structure * * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
**/
s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
{
e_dbg("Running IGP 3 PHY init script\n");
/* PHY init IGP 3 */ /* Enable rise/fall, 10-mode work in class-A */
e1e_wphy(hw, 0x2F5B, 0x9018); /* Remove all caps from Replica path filter */
e1e_wphy(hw, 0x2F52, 0x0000); /* Bias trimming for ADC, AFE and Driver (Default) */
e1e_wphy(hw, 0x2FB1, 0x8B24); /* Increase Hybrid poly bias */
e1e_wphy(hw, 0x2FB2, 0xF8F0); /* Add 4% to Tx amplitude in Gig mode */
e1e_wphy(hw, 0x2010, 0x10B0); /* Disable trimming (TTT) */
e1e_wphy(hw, 0x2011, 0x0000); /* Poly DC correction to 94.6% + 2% for all channels */
e1e_wphy(hw, 0x20DD, 0x249A); /* ABS DC correction to 95.9% */
e1e_wphy(hw, 0x20DE, 0x00D3); /* BG temp curve trim */
e1e_wphy(hw, 0x28B4, 0x04CE); /* Increasing ADC OPAMP stage 1 currents to max */
e1e_wphy(hw, 0x2F70, 0x29E4); /* Force 1000 ( required for enabling PHY regs configuration) */
e1e_wphy(hw, 0x0000, 0x0140); /* Set upd_freq to 6 */
e1e_wphy(hw, 0x1F30, 0x1606); /* Disable NPDFE */
e1e_wphy(hw, 0x1F31, 0xB814); /* Disable adaptive fixed FFE (Default) */
e1e_wphy(hw, 0x1F35, 0x002A); /* Enable FFE hysteresis */
e1e_wphy(hw, 0x1F3E, 0x0067); /* Fixed FFE for short cable lengths */
e1e_wphy(hw, 0x1F54, 0x0065); /* Fixed FFE for medium cable lengths */
e1e_wphy(hw, 0x1F55, 0x002A); /* Fixed FFE for long cable lengths */
e1e_wphy(hw, 0x1F56, 0x002A); /* Enable Adaptive Clip Threshold */
e1e_wphy(hw, 0x1F72, 0x3FB0); /* AHT reset limit to 1 */
e1e_wphy(hw, 0x1F76, 0xC0FF); /* Set AHT master delay to 127 msec */
e1e_wphy(hw, 0x1F77, 0x1DEC); /* Set scan bits for AHT */
e1e_wphy(hw, 0x1F78, 0xF9EF); /* Set AHT Preset bits */
e1e_wphy(hw, 0x1F79, 0x0210); /* Change integ_factor of channel A to 3 */
e1e_wphy(hw, 0x1895, 0x0003); /* Change prop_factor of channels BCD to 8 */
e1e_wphy(hw, 0x1796, 0x0008); /* Change cg_icount + enable integbp for channels BCD */
e1e_wphy(hw, 0x1798, 0xD008); /* Change cg_icount + enable integbp + change prop_factor_master * to 8 for channel A
*/
e1e_wphy(hw, 0x1898, 0xD918); /* Disable AHT in Slave mode on channel A */
e1e_wphy(hw, 0x187A, 0x0800); /* Enable LPLU and disable AN to 1000 in non-D0a states, * Enable SPD+B2B
*/
e1e_wphy(hw, 0x0019, 0x008D); /* Enable restart AN on an1000_dis change */
e1e_wphy(hw, 0x001B, 0x2080); /* Enable wh_fifo read clock in 10/100 modes */
e1e_wphy(hw, 0x0014, 0x0045); /* Restart AN, Speed selection is 1000 */
e1e_wphy(hw, 0x0000, 0x1340);
return 0;
}
/** * e1000e_get_phy_type_from_id - Get PHY type from id * @phy_id: phy_id read from the phy * * Returns the phy type from the id.
**/ enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
{ enum e1000_phy_type phy_type = e1000_phy_unknown;
switch (phy_id) { case M88E1000_I_PHY_ID: case M88E1000_E_PHY_ID: case M88E1111_I_PHY_ID: case M88E1011_I_PHY_ID:
phy_type = e1000_phy_m88; break; case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
phy_type = e1000_phy_igp_2; break; case GG82563_E_PHY_ID:
phy_type = e1000_phy_gg82563; break; case IGP03E1000_E_PHY_ID:
phy_type = e1000_phy_igp_3; break; case IFE_E_PHY_ID: case IFE_PLUS_E_PHY_ID: case IFE_C_E_PHY_ID:
phy_type = e1000_phy_ife; break; case BME1000_E_PHY_ID: case BME1000_E_PHY_ID_R2:
phy_type = e1000_phy_bm; break; case I82578_E_PHY_ID:
phy_type = e1000_phy_82578; break; case I82577_E_PHY_ID:
phy_type = e1000_phy_82577; break; case I82579_E_PHY_ID:
phy_type = e1000_phy_82579; break; case I217_E_PHY_ID:
phy_type = e1000_phy_i217; break; default:
phy_type = e1000_phy_unknown; break;
} return phy_type;
}
/** * e1000e_determine_phy_address - Determines PHY address. * @hw: pointer to the HW structure * * This uses a trial and error method to loop through possible PHY * addresses. It tests each by reading the PHY ID registers and * checking for a match.
**/
s32 e1000e_determine_phy_address(struct e1000_hw *hw)
{
u32 phy_addr = 0;
u32 i; enum e1000_phy_type phy_type = e1000_phy_unknown;
hw->phy.id = phy_type;
for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
hw->phy.addr = phy_addr;
i = 0;
do {
e1000e_get_phy_id(hw);
phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
/* If phy_type is valid, break - we found our * PHY address
*/ if (phy_type != e1000_phy_unknown) return 0;
usleep_range(1000, 2000);
i++;
} while (i < 10);
}
return -E1000_ERR_PHY_TYPE;
}
/** * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address * @page: page to access * @reg: register to check * * Returns the phy address for the page requested.
**/ static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
{
u32 phy_addr = 2;
/** * e1000e_write_phy_reg_bm - Write BM PHY register * @hw: pointer to the HW structure * @offset: register offset to write to * @data: data to write at register offset * * Acquires semaphore, if necessary, then writes the data to PHY register * at the offset. Release any acquired semaphores before exiting.
**/
s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
{
s32 ret_val;
u32 page = offset >> IGP_PAGE_SHIFT;
ret_val = hw->phy.ops.acquire(hw); if (ret_val) return ret_val;
/* Page 800 works differently than the rest so it has its own func */ if (page == BM_WUC_PAGE) {
ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, false, false); goto release;
}
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