/* cmd_addr is used for some special command: * 1. to be sector address, when implemented erase sector command * 2. to be flash address when implemented read, write flash address
*/ staticint wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr)
{
u32 cmd_val = 0, val = 0;
void wx_control_hw(struct wx *wx, bool drv)
{ /* True : Let firmware know the driver has taken over * False : Let firmware take over control of hw
*/
wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD,
drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0);
}
EXPORT_SYMBOL(wx_control_hw);
/** * wx_mng_present - returns 0 when management capability is present * @wx: pointer to hardware structure
*/ int wx_mng_present(struct wx *wx)
{
u32 fwsm;
/* Software lock to be held while software semaphore is being accessed. */ static DEFINE_MUTEX(wx_sw_sync_lock);
/** * wx_release_sw_sync - Release SW semaphore * @wx: pointer to hardware structure * @mask: Mask to specify which semaphore to release * * Releases the SW semaphore for the specified * function (CSR, PHY0, PHY1, EEPROM, Flash)
**/ staticvoid wx_release_sw_sync(struct wx *wx, u32 mask)
{
mutex_lock(&wx_sw_sync_lock);
wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0);
mutex_unlock(&wx_sw_sync_lock);
}
/** * wx_acquire_sw_sync - Acquire SW semaphore * @wx: pointer to hardware structure * @mask: Mask to specify which semaphore to acquire * * Acquires the SW semaphore for the specified * function (CSR, PHY0, PHY1, EEPROM, Flash)
**/ staticint wx_acquire_sw_sync(struct wx *wx, u32 mask)
{
u32 sem = 0; int ret = 0;
mutex_lock(&wx_sw_sync_lock);
ret = read_poll_timeout(rd32, sem, !(sem & mask),
5000, 2000000, false, wx, WX_MNG_SWFW_SYNC); if (!ret) {
sem |= mask;
wr32(wx, WX_MNG_SWFW_SYNC, sem);
} else {
wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem);
}
mutex_unlock(&wx_sw_sync_lock);
status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); if (status != 0) return status;
dword_len = length >> 2;
/* The device driver writes the relevant command block * into the ram area.
*/ for (i = 0; i < dword_len; i++) {
wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); /* write flush */
buf[i] = rd32a(wx, WX_MNG_MBOX, i);
} /* Setting this bit tells the ARC that a new command is pending. */
wr32m(wx, WX_MNG_MBOX_CTL,
WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY);
/* first pull in the header so we know the buffer length */ for (bi = 0; bi < dword_len; bi++) {
buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi);
le32_to_cpus(&buffer[bi]);
}
/* If there is any thing in data position pull it in */
buf_len = ((struct wx_hic_hdr *)buffer)->buf_len; if (buf_len == 0) goto rel_out;
if (length < buf_len + hdr_size) {
wx_err(wx, "Buffer not large enough for reply message.\n");
status = -EFAULT; goto rel_out;
}
/* Calculate length in DWORDs, add 3 for odd lengths */
dword_len = (buf_len + 3) >> 2;
/* Pull in the rest of the buffer (bi is where we left off) */ for (; bi <= dword_len; bi++) {
buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi);
le32_to_cpus(&buffer[bi]);
}
/** * wx_host_interface_command - Issue command to manageability block * @wx: pointer to the HW structure * @buffer: contains the command to write and where the return status will * be placed * @length: length of buffer, must be multiple of 4 bytes * @timeout: time in ms to wait for command completion * @return_data: read and return data from the buffer (true) or not (false) * Needed because FW structures are big endian and decoding of * these fields can be 8 bit or 16 bit based on command. Decoding * is not easily understood without making a table of commands. * So we will leave this up to the caller to read back the data * in these cases.
**/ int wx_host_interface_command(struct wx *wx, u32 *buffer,
u32 length, u32 timeout, bool return_data)
{ if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) {
wx_err(wx, "Buffer length failure buffersize=%d.\n", length); return -EINVAL;
}
/* Calculate length in DWORDs. We must be DWORD aligned */ if ((length % (sizeof(u32))) != 0) {
wx_err(wx, "Buffer length failure, not aligned to dword"); return -EINVAL;
}
if (test_bit(WX_FLAG_SWFW_RING, wx->flags)) return wx_host_interface_command_r(wx, buffer, length,
timeout, return_data);
/** * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd * assuming that the semaphore is already obtained. * @wx: pointer to hardware structure * @offset: offset of word in the EEPROM to read * @data: word read from the EEPROM * * Reads a 16 bit word from the EEPROM using the hostif.
**/ staticint wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data)
{ struct wx_hic_read_shadow_ram buffer; int status;
/* convert offset from words to bytes */
buffer.address = (__force u32)cpu_to_be32(offset * 2); /* one word */
buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer),
WX_HI_COMMAND_TIMEOUT, false);
/** * wx_read_ee_hostif - Read EEPROM word using a host interface cmd * @wx: pointer to hardware structure * @offset: offset of word in the EEPROM to read * @data: word read from the EEPROM * * Reads a 16 bit word from the EEPROM using the hostif.
**/ int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data)
{ int status = 0;
status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); if (status == 0) {
status = wx_read_ee_hostif_data(wx, offset, data);
wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH);
}
/** * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif * @wx: pointer to hardware structure * @offset: offset of word in the EEPROM to read * @words: number of words * @data: word(s) read from the EEPROM * * Reads a 16 bit word(s) from the EEPROM using the hostif.
**/ int wx_read_ee_hostif_buffer(struct wx *wx,
u16 offset, u16 words, u16 *data)
{ struct wx_hic_read_shadow_ram buffer;
u32 current_word = 0;
u16 words_to_read;
u32 value = 0; int status;
u32 mbox;
u32 i;
/* Take semaphore for the entire operation. */
status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); if (status != 0) return status;
while (words) { if (words > FW_MAX_READ_BUFFER_SIZE / 2)
words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; else
words_to_read = words;
/** * wx_init_eeprom_params - Initialize EEPROM params * @wx: pointer to hardware structure * * Initializes the EEPROM parameters wx_eeprom_info within the * wx_hw struct in order to set up EEPROM access.
**/ void wx_init_eeprom_params(struct wx *wx)
{ struct wx_eeprom_info *eeprom = &wx->eeprom;
u16 eeprom_size;
u16 data = 0x80;
switch (wx->mac.type) { case wx_mac_sp: case wx_mac_aml: case wx_mac_aml40: if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) {
wx_err(wx, "NVM Read Error\n"); return;
}
data = data >> 1; break; default: break;
}
/** * wx_get_mac_addr - Generic get MAC address * @wx: pointer to hardware structure * @mac_addr: Adapter MAC address * * Reads the adapter's MAC address from first Receive Address Register (RAR0) * A reset of the adapter must be performed prior to calling this function * in order for the MAC address to have been loaded from the EEPROM into RAR0
**/ void wx_get_mac_addr(struct wx *wx, u8 *mac_addr)
{
u32 rar_high;
u32 rar_low;
u16 i;
for (i = 0; i < 2; i++)
mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
for (i = 0; i < 4; i++)
mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
}
EXPORT_SYMBOL(wx_get_mac_addr);
/** * wx_set_rar - Set Rx address register * @wx: pointer to hardware structure * @index: Receive address register to write * @addr: Address to put into receive address register * @pools: VMDq "set" or "pool" index * @enable_addr: set flag that address is active * * Puts an ethernet address into a receive address register.
**/ staticint wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools,
u32 enable_addr)
{
u32 rar_entries = wx->mac.num_rar_entries;
u32 rar_low, rar_high;
/* Make sure we are using a valid rar index range */ if (index >= rar_entries) {
wx_err(wx, "RAR index %d is out of range.\n", index); return -EINVAL;
}
/* select the MAC address */
wr32(wx, WX_PSR_MAC_SWC_IDX, index);
if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags))
wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32);
/* HW expects these in little endian so we reverse the byte * order from network order (big endian) to little endian * * Some parts put the VMDq setting in the extra RAH bits, * so save everything except the lower 16 bits that hold part * of the address and the address valid bit.
*/
rar_low = ((u32)addr[5] |
((u32)addr[4] << 8) |
((u32)addr[3] << 16) |
((u32)addr[2] << 24));
rar_high = ((u32)addr[1] |
((u32)addr[0] << 8)); if (enable_addr != 0)
rar_high |= WX_PSR_MAC_SWC_AD_H_AV;
/** * wx_clear_rar - Remove Rx address register * @wx: pointer to hardware structure * @index: Receive address register to write * * Clears an ethernet address from a receive address register.
**/ staticint wx_clear_rar(struct wx *wx, u32 index)
{
u32 rar_entries = wx->mac.num_rar_entries;
/* Make sure we are using a valid rar index range */ if (index >= rar_entries) {
wx_err(wx, "RAR index %d is out of range.\n", index); return -EINVAL;
}
/* Some parts put the VMDq setting in the extra RAH bits, * so save everything except the lower 16 bits that hold part * of the address and the address valid bit.
*/
wr32(wx, WX_PSR_MAC_SWC_IDX, index);
/** * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address * @wx: pointer to hardware struct * @rar: receive address register index to disassociate * @vmdq: VMDq pool index to remove from the rar
**/ staticint wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq)
{
u32 rar_entries = wx->mac.num_rar_entries;
u32 mpsar_lo, mpsar_hi;
/* Make sure we are using a valid rar index range */ if (rar >= rar_entries) {
wx_err(wx, "RAR index %d is out of range.\n", rar); return -EINVAL;
}
/* was that the last pool using this rar? */ if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
wx_clear_rar(wx, rar);
return 0;
}
/** * wx_init_uta_tables - Initialize the Unicast Table Array * @wx: pointer to hardware structure
**/ staticvoid wx_init_uta_tables(struct wx *wx)
{ int i;
wx_dbg(wx, " Clearing UTA\n");
for (i = 0; i < 128; i++)
wr32(wx, WX_PSR_UC_TBL(i), 0);
}
/** * wx_init_rx_addrs - Initializes receive address filters. * @wx: pointer to hardware structure * * Places the MAC address in receive address register 0 and clears the rest * of the receive address registers. Clears the multicast table. Assumes * the receiver is in reset when the routine is called.
**/ void wx_init_rx_addrs(struct wx *wx)
{
u32 rar_entries = wx->mac.num_rar_entries;
u32 psrctl; int i;
/* If the current mac address is valid, assume it is a software override * to the permanent address. * Otherwise, use the permanent address from the eeprom.
*/ if (!is_valid_ether_addr(wx->mac.addr)) { /* Get the MAC address from the RAR0 for later reference */
wx_get_mac_addr(wx, wx->mac.addr);
wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr);
} else { /* Setup the receive address. */
wx_dbg(wx, "Overriding MAC Address in RAR[0]\n");
wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr);
if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { /* clear VMDq pool/queue selection for RAR 0 */
wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL);
}
}
/* Zero out the other receive addresses. */
wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1); for (i = 1; i < rar_entries; i++) {
wr32(wx, WX_PSR_MAC_SWC_IDX, i);
wr32(wx, WX_PSR_MAC_SWC_AD_L, 0);
wr32(wx, WX_PSR_MAC_SWC_AD_H, 0);
}
/* Clear the MTA */
wx->addr_ctrl.mta_in_use = 0;
psrctl = rd32(wx, WX_PSR_CTL);
psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE);
psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT;
wr32(wx, WX_PSR_CTL, psrctl);
wx_dbg(wx, " Clearing MTA\n"); for (i = 0; i < wx->mac.mcft_size; i++)
wr32(wx, WX_PSR_MC_TBL(i), 0);
/* search table for addr, if found, set to 0 and sync */ for (i = 0; i < wx->mac.num_rar_entries; i++) { if (!ether_addr_equal(addr, wx->mac_table[i].addr)) continue;
staticint wx_available_rars(struct wx *wx)
{
u32 i, count = 0;
for (i = 0; i < wx->mac.num_rar_entries; i++) { if (wx->mac_table[i].state == 0)
count++;
}
return count;
}
/** * wx_write_uc_addr_list - write unicast addresses to RAR table * @netdev: network interface device structure * @pool: index for mac table * * Writes unicast address list to the RAR table. * Returns: -ENOMEM on failure/insufficient address space * 0 on no addresses written * X on writing X addresses to the RAR table
**/ staticint wx_write_uc_addr_list(struct net_device *netdev, int pool)
{ struct wx *wx = netdev_priv(netdev); int count = 0;
/* return ENOMEM indicating insufficient memory for addresses */ if (netdev_uc_count(netdev) > wx_available_rars(wx)) return -ENOMEM;
if (!netdev_uc_empty(netdev)) { struct netdev_hw_addr *ha;
/** * wx_mta_vector - Determines bit-vector in multicast table to set * @wx: pointer to private structure * @mc_addr: the multicast address * * Extracts the 12 bits, from a multicast address, to determine which * bit-vector to set in the multicast table. The hardware uses 12 bits, from * incoming rx multicast addresses, to determine the bit-vector to check in * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set * by the MO field of the MCSTCTRL. The MO field is set during initialization * to mc_filter_type.
**/
u32 wx_mta_vector(struct wx *wx, u8 *mc_addr)
{
u32 vector = 0;
switch (wx->mac.mc_filter_type) { case 0: /* use bits [47:36] of the address */
vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); break; case 1: /* use bits [46:35] of the address */
vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); break; case 2: /* use bits [45:34] of the address */
vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); break; case 3: /* use bits [43:32] of the address */
vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); break; default: /* Invalid mc_filter_type */
wx_err(wx, "MC filter type param set incorrectly\n"); break;
}
/* vector can only be 12-bits or boundary will be exceeded */
vector &= 0xFFF; return vector;
}
/** * wx_set_mta - Set bit-vector in multicast table * @wx: pointer to private structure * @mc_addr: Multicast address * * Sets the bit-vector in the multicast table.
**/ staticvoid wx_set_mta(struct wx *wx, u8 *mc_addr)
{
u32 vector, vector_bit, vector_reg;
/* The MTA is a register array of 128 32-bit registers. It is treated * like an array of 4096 bits. We want to set bit * BitArray[vector_value]. So we figure out what register the bit is * in, read it, OR in the new bit, then write back the new value. The * register is determined by the upper 7 bits of the vector value and * the bit within that register are determined by the lower 5 bits of * the value.
*/
vector_reg = (vector >> 5) & 0x7F;
vector_bit = vector & 0x1F;
wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
}
/** * wx_update_mc_addr_list - Updates MAC list of multicast addresses * @wx: pointer to private structure * @netdev: pointer to net device structure * * The given list replaces any existing list. Clears the MC addrs from receive * address registers and the multicast table. Uses unused receive address * registers for the first multicast addresses, and hashes the rest into the * multicast table.
**/ staticvoid wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev)
{ struct netdev_hw_addr *ha;
u32 i, psrctl;
/* Set the new number of MC addresses that we are being requested to * use.
*/
wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
wx->addr_ctrl.mta_in_use = 0;
/* Restore any VF macvlans */
wx_full_sync_mac_table(wx);
}
/** * wx_write_mc_addr_list - write multicast addresses to MTA * @netdev: network interface device structure * * Writes multicast address list to the MTA hash table. * Returns: 0 on no addresses written * X on writing X addresses to MTA
**/ staticint wx_write_mc_addr_list(struct net_device *netdev)
{ struct wx *wx = netdev_priv(netdev);
if (!netif_running(netdev)) return 0;
wx_update_mc_addr_list(wx, netdev);
if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags))
wx_restore_vf_multicasts(wx);
return netdev_mc_count(netdev);
}
/** * wx_set_mac - Change the Ethernet Address of the NIC * @netdev: network interface device structure * @p: pointer to an address structure * * Returns 0 on success, negative on failure
**/ int wx_set_mac(struct net_device *netdev, void *p)
{ struct wx *wx = netdev_priv(netdev); struct sockaddr *addr = p; int retval;
retval = eth_prepare_mac_addr_change(netdev, addr); if (retval) return retval;
/* Only support an equally distributed Tx packet buffer strategy. */
txpktsize = wx->mac.tx_pb_size;
txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX;
wr32(wx, WX_TDB_PB_SZ(0), txpktsize);
wr32(wx, WX_TDM_PB_THRE(0), txpbthresh);
}
#define WX_ETH_FRAMING 20
/** * wx_hpbthresh - calculate high water mark for flow control * * @wx: board private structure to calculate for
**/ staticint wx_hpbthresh(struct wx *wx)
{ struct net_device *dev = wx->netdev; int link, tc, kb, marker;
u32 dv_id, rx_pba;
/* Calculate max LAN frame size */
link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + WX_ETH_FRAMING;
tc = link;
/* Calculate delay value for device */
dv_id = WX_DV(link, tc);
/* Delay value is calculated in bit times convert to KB */
kb = WX_BT2KB(dv_id);
rx_pba = rd32(wx, WX_RDB_PB_SZ(0)) >> WX_RDB_PB_SZ_SHIFT;
marker = rx_pba - kb;
/* It is possible that the packet buffer is not large enough * to provide required headroom. In this case throw an error * to user and a do the best we can.
*/ if (marker < 0) {
dev_warn(&wx->pdev->dev, "Packet Buffer can not provide enough headroom to support flow control. Decrease MTU or number of traffic classes\n");
marker = tc + 1;
}
return marker;
}
/** * wx_lpbthresh - calculate low water mark for flow control * * @wx: board private structure to calculate for
**/ staticint wx_lpbthresh(struct wx *wx)
{ struct net_device *dev = wx->netdev;
u32 dv_id; int tc;
/* Calculate max LAN frame size */
tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
/* Calculate delay value for device */
dv_id = WX_LOW_DV(tc);
/* Delay value is calculated in bit times convert to KB */ return WX_BT2KB(dv_id);
}
/** * wx_pbthresh_setup - calculate and setup high low water marks * * @wx: board private structure to calculate for
**/ staticvoid wx_pbthresh_setup(struct wx *wx)
{
wx->fc.high_water = wx_hpbthresh(wx);
wx->fc.low_water = wx_lpbthresh(wx);
/* Low water marks must not be larger than high water marks */ if (wx->fc.low_water > wx->fc.high_water)
wx->fc.low_water = 0;
}
/* clear VLAN promisc flag so VFTA will be updated if necessary */
clear_bit(WX_FLAG_VLAN_PROMISC, wx->flags);
for (i = 0; i < wx->num_vfs; i++) { if (!wx->vfinfo[i].spoofchk_enabled)
wx_set_vf_spoofchk(wx->netdev, i, false); /* enable ethertype anti spoofing if hw supports it */
wx_set_ethertype_anti_spoofing(wx, true, i);
}
}
wr32(wx, WX_CFG_TAG_TPID(0),
ETH_P_8021Q | ETH_P_8021AD << 16);
wx->tpid[0] = ETH_P_8021Q;
wx->tpid[1] = ETH_P_8021AD; for (i = 1; i < 4; i++)
wr32(wx, WX_CFG_TAG_TPID(i),
ETH_P_8021Q | ETH_P_8021Q << 16); for (i = 2; i < 8; i++)
wx->tpid[i] = ETH_P_8021Q;
}
/** * wx_disable_sec_rx_path - Stops the receive data path * @wx: pointer to private structure * * Stops the receive data path and waits for the HW to internally empty * the Rx security block
**/ int wx_disable_sec_rx_path(struct wx *wx)
{
u32 secrx;
vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) { /* we need to keep the VLAN filter on in SRIOV */
vlnctrl |= WX_PSR_VLAN_CTL_VFE;
wr32(wx, WX_PSR_VLAN_CTL, vlnctrl);
} else {
vlnctrl &= ~WX_PSR_VLAN_CTL_VFE;
wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); return;
} /* We are already in VLAN promisc, nothing to do */ if (test_bit(WX_FLAG_VLAN_PROMISC, wx->flags)) return; /* Set flag so we don't redo unnecessary work */
set_bit(WX_FLAG_VLAN_PROMISC, wx->flags); /* Add PF to all active pools */ for (i = WX_PSR_VLAN_SWC_ENTRIES; --i;) {
wr32(wx, WX_PSR_VLAN_SWC_IDX, i);
vind = WX_VF_IND_SHIFT(VMDQ_P(0));
reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0));
bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx));
bits |= BIT(vind);
wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits);
} /* Set all bits in the VLAN filter table array */ for (i = 0; i < wx->mac.vft_size; i++)
wr32(wx, WX_PSR_VLAN_TBL(i), U32_MAX);
}
for (i = WX_PSR_VLAN_SWC_ENTRIES; --i;) {
wr32(wx, WX_PSR_VLAN_SWC_IDX, i);
vlvf = rd32(wx, WX_PSR_VLAN_SWC_IDX); /* pull VLAN ID from VLVF */
vid = vlvf & ~WX_PSR_VLAN_SWC_VIEN; if (vlvf & WX_PSR_VLAN_SWC_VIEN) { /* if PF is part of this then continue */ if (test_bit(vid, wx->active_vlans)) continue;
} /* remove PF from the pool */
vind = WX_VF_IND_SHIFT(VMDQ_P(0));
reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0));
bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx));
bits &= ~BIT(vind);
wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits);
} /* extract values from vft_shadow and write back to VFTA */ for (i = 0; i < wx->mac.vft_size; i++) {
vfta = wx->mac.vft_shadow[i];
wr32(wx, WX_PSR_VLAN_TBL(i), vfta);
}
}
/* configure vlan filtering */
vlnctrl = rd32(wx, WX_PSR_VLAN_CTL);
vlnctrl |= WX_PSR_VLAN_CTL_VFE;
wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); /* We are not in VLAN promisc, nothing to do */ if (!test_bit(WX_FLAG_VLAN_PROMISC, wx->flags)) return; /* Set flag so we don't redo unnecessary work */
clear_bit(WX_FLAG_VLAN_PROMISC, wx->flags);
wx_scrub_vfta(wx);
}
/* set all bits that we expect to always be set */
fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE;
vmolr |= WX_PSR_VM_L2CTL_BAM |
WX_PSR_VM_L2CTL_AUPE |
WX_PSR_VM_L2CTL_VACC;
vlnctrl |= WX_PSR_VLAN_CTL_VFE;
wx->addr_ctrl.user_set_promisc = false; if (netdev->flags & IFF_PROMISC) {
wx->addr_ctrl.user_set_promisc = true;
fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE; /* pf don't want packets routing to vf, so clear UPE */
vmolr |= WX_PSR_VM_L2CTL_MPE; if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags) &&
test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags))
vlnctrl |= WX_PSR_VLAN_CTL_VFE;
features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
}
/* Write addresses to available RAR registers, if there is not * sufficient space to store all the addresses then enable * unicast promiscuous mode
*/
count = wx_write_uc_addr_list(netdev, VMDQ_P(0)); if (count < 0) {
vmolr &= ~WX_PSR_VM_L2CTL_ROPE;
vmolr |= WX_PSR_VM_L2CTL_UPE;
}
/* Write addresses to the MTA, if the attempt fails * then we should just turn on promiscuous mode so * that we can at least receive multicast traffic
*/
count = wx_write_mc_addr_list(netdev); if (count < 0) {
vmolr &= ~WX_PSR_VM_L2CTL_ROMPE;
vmolr |= WX_PSR_VM_L2CTL_MPE;
}
max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; /* adjust max frame to be at least the size of a standard frame */ if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
/** * wx_change_mtu - Change the Maximum Transfer Unit * @netdev: network interface device structure * @new_mtu: new value for maximum frame size * * Returns 0 on success, negative on failure
**/ int wx_change_mtu(struct net_device *netdev, int new_mtu)
{ struct wx *wx = netdev_priv(netdev);
/* write value back with RRCFG.EN bit cleared */
wr32m(wx, WX_PX_RR_CFG(reg_idx),
WX_PX_RR_CFG_RR_EN, 0);
/* the hardware may take up to 100us to really disable the rx queue */
ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN),
10, 100, true, wx, WX_PX_RR_CFG(reg_idx));
if (ret == -ETIMEDOUT) { /* Just for information */
wx_err(wx, "RRCFG.EN on Rx queue %d not cleared within the polling period\n",
reg_idx);
}
}
EXPORT_SYMBOL(wx_disable_rx_queue);
if (ret == -ETIMEDOUT) { /* Just for information */
wx_err(wx, "RRCFG.EN on Rx queue %d not set within the polling period\n",
reg_idx);
}
}
EXPORT_SYMBOL(wx_enable_rx_queue);
/** * wx_configure_tx - Configure Transmit Unit after Reset * @wx: pointer to private structure * * Configure the Tx unit of the MAC after a reset.
**/ staticvoid wx_configure_tx(struct wx *wx)
{
u32 i;
/* TDM_CTL.TE must be before Tx queues are enabled */
wr32m(wx, WX_TDM_CTL,
WX_TDM_CTL_TE, WX_TDM_CTL_TE);
/* Setup the HW Tx Head and Tail descriptor pointers */ for (i = 0; i < wx->num_tx_queues; i++)
wx_configure_tx_ring(wx, wx->tx_ring[i]);
/* Fill out the redirection table as follows: * - 8 bit wide entries containing 4 bit RSS index
*/ for (i = 0; i < WX_MAX_RETA_ENTRIES; i++) {
reta |= indir_tbl[i] << (i & 0x3) * 8; if ((i & 3) == 3) {
wr32(wx, WX_RDB_RSSTBL(i >> 2), reta);
reta = 0;
}
}
}
if (wx->rss_enabled)
rss_field |= WX_RDB_RA_CTL_RSS_EN;
wr32(wx, WX_RDB_RA_CTL, rss_field);
}
/** * wx_configure_rx - Configure Receive Unit after Reset * @wx: pointer to private structure * * Configure the Rx unit of the MAC after a reset.
**/ void wx_configure_rx(struct wx *wx)
{ int ret;
u32 i;
/* set_rx_buffer_len must be called before ring initialization */
wx_set_rx_buffer_len(wx);
/* Setup the HW Rx Head and Tail Descriptor Pointers and * the Base and Length of the Rx Descriptor Ring
*/ for (i = 0; i < wx->num_rx_queues; i++)
wx_configure_rx_ring(wx, wx->rx_ring[i]);
/* Enable all receives, disable security engine prior to block traffic */
ret = wx_disable_sec_rx_path(wx); if (ret < 0)
wx_err(wx, "The register status is abnormal, please check device.");
/** * wx_disable_pcie_master - Disable PCI-express master access * @wx: pointer to hardware structure * * Disables PCI-Express master access and verifies there are no pending * requests.
**/ int wx_disable_pcie_master(struct wx *wx)
{ int status = 0;
u32 val;
/* Always set this bit to ensure any future transactions are blocked */
pci_clear_master(wx->pdev);
/* Exit if master requests are blocked */ if (!(rd32(wx, WX_PX_TRANSACTION_PENDING))) return 0;
/* Poll for master request bit to clear */
status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT, false, wx, WX_PX_TRANSACTION_PENDING); if (status < 0)
wx_err(wx, "PCIe transaction pending bit did not clear.\n");
/** * wx_stop_adapter - Generic stop Tx/Rx units * @wx: pointer to hardware structure * * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts, * disables transmit and receive units. The adapter_stopped flag is used by * the shared code and drivers to determine if the adapter is in a stopped * state and should not touch the hardware.
**/ int wx_stop_adapter(struct wx *wx)
{
u16 i;
/* Set the adapter_stopped flag so other driver functions stop touching * the hardware
*/
wx->adapter_stopped = true;
/* Disable the receive unit */
wx_disable_rx(wx);
/* Set interrupt mask to stop interrupts from being generated */
wx_intr_disable(wx, WX_INTR_ALL);
/* Disable the transmit unit. Each queue must be disabled. */ for (i = 0; i < wx->mac.max_tx_queues; i++) {
wr32m(wx, WX_PX_TR_CFG(i),
WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE,
WX_PX_TR_CFG_SWFLSH);
}
/* Disable the receive unit by stopping each queue */ for (i = 0; i < wx->mac.max_rx_queues; i++) {
wr32m(wx, WX_PX_RR_CFG(i),
WX_PX_RR_CFG_RR_EN, 0);
}
/* flush all queues disables */
WX_WRITE_FLUSH(wx);
/* Prevent the PCI-E bus from hanging by disabling PCI-E master * access and verify no pending requests
*/ return wx_disable_pcie_master(wx);
}
EXPORT_SYMBOL(wx_stop_adapter);
/* errata 4: initialize mng flex tbl and wakeup flex tbl*/
wr32(wx, WX_PSR_MNG_FLEX_SEL, 0); for (i = 0; i < 16; i++) {
wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0);
wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0);
wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0);
}
wr32(wx, WX_PSR_LAN_FLEX_SEL, 0); for (i = 0; i < 16; i++) {
wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0);
wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0);
wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0);
}
/* set pause frame dst mac addr */
wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001);
wr32(wx, WX_RDB_PFCMACDAH, 0x0180);
}
EXPORT_SYMBOL(wx_reset_misc);
/** * wx_get_pcie_msix_counts - Gets MSI-X vector count * @wx: pointer to hardware structure * @msix_count: number of MSI interrupts that can be obtained * @max_msix_count: number of MSI interrupts that mac need * * Read PCIe configuration space, and get the MSI-X vector count from * the capabilities table.
**/ int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count)
{ struct pci_dev *pdev = wx->pdev; struct device *dev = &pdev->dev; int pos;
*msix_count = 1;
pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); if (!pos) {
dev_err(dev, "Unable to find MSI-X Capabilities\n"); return -EINVAL;
}
pci_read_config_word(pdev,
pos + PCI_MSIX_FLAGS,
msix_count);
*msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK; /* MSI-X count is zero-based in HW */
*msix_count += 1;
if (*msix_count > max_msix_count)
*msix_count = max_msix_count;
/** * wx_find_vlvf_slot - find the vlanid or the first empty slot * @wx: pointer to hardware structure * @vlan: VLAN id to write to VLAN filter * * return the VLVF index where this VLAN id should be placed *
**/ staticint wx_find_vlvf_slot(struct wx *wx, u32 vlan)
{
u32 bits = 0, first_empty_slot = 0; int regindex;
/* short cut the special case */ if (vlan == 0) return 0;
/* Search for the vlan id in the VLVF entries. Save off the first empty * slot found along the way
*/ for (regindex = 1; regindex < WX_PSR_VLAN_SWC_ENTRIES; regindex++) {
wr32(wx, WX_PSR_VLAN_SWC_IDX, regindex);
bits = rd32(wx, WX_PSR_VLAN_SWC); if (!bits && !(first_empty_slot))
first_empty_slot = regindex; elseif ((bits & 0x0FFF) == vlan) break;
}
if (regindex >= WX_PSR_VLAN_SWC_ENTRIES) { if (first_empty_slot)
regindex = first_empty_slot; else
regindex = -ENOMEM;
}
return regindex;
}
/** * wx_set_vlvf - Set VLAN Pool Filter * @wx: pointer to hardware structure * @vlan: VLAN id to write to VLAN filter * @vind: VMDq output index that maps queue to VLAN id in VFVFB * @vlan_on: boolean flag to turn on/off VLAN in VFVF * @vfta_changed: pointer to boolean flag which indicates whether VFTA * should be changed * * Turn on/off specified bit in VLVF table.
**/ staticint wx_set_vlvf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on, bool *vfta_changed)
{ int vlvf_index;
u32 vt, bits;
/* If VT Mode is set * Either vlan_on * make sure the vlan is in VLVF * set the vind bit in the matching VLVFB * Or !vlan_on * clear the pool bit and possibly the vind
*/
vt = rd32(wx, WX_CFG_PORT_CTL); if (!(vt & WX_CFG_PORT_CTL_NUM_VT_MASK)) return 0;
vlvf_index = wx_find_vlvf_slot(wx, vlan); if (vlvf_index < 0) return vlvf_index;
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--> maximum size reached
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