Quelle  hsi.h   Sprache: C

/* Broadcom NetXtreme-C/E network driver.
 *
 * Copyright (c) 2014-2016 Broadcom Corporation
 * Copyright (c) 2014-2018 Broadcom Limited
 * Copyright (c) 2018-2025 Broadcom Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 *
 * DO NOT MODIFY!!! This file is automatically generated.
 */

#ifndef _BNXT_HSI_H_
#define _BNXT_HSI_H_

/* hwrm_cmd_hdr (size:128b/16B) */
struct hwrm_cmd_hdr {
 __le16 req_type;
 __le16 cmpl_ring;
 __le16 seq_id;
 __le16 target_id;
 __le64 resp_addr;
};

/* hwrm_resp_hdr (size:64b/8B) */
struct hwrm_resp_hdr {
 __le16 error_code;
 __le16 req_type;
 __le16 seq_id;
 __le16 resp_len;
};

#define CMD_DISCR_TLV_ENCAP 0x8000UL
#define CMD_DISCR_LAST     CMD_DISCR_TLV_ENCAP


#define TLV_TYPE_HWRM_REQUEST                    0x1UL
#define TLV_TYPE_HWRM_RESPONSE                   0x2UL
#define TLV_TYPE_ROCE_SP_COMMAND                 0x3UL
#define TLV_TYPE_QUERY_ROCE_CC_GEN1              0x4UL
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1             0x5UL
#define TLV_TYPE_QUERY_ROCE_CC_GEN2              0x6UL
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2             0x7UL
#define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT          0x8UL
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT         0x9UL
#define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT          0xaUL
#define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT         0xbUL
#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
#define TLV_TYPE_ENGINE_CKV_IV                   0x8003UL
#define TLV_TYPE_ENGINE_CKV_AUTH_TAG             0x8004UL
#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT           0x8005UL
#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS      0x8006UL
#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY  0x8007UL
#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE      0x8008UL
#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY    0x8009UL
#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS        0x800aUL
#define TLV_TYPE_LAST                           TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS


/* tlv (size:64b/8B) */
struct tlv {
 __le16 cmd_discr;
 u8 reserved_8b;
 u8 flags;
 #define TLV_FLAGS_MORE         0x1UL
 #define TLV_FLAGS_MORE_LAST      0x0UL
 #define TLV_FLAGS_MORE_NOT_LAST  0x1UL
 #define TLV_FLAGS_REQUIRED     0x2UL
 #define TLV_FLAGS_REQUIRED_NO    (0x0UL << 1)
 #define TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)
 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
 __le16 tlv_type;
 __le16 length;
};

/* input (size:128b/16B) */
struct input {
 __le16 req_type;
 __le16 cmpl_ring;
 __le16 seq_id;
 __le16 target_id;
 __le64 resp_addr;
};

/* output (size:64b/8B) */
struct output {
 __le16 error_code;
 __le16 req_type;
 __le16 seq_id;
 __le16 resp_len;
};

/* hwrm_short_input (size:128b/16B) */
struct hwrm_short_input {
 __le16 req_type;
 __le16 signature;
 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
 #define SHORT_REQ_SIGNATURE_LAST     SHORT_REQ_SIGNATURE_SHORT_CMD
 __le16 target_id;
 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
 #define SHORT_REQ_TARGET_ID_TOOLS   0xfffdUL
 #define SHORT_REQ_TARGET_ID_LAST   SHORT_REQ_TARGET_ID_TOOLS
 __le16 size;
 __le64 req_addr;
};

/* cmd_nums (size:64b/8B) */
struct cmd_nums {
 __le16 req_type;
 #define HWRM_VER_GET                              0x0UL
 #define HWRM_FUNC_ECHO_RESPONSE                   0xbUL
 #define HWRM_ERROR_RECOVERY_QCFG                  0xcUL
 #define HWRM_FUNC_DRV_IF_CHANGE                   0xdUL
 #define HWRM_FUNC_BUF_UNRGTR                      0xeUL
 #define HWRM_FUNC_VF_CFG                          0xfUL
 #define HWRM_RESERVED1                            0x10UL
 #define HWRM_FUNC_RESET                           0x11UL
 #define HWRM_FUNC_GETFID                          0x12UL
 #define HWRM_FUNC_VF_ALLOC                        0x13UL
 #define HWRM_FUNC_VF_FREE                         0x14UL
 #define HWRM_FUNC_QCAPS                           0x15UL
 #define HWRM_FUNC_QCFG                            0x16UL
 #define HWRM_FUNC_CFG                             0x17UL
 #define HWRM_FUNC_QSTATS                          0x18UL
 #define HWRM_FUNC_CLR_STATS                       0x19UL
 #define HWRM_FUNC_DRV_UNRGTR                      0x1aUL
 #define HWRM_FUNC_VF_RESC_FREE                    0x1bUL
 #define HWRM_FUNC_VF_VNIC_IDS_QUERY               0x1cUL
 #define HWRM_FUNC_DRV_RGTR                        0x1dUL
 #define HWRM_FUNC_DRV_QVER                        0x1eUL
 #define HWRM_FUNC_BUF_RGTR                        0x1fUL
 #define HWRM_PORT_PHY_CFG                         0x20UL
 #define HWRM_PORT_MAC_CFG                         0x21UL
 #define HWRM_PORT_TS_QUERY                        0x22UL
 #define HWRM_PORT_QSTATS                          0x23UL
 #define HWRM_PORT_LPBK_QSTATS                     0x24UL
 #define HWRM_PORT_CLR_STATS                       0x25UL
 #define HWRM_PORT_LPBK_CLR_STATS                  0x26UL
 #define HWRM_PORT_PHY_QCFG                        0x27UL
 #define HWRM_PORT_MAC_QCFG                        0x28UL
 #define HWRM_PORT_MAC_PTP_QCFG                    0x29UL
 #define HWRM_PORT_PHY_QCAPS                       0x2aUL
 #define HWRM_PORT_PHY_I2C_WRITE                   0x2bUL
 #define HWRM_PORT_PHY_I2C_READ                    0x2cUL
 #define HWRM_PORT_LED_CFG                         0x2dUL
 #define HWRM_PORT_LED_QCFG                        0x2eUL
 #define HWRM_PORT_LED_QCAPS                       0x2fUL
 #define HWRM_QUEUE_QPORTCFG                       0x30UL
 #define HWRM_QUEUE_QCFG                           0x31UL
 #define HWRM_QUEUE_CFG                            0x32UL
 #define HWRM_FUNC_VLAN_CFG                        0x33UL
 #define HWRM_FUNC_VLAN_QCFG                       0x34UL
 #define HWRM_QUEUE_PFCENABLE_QCFG                 0x35UL
 #define HWRM_QUEUE_PFCENABLE_CFG                  0x36UL
 #define HWRM_QUEUE_PRI2COS_QCFG                   0x37UL
 #define HWRM_QUEUE_PRI2COS_CFG                    0x38UL
 #define HWRM_QUEUE_COS2BW_QCFG                    0x39UL
 #define HWRM_QUEUE_COS2BW_CFG                     0x3aUL
 #define HWRM_QUEUE_DSCP_QCAPS                     0x3bUL
 #define HWRM_QUEUE_DSCP2PRI_QCFG                  0x3cUL
 #define HWRM_QUEUE_DSCP2PRI_CFG                   0x3dUL
 #define HWRM_VNIC_ALLOC                           0x40UL
 #define HWRM_VNIC_FREE                            0x41UL
 #define HWRM_VNIC_CFG                             0x42UL
 #define HWRM_VNIC_QCFG                            0x43UL
 #define HWRM_VNIC_TPA_CFG                         0x44UL
 #define HWRM_VNIC_TPA_QCFG                        0x45UL
 #define HWRM_VNIC_RSS_CFG                         0x46UL
 #define HWRM_VNIC_RSS_QCFG                        0x47UL
 #define HWRM_VNIC_PLCMODES_CFG                    0x48UL
 #define HWRM_VNIC_PLCMODES_QCFG                   0x49UL
 #define HWRM_VNIC_QCAPS                           0x4aUL
 #define HWRM_VNIC_UPDATE                          0x4bUL
 #define HWRM_RING_ALLOC                           0x50UL
 #define HWRM_RING_FREE                            0x51UL
 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        0x52UL
 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS     0x53UL
 #define HWRM_RING_AGGINT_QCAPS                    0x54UL
 #define HWRM_RING_SCHQ_ALLOC                      0x55UL
 #define HWRM_RING_SCHQ_CFG                        0x56UL
 #define HWRM_RING_SCHQ_FREE                       0x57UL
 #define HWRM_RING_RESET                           0x5eUL
 #define HWRM_RING_GRP_ALLOC                       0x60UL
 #define HWRM_RING_GRP_FREE                        0x61UL
 #define HWRM_RING_CFG                             0x62UL
 #define HWRM_RING_QCFG                            0x63UL
 #define HWRM_RESERVED5                            0x64UL
 #define HWRM_RESERVED6                            0x65UL
 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC            0x70UL
 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE             0x71UL
 #define HWRM_QUEUE_MPLS_QCAPS                     0x80UL
 #define HWRM_QUEUE_MPLSTC2PRI_QCFG                0x81UL
 #define HWRM_QUEUE_MPLSTC2PRI_CFG                 0x82UL
 #define HWRM_QUEUE_VLANPRI_QCAPS                  0x83UL
 #define HWRM_QUEUE_VLANPRI2PRI_QCFG               0x84UL
 #define HWRM_QUEUE_VLANPRI2PRI_CFG                0x85UL
 #define HWRM_QUEUE_GLOBAL_CFG                     0x86UL
 #define HWRM_QUEUE_GLOBAL_QCFG                    0x87UL
 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG      0x88UL
 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG       0x89UL
 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG      0x8aUL
 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG       0x8bUL
 #define HWRM_QUEUE_QCAPS                          0x8cUL
 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG       0x8dUL
 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG        0x8eUL
 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG       0x8fUL
 #define HWRM_CFA_L2_FILTER_ALLOC                  0x90UL
 #define HWRM_CFA_L2_FILTER_FREE                   0x91UL
 #define HWRM_CFA_L2_FILTER_CFG                    0x92UL
 #define HWRM_CFA_L2_SET_RX_MASK                   0x93UL
 #define HWRM_CFA_VLAN_ANTISPOOF_CFG               0x94UL
 #define HWRM_CFA_TUNNEL_FILTER_ALLOC              0x95UL
 #define HWRM_CFA_TUNNEL_FILTER_FREE               0x96UL
 #define HWRM_CFA_ENCAP_RECORD_ALLOC               0x97UL
 #define HWRM_CFA_ENCAP_RECORD_FREE                0x98UL
 #define HWRM_CFA_NTUPLE_FILTER_ALLOC              0x99UL
 #define HWRM_CFA_NTUPLE_FILTER_FREE               0x9aUL
 #define HWRM_CFA_NTUPLE_FILTER_CFG                0x9bUL
 #define HWRM_CFA_EM_FLOW_ALLOC                    0x9cUL
 #define HWRM_CFA_EM_FLOW_FREE                     0x9dUL
 #define HWRM_CFA_EM_FLOW_CFG                      0x9eUL
 #define HWRM_TUNNEL_DST_PORT_QUERY                0xa0UL
 #define HWRM_TUNNEL_DST_PORT_ALLOC                0xa1UL
 #define HWRM_TUNNEL_DST_PORT_FREE                 0xa2UL
 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG        0xa3UL
 #define HWRM_STAT_CTX_ENG_QUERY                   0xafUL
 #define HWRM_STAT_CTX_ALLOC                       0xb0UL
 #define HWRM_STAT_CTX_FREE                        0xb1UL
 #define HWRM_STAT_CTX_QUERY                       0xb2UL
 #define HWRM_STAT_CTX_CLR_STATS                   0xb3UL
 #define HWRM_PORT_QSTATS_EXT                      0xb4UL
 #define HWRM_PORT_PHY_MDIO_WRITE                  0xb5UL
 #define HWRM_PORT_PHY_MDIO_READ                   0xb6UL
 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE            0xb7UL
 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE            0xb8UL
 #define HWRM_PORT_QSTATS_EXT_PFC_WD               0xb9UL
 #define HWRM_RESERVED7                            0xbaUL
 #define HWRM_PORT_TX_FIR_CFG                      0xbbUL
 #define HWRM_PORT_TX_FIR_QCFG                     0xbcUL
 #define HWRM_PORT_ECN_QSTATS                      0xbdUL
 #define HWRM_FW_LIVEPATCH_QUERY                   0xbeUL
 #define HWRM_FW_LIVEPATCH                         0xbfUL
 #define HWRM_FW_RESET                             0xc0UL
 #define HWRM_FW_QSTATUS                           0xc1UL
 #define HWRM_FW_HEALTH_CHECK                      0xc2UL
 #define HWRM_FW_SYNC                              0xc3UL
 #define HWRM_FW_STATE_QCAPS                       0xc4UL
 #define HWRM_FW_STATE_QUIESCE                     0xc5UL
 #define HWRM_FW_STATE_BACKUP                      0xc6UL
 #define HWRM_FW_STATE_RESTORE                     0xc7UL
 #define HWRM_FW_SET_TIME                          0xc8UL
 #define HWRM_FW_GET_TIME                          0xc9UL
 #define HWRM_FW_SET_STRUCTURED_DATA               0xcaUL
 #define HWRM_FW_GET_STRUCTURED_DATA               0xcbUL
 #define HWRM_FW_IPC_MAILBOX                       0xccUL
 #define HWRM_FW_ECN_CFG                           0xcdUL
 #define HWRM_FW_ECN_QCFG                          0xceUL
 #define HWRM_FW_SECURE_CFG                        0xcfUL
 #define HWRM_EXEC_FWD_RESP                        0xd0UL
 #define HWRM_REJECT_FWD_RESP                      0xd1UL
 #define HWRM_FWD_RESP                             0xd2UL
 #define HWRM_FWD_ASYNC_EVENT_CMPL                 0xd3UL
 #define HWRM_OEM_CMD                              0xd4UL
 #define HWRM_PORT_PRBS_TEST                       0xd5UL
 #define HWRM_PORT_SFP_SIDEBAND_CFG                0xd6UL
 #define HWRM_PORT_SFP_SIDEBAND_QCFG               0xd7UL
 #define HWRM_FW_STATE_UNQUIESCE                   0xd8UL
 #define HWRM_PORT_DSC_DUMP                        0xd9UL
 #define HWRM_PORT_EP_TX_QCFG                      0xdaUL
 #define HWRM_PORT_EP_TX_CFG                       0xdbUL
 #define HWRM_PORT_CFG                             0xdcUL
 #define HWRM_PORT_QCFG                            0xddUL
 #define HWRM_PORT_MAC_QCAPS                       0xdfUL
 #define HWRM_TEMP_MONITOR_QUERY                   0xe0UL
 #define HWRM_REG_POWER_QUERY                      0xe1UL
 #define HWRM_CORE_FREQUENCY_QUERY                 0xe2UL
 #define HWRM_REG_POWER_HISTOGRAM                  0xe3UL
 #define HWRM_WOL_FILTER_ALLOC                     0xf0UL
 #define HWRM_WOL_FILTER_FREE                      0xf1UL
 #define HWRM_WOL_FILTER_QCFG                      0xf2UL
 #define HWRM_WOL_REASON_QCFG                      0xf3UL
 #define HWRM_CFA_METER_QCAPS                      0xf4UL
 #define HWRM_CFA_METER_PROFILE_ALLOC              0xf5UL
 #define HWRM_CFA_METER_PROFILE_FREE               0xf6UL
 #define HWRM_CFA_METER_PROFILE_CFG                0xf7UL
 #define HWRM_CFA_METER_INSTANCE_ALLOC             0xf8UL
 #define HWRM_CFA_METER_INSTANCE_FREE              0xf9UL
 #define HWRM_CFA_METER_INSTANCE_CFG               0xfaUL
 #define HWRM_CFA_VFR_ALLOC                        0xfdUL
 #define HWRM_CFA_VFR_FREE                         0xfeUL
 #define HWRM_CFA_VF_PAIR_ALLOC                    0x100UL
 #define HWRM_CFA_VF_PAIR_FREE                     0x101UL
 #define HWRM_CFA_VF_PAIR_INFO                     0x102UL
 #define HWRM_CFA_FLOW_ALLOC                       0x103UL
 #define HWRM_CFA_FLOW_FREE                        0x104UL
 #define HWRM_CFA_FLOW_FLUSH                       0x105UL
 #define HWRM_CFA_FLOW_STATS                       0x106UL
 #define HWRM_CFA_FLOW_INFO                        0x107UL
 #define HWRM_CFA_DECAP_FILTER_ALLOC               0x108UL
 #define HWRM_CFA_DECAP_FILTER_FREE                0x109UL
 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG              0x10aUL
 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC       0x10bUL
 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE        0x10cUL
 #define HWRM_CFA_PAIR_ALLOC                       0x10dUL
 #define HWRM_CFA_PAIR_FREE                        0x10eUL
 #define HWRM_CFA_PAIR_INFO                        0x10fUL
 #define HWRM_FW_IPC_MSG                           0x110UL
 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        0x111UL
 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       0x112UL
 #define HWRM_CFA_FLOW_AGING_TIMER_RESET           0x113UL
 #define HWRM_CFA_FLOW_AGING_CFG                   0x114UL
 #define HWRM_CFA_FLOW_AGING_QCFG                  0x115UL
 #define HWRM_CFA_FLOW_AGING_QCAPS                 0x116UL
 #define HWRM_CFA_CTX_MEM_RGTR                     0x117UL
 #define HWRM_CFA_CTX_MEM_UNRGTR                   0x118UL
 #define HWRM_CFA_CTX_MEM_QCTX                     0x119UL
 #define HWRM_CFA_CTX_MEM_QCAPS                    0x11aUL
 #define HWRM_CFA_COUNTER_QCAPS                    0x11bUL
 #define HWRM_CFA_COUNTER_CFG                      0x11cUL
 #define HWRM_CFA_COUNTER_QCFG                     0x11dUL
 #define HWRM_CFA_COUNTER_QSTATS                   0x11eUL
 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG            0x11fUL
 #define HWRM_CFA_EEM_QCAPS                        0x120UL
 #define HWRM_CFA_EEM_CFG                          0x121UL
 #define HWRM_CFA_EEM_QCFG                         0x122UL
 #define HWRM_CFA_EEM_OP                           0x123UL
 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS              0x124UL
 #define HWRM_CFA_TFLIB                            0x125UL
 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR            0x126UL
 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR          0x127UL
 #define HWRM_CFA_TLS_FILTER_ALLOC                 0x128UL
 #define HWRM_CFA_TLS_FILTER_FREE                  0x129UL
 #define HWRM_CFA_RELEASE_AFM_FUNC                 0x12aUL
 #define HWRM_ENGINE_CKV_STATUS                    0x12eUL
 #define HWRM_ENGINE_CKV_CKEK_ADD                  0x12fUL
 #define HWRM_ENGINE_CKV_CKEK_DELETE               0x130UL
 #define HWRM_ENGINE_CKV_KEY_ADD                   0x131UL
 #define HWRM_ENGINE_CKV_KEY_DELETE                0x132UL
 #define HWRM_ENGINE_CKV_FLUSH                     0x133UL
 #define HWRM_ENGINE_CKV_RNG_GET                   0x134UL
 #define HWRM_ENGINE_CKV_KEY_GEN                   0x135UL
 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG             0x136UL
 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG            0x137UL
 #define HWRM_ENGINE_QG_CONFIG_QUERY               0x13cUL
 #define HWRM_ENGINE_QG_QUERY                      0x13dUL
 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY        0x13fUL
 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC        0x140UL
 #define HWRM_ENGINE_QG_METER_PROFILE_FREE         0x141UL
 #define HWRM_ENGINE_QG_METER_QUERY                0x142UL
 #define HWRM_ENGINE_QG_METER_BIND                 0x143UL
 #define HWRM_ENGINE_QG_METER_UNBIND               0x144UL
 #define HWRM_ENGINE_QG_FUNC_BIND                  0x145UL
 #define HWRM_ENGINE_SG_CONFIG_QUERY               0x146UL
 #define HWRM_ENGINE_SG_QUERY                      0x147UL
 #define HWRM_ENGINE_SG_METER_QUERY                0x148UL
 #define HWRM_ENGINE_SG_METER_CONFIG               0x149UL
 #define HWRM_ENGINE_SG_QG_BIND                    0x14aUL
 #define HWRM_ENGINE_QG_SG_UNBIND                  0x14bUL
 #define HWRM_ENGINE_CONFIG_QUERY                  0x154UL
 #define HWRM_ENGINE_STATS_CONFIG                  0x155UL
 #define HWRM_ENGINE_STATS_CLEAR                   0x156UL
 #define HWRM_ENGINE_STATS_QUERY                   0x157UL
 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR  0x158UL
 #define HWRM_ENGINE_RQ_ALLOC                      0x15eUL
 #define HWRM_ENGINE_RQ_FREE                       0x15fUL
 #define HWRM_ENGINE_CQ_ALLOC                      0x160UL
 #define HWRM_ENGINE_CQ_FREE                       0x161UL
 #define HWRM_ENGINE_NQ_ALLOC                      0x162UL
 #define HWRM_ENGINE_NQ_FREE                       0x163UL
 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS            0x164UL
 #define HWRM_ENGINE_FUNC_QCFG                     0x165UL
 #define HWRM_FUNC_RESOURCE_QCAPS                  0x190UL
 #define HWRM_FUNC_VF_RESOURCE_CFG                 0x191UL
 #define HWRM_FUNC_BACKING_STORE_QCAPS             0x192UL
 #define HWRM_FUNC_BACKING_STORE_CFG               0x193UL
 #define HWRM_FUNC_BACKING_STORE_QCFG              0x194UL
 #define HWRM_FUNC_VF_BW_CFG                       0x195UL
 #define HWRM_FUNC_VF_BW_QCFG                      0x196UL
 #define HWRM_FUNC_HOST_PF_IDS_QUERY               0x197UL
 #define HWRM_FUNC_QSTATS_EXT                      0x198UL
 #define HWRM_STAT_EXT_CTX_QUERY                   0x199UL
 #define HWRM_FUNC_SPD_CFG                         0x19aUL
 #define HWRM_FUNC_SPD_QCFG                        0x19bUL
 #define HWRM_FUNC_PTP_PIN_QCFG                    0x19cUL
 #define HWRM_FUNC_PTP_PIN_CFG                     0x19dUL
 #define HWRM_FUNC_PTP_CFG                         0x19eUL
 #define HWRM_FUNC_PTP_TS_QUERY                    0x19fUL
 #define HWRM_FUNC_PTP_EXT_CFG                     0x1a0UL
 #define HWRM_FUNC_PTP_EXT_QCFG                    0x1a1UL
 #define HWRM_FUNC_KEY_CTX_ALLOC                   0x1a2UL
 #define HWRM_FUNC_BACKING_STORE_CFG_V2            0x1a3UL
 #define HWRM_FUNC_BACKING_STORE_QCFG_V2           0x1a4UL
 #define HWRM_FUNC_DBR_PACING_CFG                  0x1a5UL
 #define HWRM_FUNC_DBR_PACING_QCFG                 0x1a6UL
 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT      0x1a7UL
 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2          0x1a8UL
 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY         0x1a9UL
 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED          0x1aaUL
 #define HWRM_FUNC_SYNCE_CFG                       0x1abUL
 #define HWRM_FUNC_SYNCE_QCFG                      0x1acUL
 #define HWRM_FUNC_KEY_CTX_FREE                    0x1adUL
 #define HWRM_FUNC_LAG_MODE_CFG                    0x1aeUL
 #define HWRM_FUNC_LAG_MODE_QCFG                   0x1afUL
 #define HWRM_FUNC_LAG_CREATE                      0x1b0UL
 #define HWRM_FUNC_LAG_UPDATE                      0x1b1UL
 #define HWRM_FUNC_LAG_FREE                        0x1b2UL
 #define HWRM_FUNC_LAG_QCFG                        0x1b3UL
 #define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD         0x1c2UL
 #define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE      0x1c3UL
 #define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY       0x1c4UL
 #define HWRM_SELFTEST_QLIST                       0x200UL
 #define HWRM_SELFTEST_EXEC                        0x201UL
 #define HWRM_SELFTEST_IRQ                         0x202UL
 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA        0x203UL
 #define HWRM_PCIE_QSTATS                          0x204UL
 #define HWRM_MFG_FRU_WRITE_CONTROL                0x205UL
 #define HWRM_MFG_TIMERS_QUERY                     0x206UL
 #define HWRM_MFG_OTP_CFG                          0x207UL
 #define HWRM_MFG_OTP_QCFG                         0x208UL
 #define HWRM_MFG_HDMA_TEST                        0x209UL
 #define HWRM_MFG_FRU_EEPROM_WRITE                 0x20aUL
 #define HWRM_MFG_FRU_EEPROM_READ                  0x20bUL
 #define HWRM_MFG_SOC_IMAGE                        0x20cUL
 #define HWRM_MFG_SOC_QSTATUS                      0x20dUL
 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE     0x20eUL
 #define HWRM_MFG_PARAM_CRITICAL_DATA_READ         0x20fUL
 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH       0x210UL
 #define HWRM_MFG_PRVSN_EXPORT_CSR                 0x211UL
 #define HWRM_MFG_PRVSN_IMPORT_CERT                0x212UL
 #define HWRM_MFG_PRVSN_GET_STATE                  0x213UL
 #define HWRM_MFG_GET_NVM_MEASUREMENT              0x214UL
 #define HWRM_MFG_PSOC_QSTATUS                     0x215UL
 #define HWRM_MFG_SELFTEST_QLIST                   0x216UL
 #define HWRM_MFG_SELFTEST_EXEC                    0x217UL
 #define HWRM_STAT_GENERIC_QSTATS                  0x218UL
 #define HWRM_MFG_PRVSN_EXPORT_CERT                0x219UL
 #define HWRM_STAT_DB_ERROR_QSTATS                 0x21aUL
 #define HWRM_MFG_TESTS                            0x21bUL
 #define HWRM_MFG_WRITE_CERT_NVM                   0x21cUL
 #define HWRM_PORT_POE_CFG                         0x230UL
 #define HWRM_PORT_POE_QCFG                        0x231UL
 #define HWRM_UDCC_QCAPS                           0x258UL
 #define HWRM_UDCC_CFG                             0x259UL
 #define HWRM_UDCC_QCFG                            0x25aUL
 #define HWRM_UDCC_SESSION_CFG                     0x25bUL
 #define HWRM_UDCC_SESSION_QCFG                    0x25cUL
 #define HWRM_UDCC_SESSION_QUERY                   0x25dUL
 #define HWRM_UDCC_COMP_CFG                        0x25eUL
 #define HWRM_UDCC_COMP_QCFG                       0x25fUL
 #define HWRM_UDCC_COMP_QUERY                      0x260UL
 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS            0x261UL
 #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG              0x262UL
 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG             0x263UL
 #define HWRM_TF                                   0x2bcUL
 #define HWRM_TF_VERSION_GET                       0x2bdUL
 #define HWRM_TF_SESSION_OPEN                      0x2c6UL
 #define HWRM_TF_SESSION_REGISTER                  0x2c8UL
 #define HWRM_TF_SESSION_UNREGISTER                0x2c9UL
 #define HWRM_TF_SESSION_CLOSE                     0x2caUL
 #define HWRM_TF_SESSION_QCFG                      0x2cbUL
 #define HWRM_TF_SESSION_RESC_QCAPS                0x2ccUL
 #define HWRM_TF_SESSION_RESC_ALLOC                0x2cdUL
 #define HWRM_TF_SESSION_RESC_FREE                 0x2ceUL
 #define HWRM_TF_SESSION_RESC_FLUSH                0x2cfUL
 #define HWRM_TF_SESSION_RESC_INFO                 0x2d0UL
 #define HWRM_TF_SESSION_HOTUP_STATE_SET           0x2d1UL
 #define HWRM_TF_SESSION_HOTUP_STATE_GET           0x2d2UL
 #define HWRM_TF_TBL_TYPE_GET                      0x2daUL
 #define HWRM_TF_TBL_TYPE_SET                      0x2dbUL
 #define HWRM_TF_TBL_TYPE_BULK_GET                 0x2dcUL
 #define HWRM_TF_EM_INSERT                         0x2eaUL
 #define HWRM_TF_EM_DELETE                         0x2ebUL
 #define HWRM_TF_EM_HASH_INSERT                    0x2ecUL
 #define HWRM_TF_EM_MOVE                           0x2edUL
 #define HWRM_TF_TCAM_SET                          0x2f8UL
 #define HWRM_TF_TCAM_GET                          0x2f9UL
 #define HWRM_TF_TCAM_MOVE                         0x2faUL
 #define HWRM_TF_TCAM_FREE                         0x2fbUL
 #define HWRM_TF_GLOBAL_CFG_SET                    0x2fcUL
 #define HWRM_TF_GLOBAL_CFG_GET                    0x2fdUL
 #define HWRM_TF_IF_TBL_SET                        0x2feUL
 #define HWRM_TF_IF_TBL_GET                        0x2ffUL
 #define HWRM_TF_RESC_USAGE_SET                    0x300UL
 #define HWRM_TF_RESC_USAGE_QUERY                  0x301UL
 #define HWRM_TF_TBL_TYPE_ALLOC                    0x302UL
 #define HWRM_TF_TBL_TYPE_FREE                     0x303UL
 #define HWRM_TFC_TBL_SCOPE_QCAPS                  0x380UL
 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC               0x381UL
 #define HWRM_TFC_TBL_SCOPE_CONFIG                 0x382UL
 #define HWRM_TFC_TBL_SCOPE_DECONFIG               0x383UL
 #define HWRM_TFC_TBL_SCOPE_FID_ADD                0x384UL
 #define HWRM_TFC_TBL_SCOPE_FID_REM                0x385UL
 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC             0x386UL
 #define HWRM_TFC_TBL_SCOPE_POOL_FREE              0x387UL
 #define HWRM_TFC_SESSION_ID_ALLOC                 0x388UL
 #define HWRM_TFC_SESSION_FID_ADD                  0x389UL
 #define HWRM_TFC_SESSION_FID_REM                  0x38aUL
 #define HWRM_TFC_IDENT_ALLOC                      0x38bUL
 #define HWRM_TFC_IDENT_FREE                       0x38cUL
 #define HWRM_TFC_IDX_TBL_ALLOC                    0x38dUL
 #define HWRM_TFC_IDX_TBL_ALLOC_SET                0x38eUL
 #define HWRM_TFC_IDX_TBL_SET                      0x38fUL
 #define HWRM_TFC_IDX_TBL_GET                      0x390UL
 #define HWRM_TFC_IDX_TBL_FREE                     0x391UL
 #define HWRM_TFC_GLOBAL_ID_ALLOC                  0x392UL
 #define HWRM_TFC_TCAM_SET                         0x393UL
 #define HWRM_TFC_TCAM_GET                         0x394UL
 #define HWRM_TFC_TCAM_ALLOC                       0x395UL
 #define HWRM_TFC_TCAM_ALLOC_SET                   0x396UL
 #define HWRM_TFC_TCAM_FREE                        0x397UL
 #define HWRM_TFC_IF_TBL_SET                       0x398UL
 #define HWRM_TFC_IF_TBL_GET                       0x399UL
 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET             0x39aUL
 #define HWRM_TFC_RESC_USAGE_QUERY                 0x39bUL
 #define HWRM_TFC_GLOBAL_ID_FREE                   0x39cUL
 #define HWRM_TFC_TCAM_PRI_UPDATE                  0x39dUL
 #define HWRM_TFC_HOT_UPGRADE_PROCESS              0x3a0UL
 #define HWRM_SV                                   0x400UL
 #define HWRM_DBG_SERDES_TEST                      0xff0eUL
 #define HWRM_DBG_LOG_BUFFER_FLUSH                 0xff0fUL
 #define HWRM_DBG_READ_DIRECT                      0xff10UL
 #define HWRM_DBG_READ_INDIRECT                    0xff11UL
 #define HWRM_DBG_WRITE_DIRECT                     0xff12UL
 #define HWRM_DBG_WRITE_INDIRECT                   0xff13UL
 #define HWRM_DBG_DUMP                             0xff14UL
 #define HWRM_DBG_ERASE_NVM                        0xff15UL
 #define HWRM_DBG_CFG                              0xff16UL
 #define HWRM_DBG_COREDUMP_LIST                    0xff17UL
 #define HWRM_DBG_COREDUMP_INITIATE                0xff18UL
 #define HWRM_DBG_COREDUMP_RETRIEVE                0xff19UL
 #define HWRM_DBG_FW_CLI                           0xff1aUL
 #define HWRM_DBG_I2C_CMD                          0xff1bUL
 #define HWRM_DBG_RING_INFO_GET                    0xff1cUL
 #define HWRM_DBG_CRASHDUMP_HEADER                 0xff1dUL
 #define HWRM_DBG_CRASHDUMP_ERASE                  0xff1eUL
 #define HWRM_DBG_DRV_TRACE                        0xff1fUL
 #define HWRM_DBG_QCAPS                            0xff20UL
 #define HWRM_DBG_QCFG                             0xff21UL
 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG             0xff22UL
 #define HWRM_DBG_USEQ_ALLOC                       0xff23UL
 #define HWRM_DBG_USEQ_FREE                        0xff24UL
 #define HWRM_DBG_USEQ_FLUSH                       0xff25UL
 #define HWRM_DBG_USEQ_QCAPS                       0xff26UL
 #define HWRM_DBG_USEQ_CW_CFG                      0xff27UL
 #define HWRM_DBG_USEQ_SCHED_CFG                   0xff28UL
 #define HWRM_DBG_USEQ_RUN                         0xff29UL
 #define HWRM_DBG_USEQ_DELIVERY_REQ                0xff2aUL
 #define HWRM_DBG_USEQ_RESP_HDR                    0xff2bUL
 #define HWRM_DBG_COREDUMP_CAPTURE                 0xff2cUL
 #define HWRM_DBG_PTRACE                           0xff2dUL
 #define HWRM_DBG_SIM_CABLE_STATE                  0xff2eUL
 #define HWRM_NVM_GET_VPD_FIELD_INFO               0xffeaUL
 #define HWRM_NVM_SET_VPD_FIELD_INFO               0xffebUL
 #define HWRM_NVM_DEFRAG                           0xffecUL
 #define HWRM_NVM_REQ_ARBITRATION                  0xffedUL
 #define HWRM_NVM_FACTORY_DEFAULTS                 0xffeeUL
 #define HWRM_NVM_VALIDATE_OPTION                  0xffefUL
 #define HWRM_NVM_FLUSH                            0xfff0UL
 #define HWRM_NVM_GET_VARIABLE                     0xfff1UL
 #define HWRM_NVM_SET_VARIABLE                     0xfff2UL
 #define HWRM_NVM_INSTALL_UPDATE                   0xfff3UL
 #define HWRM_NVM_MODIFY                           0xfff4UL
 #define HWRM_NVM_VERIFY_UPDATE                    0xfff5UL
 #define HWRM_NVM_GET_DEV_INFO                     0xfff6UL
 #define HWRM_NVM_ERASE_DIR_ENTRY                  0xfff7UL
 #define HWRM_NVM_MOD_DIR_ENTRY                    0xfff8UL
 #define HWRM_NVM_FIND_DIR_ENTRY                   0xfff9UL
 #define HWRM_NVM_GET_DIR_ENTRIES                  0xfffaUL
 #define HWRM_NVM_GET_DIR_INFO                     0xfffbUL
 #define HWRM_NVM_RAW_DUMP                         0xfffcUL
 #define HWRM_NVM_READ                             0xfffdUL
 #define HWRM_NVM_WRITE                            0xfffeUL
 #define HWRM_NVM_RAW_WRITE_BLK                    0xffffUL
 #define HWRM_LAST                                HWRM_NVM_RAW_WRITE_BLK
 __le16 unused_0[3];
};

/* ret_codes (size:64b/8B) */
struct ret_codes {
 __le16 error_code;
 #define HWRM_ERR_CODE_SUCCESS                      0x0UL
 #define HWRM_ERR_CODE_FAIL                         0x1UL
 #define HWRM_ERR_CODE_INVALID_PARAMS               0x2UL
 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED       0x3UL
 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR         0x4UL
 #define HWRM_ERR_CODE_INVALID_FLAGS                0x5UL
 #define HWRM_ERR_CODE_INVALID_ENABLES              0x6UL
 #define HWRM_ERR_CODE_UNSUPPORTED_TLV              0x7UL
 #define HWRM_ERR_CODE_NO_BUFFER                    0x8UL
 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR       0x9UL
 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS           0xaUL
 #define HWRM_ERR_CODE_HOT_RESET_FAIL               0xbUL
 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
 #define HWRM_ERR_CODE_KEY_HASH_COLLISION           0xdUL
 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS           0xeUL
 #define HWRM_ERR_CODE_HWRM_ERROR                   0xfUL
 #define HWRM_ERR_CODE_BUSY                         0x10UL
 #define HWRM_ERR_CODE_RESOURCE_LOCKED              0x11UL
 #define HWRM_ERR_CODE_PF_UNAVAILABLE               0x12UL
 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT           0x13UL
 #define HWRM_ERR_CODE_SECURE_SOC_ERROR             0x14UL
 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE    0x8000UL
 #define HWRM_ERR_CODE_UNKNOWN_ERR                  0xfffeUL
 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED            0xffffUL
 #define HWRM_ERR_CODE_LAST                        HWRM_ERR_CODE_CMD_NOT_SUPPORTED
 __le16 unused_0[3];
};

/* hwrm_err_output (size:128b/16B) */
struct hwrm_err_output {
 __le16 error_code;
 __le16 req_type;
 __le16 seq_id;
 __le16 resp_len;
 __le32 opaque_0;
 __le16 opaque_1;
 u8 cmd_err;
 u8 valid;
};
#define HWRM_NA_SIGNATURE ((__le32)(-1))
#define HWRM_MAX_REQ_LEN 128
#define HWRM_MAX_RESP_LEN 704
#define HW_HASH_INDEX_SIZE 0x80
#define HW_HASH_KEY_SIZE 40
#define HWRM_RESP_VALID_KEY 1
#define HWRM_TARGET_ID_BONO 0xFFF8
#define HWRM_TARGET_ID_KONG 0xFFF9
#define HWRM_TARGET_ID_APE 0xFFFA
#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 3
#define HWRM_VERSION_RSVD 97
#define HWRM_VERSION_STR "1.10.3.97"

/* hwrm_ver_get_input (size:192b/24B) */
struct hwrm_ver_get_input {
 __le16 req_type;
 __le16 cmpl_ring;
 __le16 seq_id;
 __le16 target_id;
 __le64 resp_addr;
 u8 hwrm_intf_maj;
 u8 hwrm_intf_min;
 u8 hwrm_intf_upd;
 u8 unused_0[5];
};

/* hwrm_ver_get_output (size:1408b/176B) */
struct hwrm_ver_get_output {
 __le16 error_code;
 __le16 req_type;
 __le16 seq_id;
 __le16 resp_len;
 u8 hwrm_intf_maj_8b;
 u8 hwrm_intf_min_8b;
 u8 hwrm_intf_upd_8b;
 u8 hwrm_intf_rsvd_8b;
 u8 hwrm_fw_maj_8b;
 u8 hwrm_fw_min_8b;
 u8 hwrm_fw_bld_8b;
 u8 hwrm_fw_rsvd_8b;
 u8 mgmt_fw_maj_8b;
 u8 mgmt_fw_min_8b;
 u8 mgmt_fw_bld_8b;
 u8 mgmt_fw_rsvd_8b;
 u8 netctrl_fw_maj_8b;
 u8 netctrl_fw_min_8b;
 u8 netctrl_fw_bld_8b;
 u8 netctrl_fw_rsvd_8b;
 __le32 dev_caps_cfg;
 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED                  0x1UL
 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED                  0x2UL
 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED                      0x4UL
 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED                       0x8UL
 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED                   0x10UL
 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED              0x20UL
 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED     0x40UL
 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED         0x80UL
 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED                     0x100UL
 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED                     0x200UL
 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED              0x400UL
 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED                        0x800UL
 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED              0x1000UL
 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED                      0x2000UL
 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED                    0x4000UL
 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE                      0x8000UL
 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE                       0x10000UL
 u8 roce_fw_maj_8b;
 u8 roce_fw_min_8b;
 u8 roce_fw_bld_8b;
 u8 roce_fw_rsvd_8b;
 char hwrm_fw_name[16];
 char mgmt_fw_name[16];
 char netctrl_fw_name[16];
 char active_pkg_name[16];
 char roce_fw_name[16];
 __le16 chip_num;
 u8 chip_rev;
 u8 chip_metal;
 u8 chip_bond_id;
 u8 chip_platform_type;
 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC      0x0UL
 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA      0x1UL
 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST     VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
 __le16 max_req_win_len;
 __le16 max_resp_len;
 __le16 def_req_timeout;
 u8 flags;
 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY                   0x1UL
 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL                 0x2UL
 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE     0x4UL
 u8 unused_0[2];
 u8 always_1;
 __le16 hwrm_intf_major;
 __le16 hwrm_intf_minor;
 __le16 hwrm_intf_build;
 __le16 hwrm_intf_patch;
 __le16 hwrm_fw_major;
 __le16 hwrm_fw_minor;
 __le16 hwrm_fw_build;
 __le16 hwrm_fw_patch;
 __le16 mgmt_fw_major;
 __le16 mgmt_fw_minor;
 __le16 mgmt_fw_build;
 __le16 mgmt_fw_patch;
 __le16 netctrl_fw_major;
 __le16 netctrl_fw_minor;
 __le16 netctrl_fw_build;
 __le16 netctrl_fw_patch;
 __le16 roce_fw_major;
 __le16 roce_fw_minor;
 __le16 roce_fw_build;
 __le16 roce_fw_patch;
 __le16 max_ext_req_len;
 __le16 max_req_timeout;
 u8 unused_1[3];
 u8 valid;
};

/* eject_cmpl (size:128b/16B) */
struct eject_cmpl {
 __le16 type;
 #define EJECT_CMPL_TYPE_MASK       0x3fUL
 #define EJECT_CMPL_TYPE_SFT        0
 #define EJECT_CMPL_TYPE_STAT_EJECT   0x1aUL
 #define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT
 #define EJECT_CMPL_FLAGS_MASK      0xffc0UL
 #define EJECT_CMPL_FLAGS_SFT       6
 #define EJECT_CMPL_FLAGS_ERROR      0x40UL
 __le16 len;
 __le32 opaque;
 __le16 v;
 #define EJECT_CMPL_V                              0x1UL
 #define EJECT_CMPL_ERRORS_MASK                    0xfffeUL
 #define EJECT_CMPL_ERRORS_SFT                     1
 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        0xeUL
 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1
 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER     (0x0UL << 1)
 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (0x1UL << 1)
 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT    (0x3UL << 1)
 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH         (0x5UL << 1)
 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST         EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
 __le16 reserved16;
 __le32 unused_2;
};

/* hwrm_cmpl (size:128b/16B) */
struct hwrm_cmpl {
 __le16 type;
 #define CMPL_TYPE_MASK     0x3fUL
 #define CMPL_TYPE_SFT      0
 #define CMPL_TYPE_HWRM_DONE  0x20UL
 #define CMPL_TYPE_LAST      CMPL_TYPE_HWRM_DONE
 __le16 sequence_id;
 __le32 unused_1;
 __le32 v;
 #define CMPL_V     0x1UL
 __le32 unused_3;
};

/* hwrm_fwd_req_cmpl (size:128b/16B) */
struct hwrm_fwd_req_cmpl {
 __le16 req_len_type;
 #define FWD_REQ_CMPL_TYPE_MASK        0x3fUL
 #define FWD_REQ_CMPL_TYPE_SFT         0
 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ  0x22UL
 #define FWD_REQ_CMPL_TYPE_LAST         FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
 #define FWD_REQ_CMPL_REQ_LEN_MASK     0xffc0UL
 #define FWD_REQ_CMPL_REQ_LEN_SFT      6
 __le16 source_id;
 __le32 unused0;
 __le32 req_buf_addr_v[2];
 #define FWD_REQ_CMPL_V                0x1UL
 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
};

/* hwrm_fwd_resp_cmpl (size:128b/16B) */
struct hwrm_fwd_resp_cmpl {
 __le16 type;
 #define FWD_RESP_CMPL_TYPE_MASK         0x3fUL
 #define FWD_RESP_CMPL_TYPE_SFT          0
 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP  0x24UL
 #define FWD_RESP_CMPL_TYPE_LAST          FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
 __le16 source_id;
 __le16 resp_len;
 __le16 unused_1;
 __le32 resp_buf_addr_v[2];
 #define FWD_RESP_CMPL_V                 0x1UL
 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
};

/* hwrm_async_event_cmpl (size:128b/16B) */
struct hwrm_async_event_cmpl {
 __le16 type;
 #define ASYNC_EVENT_CMPL_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_TYPE_LAST             ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE              0x0UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE                 0x1UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE               0x2UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE               0x3UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED           0x4UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED      0x5UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE           0x6UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE             0x7UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY                    0x8UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY                  0x9UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG                0xaUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD                0x10UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD                  0x11UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT             0x12UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD                  0x20UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD                    0x21UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR                          0x30UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE              0x31UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE        0x32UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE                   0x33UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE                 0x34UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE             0x35UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED                    0x36UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION              0x37UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ             0x38UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE            0x39UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE          0x3aUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE                 0x3bUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE                  0x3cUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE       0x3dUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE        0x3eUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE                    0x3fUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE               0x40UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE         0x41UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST                    0x42UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE                      0x43UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP                   0x44UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT                    0x45UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD       0x46UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE                      0x47UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE       0x48UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR                       0x4aUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE             0x4bUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER                0x4cUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE                0x4dUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE         0x4eUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE                  0x4fUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP                   0x50UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID               0x51UL
 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG                    0xfeUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                      0xffUL
 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST                           ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_V          0x1UL
 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
};

/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
struct hwrm_async_event_cmpl_link_status_change {
 __le16 type;
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V          0x1UL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE     0x1UL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN  0x0UL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP    0x1UL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK       0xeUL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT        1
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK    0xffff0UL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT     4
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK      0xff00000UL
 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT       20
};

/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
struct hwrm_async_event_cmpl_port_conn_not_allowed {
 __le16 type;
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V          0x1UL
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK                 0xffffUL
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT                  0
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK      0xff0000UL
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT       16
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE        (0x0UL << 16)
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (0x1UL << 16)
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG  (0x2UL << 16)
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN     (0x3UL << 16)
 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST       ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
};

/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
struct hwrm_async_event_cmpl_link_speed_cfg_change {
 __le16 type;
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V          0x1UL
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK                     0xffffUL
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT                      0
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE     0x10000UL
 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG           0x20000UL
};

/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
struct hwrm_async_event_cmpl_reset_notify {
 __le16 type;
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST             ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST        ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
 __le32 event_data2;
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V          0x1UL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK                  0xffUL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT                   0
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE    0x1UL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN           0x2UL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST                   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK                    0xff00UL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT                     8
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST  (0x1UL << 8)
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL        (0x2UL << 8)
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL    (0x3UL << 8)
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET                (0x4UL << 8)
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION             (0x5UL << 8)
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST                     ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK           0xffff0000UL
 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT            16
};

/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
struct hwrm_async_event_cmpl_error_recovery {
 __le16 type;
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST          ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V          0x1UL
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK                 0xffUL
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT                  0
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC           0x1UL
 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED      0x2UL
};

/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
struct hwrm_async_event_cmpl_ring_monitor_msg {
 __le16 type;
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST             ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST            ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
 __le32 event_data2;
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX    0x0UL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX    0x1UL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL  0x2UL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V          0x1UL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
};

/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
struct hwrm_async_event_cmpl_vf_cfg_change {
 __le16 type;
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST         ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
 __le32 event_data2;
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V          0x1UL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE                0x1UL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE                0x2UL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE      0x4UL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE          0x8UL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE     0x10UL
 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE      0x20UL
};

/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
struct hwrm_async_event_cmpl_default_vnic_change {
 __le16 type;
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK         0xffc0UL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT          6
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST                   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V          0x1UL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK          0x3UL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT           0
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC  0x1UL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   0x2UL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST           ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK                   0x3fcUL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT                    2
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK                   0x3fffc00UL
 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT                    10
};

/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
struct hwrm_async_event_cmpl_hw_flow_aged {
 __le16 type;
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST             ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST        ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          0x1UL
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK       0x7fffffffUL
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT        0
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION     0x80000000UL
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX    (0x0UL << 31)
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX    (0x1UL << 31)
 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
};

/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
struct hwrm_async_event_cmpl_eem_cache_flush_req {
 __le16 type;
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST               ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V          0x1UL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
};

/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
struct hwrm_async_event_cmpl_eem_cache_flush_done {
 __le16 type;
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST                ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V          0x1UL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
};

/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
struct hwrm_async_event_cmpl_deferred_response {
 __le16 type;
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST             ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
 __le32 event_data2;
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V          0x1UL
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
};

/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
struct hwrm_async_event_cmpl_echo_request {
 __le16 type;
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST             ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
 __le32 event_data2;
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V          0x1UL
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
};

/* hwrm_async_event_cmpl_phc_update (size:128b/16B) */
struct hwrm_async_event_cmpl_phc_update {
 __le16 type;
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK            0x3fUL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT             0
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST             ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT
 __le16 event_id;
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST      ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE
 __le32 event_data2;
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK   0xffff0000UL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT    16
 u8 opaque_v;
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V          0x1UL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1
 u8 timestamp_lo;
 __le16 timestamp_hi;
 __le32 event_data1;
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK          0xfUL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT           0
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER      0x1UL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY   0x2UL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER    0x3UL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE  0x4UL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST           ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK   0xffff0UL
 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT    4
};

/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
struct hwrm_async_event_cmpl_pps_timestamp {
 __le16 type;
 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK            0x3fUL
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