// SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (c) by Jaroslav Kysela <perex@perex.cz> * Lee Revell <rlrevell@joe-job.com> * James Courtier-Dutton <James@superbug.co.uk> * Oswald Buddenhagen <oswald.buddenhagen@gmx.de> * Creative Labs, Inc. * * Routines for control of EMU10K1 chips
*/
int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsignedint data)
{ unsignedint reset, set; unsignedint reg, tmp; int n, result; int err = 0;
/* This function is not re-entrant, so protect against it. */
spin_lock(&emu->spi_lock); if (emu->card_capabilities->ca0108_chip)
reg = P17V_SPI; else { /* For other chip types the SPI register
* is currently unknown. */
err = 1; goto spi_write_exit;
} if (data > 0xffff) { /* Only 16bit values allowed */
err = 1; goto spi_write_exit;
}
tmp = snd_emu10k1_ptr20_read(emu, reg, 0);
reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */
set = reset | 0x10000; /* Set xxx1xxxx */
snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */
snd_emu10k1_ptr20_write(emu, reg, 0, set | data);
result = 1; /* Wait for status bit to return to 0 */ for (n = 0; n < 100; n++) {
udelay(10);
tmp = snd_emu10k1_ptr20_read(emu, reg, 0); if (!(tmp & 0x10000)) {
result = 0; break;
}
} if (result) { /* Timed out */
err = 1; goto spi_write_exit;
}
snd_emu10k1_ptr20_write(emu, reg, 0, reset | data);
tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */
err = 0;
spi_write_exit:
spin_unlock(&emu->spi_lock); return err;
}
/* The ADC does not support i2c read, so only write is implemented */ int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu,
u32 reg,
u32 value)
{
u32 tmp; int timeout = 0; int status; int retry; int err = 0;
/* This function is not re-entrant, so protect against it. */
spin_lock(&emu->i2c_lock);
tmp = reg << 25 | value << 16;
/* This controls the I2C connected to the WM8775 ADC Codec */
snd_emu10k1_ptr20_write(emu, P17V_I2C_1, 0, tmp);
tmp = snd_emu10k1_ptr20_read(emu, P17V_I2C_1, 0); /* write post */
for (retry = 0; retry < 10; retry++) { /* Send the data to i2c */
tmp = 0;
tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD);
snd_emu10k1_ptr20_write(emu, P17V_I2C_ADDR, 0, tmp);
/* Wait till the transaction ends */ while (1) {
mdelay(1);
status = snd_emu10k1_ptr20_read(emu, P17V_I2C_ADDR, 0);
timeout++; if ((status & I2C_A_ADC_START) == 0) break;
if (timeout > 1000) {
dev_warn(emu->card->dev, "emu10k1:I2C:timeout status=0x%x\n",
status); break;
}
} //Read back and see if the transaction is successful if ((status & I2C_A_ADC_ABORT) == 0) break;
}
staticvoid snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value)
{ if (snd_BUG_ON(reg > 0x3f)) return;
reg += 0x40; /* 0x40 upwards are registers. */ if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */ return;
outw(reg, emu->port + A_GPIO);
udelay(10);
outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
udelay(10);
outw(value, emu->port + A_GPIO);
udelay(10);
outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
udelay(10);
}
void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value)
{ // The higest input pin is used as the designated interrupt trigger, // so it needs to be masked out. // But note that any other input pin change will also cause an IRQ, // so using this function often causes an IRQ as a side effect.
u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f;
if (snd_BUG_ON(!mutex_is_locked(&emu->emu1010.lock))) return; if (snd_BUG_ON(reg > 0x3f)) return;
reg += 0x40; /* 0x40 upwards are registers. */
outw(reg, emu->port + A_GPIO);
udelay(10);
outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */
udelay(10);
*value = ((inw(emu->port + A_GPIO) >> 8) & mask);
}
/* Each Destination has one and only one Source, * but one Source can feed any number of Destinations simultaneously.
*/ void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src)
{ if (snd_BUG_ON(dst & ~0x71f)) return; if (snd_BUG_ON(src & ~0x71f)) return;
snd_emu1010_fpga_write(emu, EMU_HANA_DESTHI, dst >> 8);
snd_emu1010_fpga_write(emu, EMU_HANA_DESTLO, dst & 0x1f);
snd_emu1010_fpga_write(emu, EMU_HANA_SRCHI, src >> 8);
snd_emu1010_fpga_write(emu, EMU_HANA_SRCLO, src & 0x1f);
}
switch (src) { case EMU_HANA_WCLOCK_HANA_SPDIF_IN:
snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &value); if (value & EMU_HANA_SPDIF_MODE_RX_INVALID) return 0;
reg_lo = EMU_HANA_WC_SPDIF_LO;
reg_hi = EMU_HANA_WC_SPDIF_HI; break; case EMU_HANA_WCLOCK_HANA_ADAT_IN:
reg_lo = EMU_HANA_WC_ADAT_LO;
reg_hi = EMU_HANA_WC_ADAT_HI; break; case EMU_HANA_WCLOCK_SYNC_BNC:
reg_lo = EMU_HANA_WC_BNC_LO;
reg_hi = EMU_HANA_WC_BNC_HI; break; case EMU_HANA_WCLOCK_2ND_HANA:
reg_lo = EMU_HANA2_WC_SPDIF_LO;
reg_hi = EMU_HANA2_WC_SPDIF_HI; break; default: return 0;
}
snd_emu1010_fpga_read(emu, reg_hi, &value);
snd_emu1010_fpga_read(emu, reg_lo, &value2); // FIXME: The /4 is valid for 0404b, but contradicts all other info. return 0x1770000 / 4 / (((value << 5) | value2) + 1);
}
void snd_emu1010_update_clock(struct snd_emu10k1 *emu)
{ int clock;
u32 leds;
switch (emu->emu1010.wclock) { case EMU_HANA_WCLOCK_INT_44_1K | EMU_HANA_WCLOCK_1X:
clock = 44100;
leds = EMU_HANA_DOCK_LEDS_2_44K; break; case EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_1X:
clock = 48000;
leds = EMU_HANA_DOCK_LEDS_2_48K; break; default:
clock = snd_emu1010_get_raw_rate(
emu, emu->emu1010.wclock & EMU_HANA_WCLOCK_SRC_MASK); // The raw rate reading is rather coarse (it cannot accurately // represent 44.1 kHz) and fluctuates slightly. Luckily, the // clock comes from digital inputs, which use standardized rates. // So we round to the closest standard rate and ignore discrepancies. if (clock < 46000) {
clock = 44100;
leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_44K;
} else {
clock = 48000;
leds = EMU_HANA_DOCK_LEDS_2_EXT | EMU_HANA_DOCK_LEDS_2_48K;
} break;
}
emu->emu1010.word_clock = clock;
// FIXME: this should probably represent the AND of all currently // used sources' lock status. But we don't know how to get that ...
leds |= EMU_HANA_DOCK_LEDS_2_LOCK;
// On E-MU 1010 rev1 the FPGA is a Xilinx Spartan IIE XC2S50E. // On E-MU 0404b it is a Xilinx Spartan III XC3S50. // The wiring is as follows: // GPO7 -> FPGA input & 1K resistor -> FPGA /PGMN <- FPGA output // In normal operation, the active low reset line is held up by // an FPGA output, while the GPO pin performs its duty as control // register access strobe signal. Writing the respective bit to // EMU_HANA_FPGA_CONFIG puts the FPGA output into high-Z mode, at // which point the GPO pin can control the reset line through the // resistor. // GPO6 -> FPGA CCLK & FPGA input // GPO5 -> FPGA DIN (dual function)
// If the FPGA is already programmed, return it to programming mode
snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG,
dock ? EMU_HANA_FPGA_CONFIG_AUDIODOCK :
EMU_HANA_FPGA_CONFIG_HANA);
// Upload the netlist. Keep reset line high! for (int n = 0; n < fw_entry->size; n++) {
u8 value = fw_entry->data[n]; for (int i = 0; i < 8; i++) {
u16 reg = 0x80; if (value & 1)
reg |= 0x20;
value >>= 1;
outw(reg, emu->port + A_GPIO);
write_post = inw(emu->port + A_GPIO);
outw(reg | 0x40, emu->port + A_GPIO);
write_post = inw(emu->port + A_GPIO);
}
}
// After programming, set GPIO bit 4 high again. // This appears to be a config word that the rev1 Hana // firmware reads; weird things happen without this.
outw(0x10, emu->port + A_GPIO);
write_post = inw(emu->port + A_GPIO);
}
soll &= (u32)~voices;
solh &= (u32)(~voices >> 32);
for (int tries = 0; tries < 1000; tries++) { const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2); // First we wait for the third quarter of the sample cycle ...
u32 wc = inl(emu->port + WC);
u32 cc = REG_VAL_GET(WC_CURRENTCHANNEL, wc); if (cc >= quart * 2 && cc < quart * 3) { // ... and release the low voices, while the high ones are serviced.
outl(SOLEL << 16, emu->port + PTR);
outl(soll, emu->port + DATA); // Then we wait for the first quarter of the next sample cycle ... for (; tries < 1000; tries++) {
cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC)); if (cc < quart) goto good; // We will block for 10+ us with interrupts disabled. This is // not nice at all, but necessary for reasonable reliability.
udelay(1);
} break;
good: // ... and release the high voices, while the low ones are serviced.
outl(SOLEH << 16, emu->port + PTR);
outl(solh, emu->port + DATA); // Finally we verify that nothing interfered in fact. if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) ==
((REG_VAL_GET(WC_SAMPLECOUNTER, wc) + 1) & REG_MASK0(WC_SAMPLECOUNTER))) {
ret = 0;
} else {
ret = -EAGAIN;
} break;
} // Don't block for too long
spin_unlock_irqrestore(&emu->emu_lock, flags);
udelay(1);
spin_lock_irqsave(&emu->emu_lock, flags);
}
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